Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on January 2nd, 2025
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on January 2nd, 2025
Taiwan Semiconductor Manufacturing Company, Ltd.: 47 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (17), H01L29/06 (15), H01L29/423 (13), H01L29/775 (10), H01L23/00 (9) H01L29/775 (3), H01L21/823481 (3), H01L25/0657 (2), H01L27/0886 (2), H01L29/66545 (2)
With keywords such as: layer, structure, gate, dielectric, semiconductor, forming, drain, source, device, and transistor in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Wei-Ming WANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chen CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao YU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Peng TAI of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/13
CPC Code(s): G02B6/13
Abstract: a method of forming a semiconductor package is provided. the method includes forming a first wafer that includes multiple photonic dies. the method includes forming a second wafer that includes multiple electronic dies. the method includes forming micro lenses within the second wafer. the method includes bonding the first wafer to the second wafer after forming the plurality of micro lenses. the method further includes performing a singulation process to dice the first wafer and the second wafer to form multiple photonic packages, wherein one of the photonic packages includes an electronic die, a photonic die bonded to the electronic die, and one or more micro lenses embedded in the electronic die.
Inventor(s): Kenji YAMAZOE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Shiang CHOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G03F1/70, H01L21/033
CPC Code(s): G03F7/705
Abstract: a process for forming a photolithography mask includes generating a sub-resolution assist feature (sraf) pattern from a blank mask layout based on a target layout. the sraf pattern can be generated using an iterative process including finding the gradient of a cost function. a main pattern can be generated simultaneously with the sraf pattern or after generation of the sraf pattern.
Inventor(s): Sachin Kumar of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G05B19/4099
CPC Code(s): G05B19/4099
Abstract: a method of fabricating an integrated circuit using spare cells is provided. the method comprises receiving an input design and generating a design layout comprising a plurality of functional cells and a plurality of spare cells, wherein the plurality of spare cells comprises a plurality of pins. a plurality of flexible pin extensions are also generated to connect to pins of the plurality of spare cells, wherein the plurality of flexible pin extensions include a plurality of segments formed on different layer levels of the design layout. a routing is performed to interconnect functional cells in the design layout thereby generating a routed design, and an integrated circuit is fabricated according to the routed design.
Inventor(s): CHUNG-HSING WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ping Hsiu WEI of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chung CHEN of Keelung (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Sheng YUAN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Kan CHENG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/3308, G06F30/394, G06F30/398
CPC Code(s): G06F30/3308
Abstract: a computer-implemented method includes: placing and routing design elements in a simulation environment; applying one or more simulation conditions to the design elements; obtaining a first set of data based on the one or more simulation conditions, and a first relationship between the first set of data; obtaining a prediction model based on the first relationship; and predicting a new set of data using the prediction model.
Inventor(s): Kai Fai CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Johnny Chiahao LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Min TSENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hsien WEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jerry Chang Jui KAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/398, G06F30/392, G06F30/3953, H01L23/528
CPC Code(s): G06F30/398
Abstract: a system includes a processor for performing a thermal analysis for an ic layout, which includes a redistribution structure having a plurality of conductive layers stacked one upon another in a thickness direction. in response to a property of a first conductive layer satisfying a first condition, the processor applies a first modeling rule to the first conductive layer to obtain a first model, and, in response to the property of a second conductive layer satisfying a second condition but not the first condition, the processor applies a second modeling rule different from the first modeling rule to the second conductive layer to obtain a second model. the processor performs a thermal simulation for the ic layout based on the first and second models, and, based on the thermal simulation result, modifies the ic layout or proceeds with manufacturing one or more ic devices corresponding to the ic layout.
Inventor(s): Wei-Xiang YOU of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yin WANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya LIAO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/412, H10B10/00
CPC Code(s): G11C11/4125
Abstract: a semiconductor device includes a first memory cell and a second memory cell. the first memory cell is configured to store a first data bit at a first node when the first memory cell is turned on. the second memory cell is configured to store the first data bit when the first memory cell is turned off. the first memory cell comprises a first switch coupled to the first node, and the first switch is configured to transmit the first data bit to the second memory cell, and configured to be turned off when the first memory cell is turned off.
Inventor(s): Tsung-Hsien Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Jer Hsieh of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yuan Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hao Hsu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/418
CPC Code(s): G11C11/418
Abstract: a memory device and a method of operating the memory device are disclosed. in one aspect, the memory device includes a word line driver connected to a word line, a row of memory cells connected to the word line, each memory cell powered by a first supply voltage, and a power circuit. the power circuit is configured to provide the first supply voltage to the word line driver when a read condition is satisfied, and a second supply voltage to the word line driver when the read condition is not satisfied, the second supply voltage being less than the first supply voltage.
Inventor(s): Sanjeev Kumar Jain of OTTAWA (CA) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419
CPC Code(s): G11C11/419
Abstract: a memory cell is configured to store data and operate in an operational state or a sleep state. a first set of transistors is configured to transfer data from the data sensing node of the memory cell to a data latch node, in response to the memory cell being in the operational state. a second set of transistors is configured to latch the data at the data latch node, in response to the memory cell being in the operational state. a third set of transistors is configured to latch the data at the data latch node, in response to the memory cell being in the sleep state. the first set of transistors is further configured to transfer the data from the data latch node to the data sensing node of the memory cell, in response to the memory cell being transitioned from the sleep state to the operational state.
Inventor(s): Meng-Sheng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Jen YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C17/16, G11C17/18
CPC Code(s): G11C17/16
Abstract: a semiconductor device and a method for manufacturing the semiconductor device are provided. the semiconductor device includes a first transistor, the second transistor, a first circuit, a second circuit and a third transistor. the second transistor is electrically connected to the first transistor, wherein gates of the first transistor and the second transistor are electrically connected to a word line. the first circuit is electrically connected between a drain of the first transistor and a first bit line. the second circuit is electrically connected between a drain of the second transistor and a second bit line. the third transistor is electrically connected between the drain of the first transistor and the drain of the second transistor.
Inventor(s): Ya-Lan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Gang Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tai-Chun Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Cheng Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L21/02, H01L21/3105, H01L21/762, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/66, H01L29/78
CPC Code(s): H01L21/28123
Abstract: an embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.
Inventor(s): Tzu-Hsiang HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sun-Yi CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H. CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/311, H01L21/3105, H01L21/768, H01L27/088
CPC Code(s): H01L21/31144
Abstract: a method for manufacturing a semiconductor structure includes: forming an interconnect level structure having a first device region, a first side region aside the first device region, a second device region and a second side region aside the second device region; forming a dielectric layer over the interconnect structure, the dielectric layer including a first dielectric portion, a second dielectric portion, a first patterned portion and a second patterned portion that are respectively formed over the first device region, the second device region, the first side region, and the second side region, the first patterned portion and the second patterned portion being formed with different patterns; performing a planarization process on the dielectric layer; forming first recesses and second recesses respectively in the planarized first dielectric portion and the planarized second dielectric portion; and forming contact portion respectively in the first recesses and the second recesses.
Inventor(s): Hsien-Chih HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Lin CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shi Ning JU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L29/06, H01L29/423, H01L29/66
CPC Code(s): H01L21/76229
Abstract: an integrated circuit includes a transistor including a plurality of stacked channels. a first dielectric wall structure is positioned on a first lateral side of the stacked channels. a second dielectric wall structure is positioned on a second lateral side of the stacked channels. a dielectric home structure is positioned above the top channel. a gate electrode includes a vertical column extending vertically between the second dielectric wall structure and the stacked channels. the gate electrode includes finger portions extending laterally from the vertical column between the stacked channels.
Inventor(s): Yen-Ru Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chii-Horng Li of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-I Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Li Su of ChuBei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chang Su of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Heng-Wen Ting of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Chi Tai of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Hui Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Wei Li of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/764, H01L29/06, H01L29/08, H01L29/16, H01L29/161, H01L29/165, H01L29/24, H01L29/66, H01L29/78
CPC Code(s): H01L21/764
Abstract: an embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.
Inventor(s): Cheng-Hsiang Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yang Hsieh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chang Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Tung Chuang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/00, H01L23/48, H01L25/065
CPC Code(s): H01L21/76849
Abstract: semiconductor structures and fabrication methods are provided. in one example, a method includes forming a first dielectric layer on a semiconductor structure. the semiconductor structure includes a substrate and a multi-layer interconnect (mli) structure on the substrate. the mli structure includes multiple metallization layers. the first dielectric layer is formed on a topmost metallization layer. the method further includes forming a through-substrate-via (tsv) opening extending vertically through the first dielectric layer and the multiple metallization layers into the substrate, forming a tsv in the tsv opening, performing a first planarization process to planarize the tsv, forming multiple first metal vias and first metal lines in the first dielectric layer after the first planarization process, forming multiple first metal capping layers respectively on the multiple first metal lines, and performing a second planarization process to planarize the first metal capping layers.
Inventor(s): Po-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chieh Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., I-Wen Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ming Lee of Yangmei City (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Yun Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/285, H01L21/74, H01L23/522, H01L23/528
CPC Code(s): H01L21/823418
Abstract: an exemplary device includes a frontside power rail disposed over a frontside of a substrate, a backside power rail disposed over a backside of the substrate, an epitaxial source/drain structure disposed between the frontside power rail and the backside power rail. the epitaxial source/drain structure is connected to the frontside power rail by a frontside source/drain contact. the epitaxial source/drain structure is connected to the backside power rail by a backside source/drain via. the backside source/drain via is disposed in a substrate, and a dielectric layer is disposed between the substrate and the backside power rail. the backside source/drain via extends through the dielectric layer and the substrate. a frontside silicide layer may be between the frontside source/drain contact and the epitaxial source/drain structure, and a backside silicide layer may be between the backside source/drain contact and the epitaxial source/drain structure, such that the epitaxial source/drain structure between silicide layers.
Inventor(s): Yu-Lung TUNG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Xiaodong Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L21/823481
Abstract: a method includes forming first, second, third, fourth, fifth, and sixth channel patterns on a semiconductor substrate; forming a first isolation wall interposing the first and second channel patterns, a second isolation wall interposing the third and fourth channel patterns, wherein the first isolation wall further continuously extends to interpose the fifth and sixth channel patterns; forming a first gate pattern extending across the first, second, third, and fourth channel patterns and the first and second isolation walls, and a second gate pattern extending across the fifth and sixth channel patterns and the first isolation wall from the top view, wherein the first, second, third, fourth, and sixth channel patterns respectively have first, second, third, fourth, and sixth dimensions in a lengthwise direction of the first gate pattern, and the sixth dimension is greater than the first, second, third, and fourth dimensions.
Inventor(s): Siao-Jing Li of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L21/823481
Abstract: semiconductor structures and methods are provided. an exemplary method according to the present disclosure includes forming a first and a second fin-shaped active region over a substrate, the first and second fin-shaped active regions extending lengthwise along a first direction, forming a gate structure over channel regions of the first and second fin-shaped active regions, the gate structure extending lengthwise along a second direction substantially perpendicular to the first direction, forming a trench to separate the gate structure into two segments, the trench extending lengthwise along the first direction and being disposed between the first and second fin-shaped active regions, performing an etching process to enlarge an upper portion of the trench, and forming a gate isolation structure in the trench, and, in a cross-sectional view cut through both the first and second fin-shaped active regions and the gate structure, the gate isolation structure is a t-shape structure.
Inventor(s): Chieh-Ping Wang of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Gang Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Cyuan Lu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tai-Chun Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L21/28, H01L21/311, H01L21/762, H01L21/764, H01L27/088, H01L29/06, H01L29/66, H01L29/78
CPC Code(s): H01L21/823481
Abstract: a method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.
Inventor(s): Kuan-Kan HU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Che Chi SHIH of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ku-Feng YANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Szuya LIAO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/285, H01L21/3065, H01L21/822, H01L27/092, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L21/823814
Abstract: method to form low-contact-resistance contacts to source/drain features is provided. a method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, lateral epitaxial structures etching on the n-type source/drain feature creating the offset from the sidewall of the dielectric layer, depositing a silicide layer and the offset between etched epitaxial structures and sidewall of the dielectric layer is eliminated. the lateral epitaxial structures etching includes a reactive-ion etching (rie) process and an atomic layer etching (ale) process.
Inventor(s): Cheng-Hsiang Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yang Hsieh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chang Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Tung Chuang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, H01L23/00, H01L25/065
CPC Code(s): H01L22/32
Abstract: semiconductor structures, die stack structures, and fabrication methods are provided. in one example, a semiconductor structure includes a die having a test pad disposed on a front side of the die. the test pad has a probe mark in an upper portion of the test pad. the probe mark has an open end at a top surface of the test pad, a bottom wall, a sidewall connected to the bottom wall, and a space between the open end, the bottom wall and the sidewall. the semiconductor structure further includes a first cover layer and a second cover layer. the first cover layer is disposed on the front side of the first test pad and the sidewall and the bottom wall of the probe mark. the second cover layer is disposed on the first cover layer. the first and second cover layers comprise different materials.
Inventor(s): Kuo-Chiang Ting of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ta Hao Sung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Yan Jhu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/42, H01L21/56, H01L23/00, H01L23/31, H01L25/10
CPC Code(s): H01L23/42
Abstract: a semiconductor package with a dummy die having two layers with different thermal conductivities and the method of forming the same are provided. the semiconductor package may include a first semiconductor die, a first bonding layer on the first semiconductor die, a second semiconductor die bonded to the first bonding layer, and a first dummy die bonded to the first bonding layer. the first dummy die may include a substrate, a material layer between the substrate and the first bonding layer, and a second bonding layer between the material layer and the first bonding layer. the material layer may include a first material with a first thermal conductivity and the second bonding layer may include a second material with a second thermal conductivity different from the first thermal conductivity.
Inventor(s): Chi-Yuan KUO of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Heng ZHU of Chiayi County (TW) for taiwan semiconductor manufacturing company, ltd., I-Chih NI of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-I WU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/768
CPC Code(s): H01L23/53276
Abstract: a method includes loading a wafer having a dielectric layer thereon into a processing chamber; introducing a hydrocarbon precursor into the processing chamber; pyrolyzing the hydrocarbon precursor; introducing the pyrolyzed hydrocarbon precursor to the dielectric layer to form a graphene layer on the dielectric layer at a temperature lower than about 400� c.
Inventor(s): Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L23/00, H01L23/498, H01L25/16
CPC Code(s): H01L23/5381
Abstract: a semiconductor package and a manufacturing method thereof are provided. the semiconductor package includes a first device die and a second device die; an encapsulant, laterally encapsulating the first and second device dies; a bridge die, electrically connected to the first and second device dies and establishing communication between the first and second device dies; and bonding layers, between the first and second device dies and the bridge die, and including a first die bonding layer and a second die bonding layer respectively disposed upon the first device die and the second device die, and a third die bonding layer disposed upon the bridge die. each of the bonding layers includes a polymer layer and metallic features embedded in the polymer layer.
Inventor(s): Wen-Shiang LIAO of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/66, H01L23/00, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L23/66
Abstract: a package structure and a formation method are provided. the package structure includes a chip structure bonded to a substrate through dielectric-to-dielectric bonding and metal-to-metal bonding and interconnect dielectric layers formed over the chip structure. the package structure further includes interconnect conductive structures formed in the interconnect dielectric layers and a transmission line formed in the interconnect dielectric layers. the package structure further includes a magnetic structure formed in the interconnect dielectric layers and separated from the transmission line by the interconnect dielectric layers. in addition, the magnetic structure is electrically isolated from the chip structure and the interconnect conductive structures.
Inventor(s): Ming-Tsu Chung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chi Lin of Su-Lin City (TW) for taiwan semiconductor manufacturing company, ltd., Yan-Zuo Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/08
Abstract: a method includes depositing a first dielectric layer as a first surface layer of a first package component, forming a plurality of metal pads in the first dielectric layer, depositing a second dielectric layer as a second surface layer of a second package component, and bonding the second package component to the first package component. the first dielectric layer is bonded to the second dielectric layer. at a time after the bonding, a metal pad in the plurality of metal pads has a top surface contacting a bottom surface of the second dielectric layer.
Inventor(s): Zheng-Yong Liang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ting Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Han-De Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Fong Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Yun Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Chu Lin of Ping-Tung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/373
CPC Code(s): H01L24/29
Abstract: an integrated circuit die with two material layers having metal nano-particles and the method of forming the same are provided. the integrated circuit die includes a device layer comprising a first transistor, a first interconnect structure on a first side of the device layer, a first material layer on the first interconnect structure, wherein the first material layer comprises first metal nano-particles, and a second material layer bonded to the first material layer, wherein the second material layer comprises second metal nano-particles, and wherein the first material layer and the second material layer share an interface.
Inventor(s): Chen-Sheng Lin of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ning Jiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Wen Shih of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chiang Ting of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ming Chen of Hsin-Chu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L21/78, H01L23/00, H01L23/48, H01L23/58
CPC Code(s): H01L25/0657
Abstract: a stacking structure including a first die and a second die bonded with the first die is provided. the first die has a first region and a second region encircled by the first region. the first die includes first metallization structures having a first seal ring structure and a first bonding structure having first dummy pads located over the first seal ring structure. the second die includes second metallization structures having a second seal ring structure and a second bonding structure having second dummy pads located over the second seal ring structure. the first die and the second die are bonded through bonding of the first and second bonding structures. the first and second seal ring structures are substantially vertically aligned, and the first dummy pads are respectively bonded with the second dummy pads.
Inventor(s): Chi-Yi Chuang of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Hou-Yu Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/528, H01L25/00, H01L29/06, H01L29/423, H01L29/45, H01L29/786
CPC Code(s): H01L25/0657
Abstract: methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. in an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.
Inventor(s): Kau-Chu LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chan-yu HUNG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Fei-Yun CHEN of Hinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L29/66, H01L29/78
CPC Code(s): H01L27/0886
Abstract: a high voltage transistor may include a plurality of source/drain regions, a gate structure, and a gate oxide layer that enables the gate structure to selectively control a channel region between the source/drain regions. the gate oxide layer may extend laterally outward toward one or more of the plurality of source/drain regions such that at least a portion of the gate oxide layer is not under the gate structure. the gate oxide layer extending laterally outward from under the gate structure enables the gate oxide layer to be used as a self-aligned structure for forming the source/drain regions of the high voltage transistor. in particular, the gate oxide layer extending laterally outward from under the gate structure enables the gate oxide layer to be used to form the source/drain regions at a greater spacing from the gate structure without the use of additional implant masks when forming the source/drain regions.
Inventor(s): Chia-Yi Wu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234
CPC Code(s): H01L27/0886
Abstract: semiconductor devices and fabrication methods are provided. in one example, a semiconductor device includes: a substrate, a fin formed on the substrate, a gate structure formed on the fin, a metal contact formed on the fin and adjacent to the gate structure. the fin extends along a first horizontal direction, the gate structure and the metal contact extend along a second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction. the gate structure further includes a gate electrode coupled to the fin and a dielectric gate isolation section separated from the gate electrode. the dielectric gate isolation section includes a dielectric material. a portion of the dielectric gate isolation section is aligned with a portion of the metal contact adjacent and proximate to the dielectric gate isolation section in the first horizontal direction.
Inventor(s): Cheng-Ming Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-I Wu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Kai Chiu of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yen Woon of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/822, H01L21/8238, H01L29/06, H01L29/423, H01L29/49, H01L29/66, H01L29/775
CPC Code(s): H01L27/0922
Abstract: a method of forming a complementary field-effect transistor (cfet) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurality of channel regions.
Inventor(s): Chun-Hsuan WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/12, H01L21/84
CPC Code(s): H01L27/12
Abstract: an integrated circuit device includes a first semiconductor layer, a second semiconductor layer, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a first contact plug. the second semiconductor layer is above the first semiconductor layer. the first and second semiconductor layers are vertically spaced apart from each other. the first source/drain epitaxial structure is on a side of the first semiconductor layer. the second source/drain epitaxial structure is on a side of the second semiconductor layer and above the first source/drain epitaxial structure. the first source/drain epitaxial structure has a portion extending beyond a sidewall of the second source/drain epitaxial structure from a top view. the first contact plug is over a frontside of the first source/drain epitaxial structure. the first contact plug overlaps the portion of the first source/drain epitaxial structure from the top view.
Inventor(s): Yuting CHENG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu Pei CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Kan HU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shao-An WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Hao CHANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/12, H01L21/84
CPC Code(s): H01L27/1207
Abstract: a semiconductor device that has two transistors and a source/drain contact. the first transistor has a layer of semiconductor material that acts as a channel, a structure that serves as a gate and wraps around the semiconductor channel layer, and two epitaxy structures on either end of the semiconductor channel layer that function as the source and drain. the second transistor is situated above the first transistor and has similar components, including a semiconductor channel layer, gate structure, and source/drain epitaxy structures. the connection between the first and second source/drain epitaxy structures is made by a source/drain contact that passes through one of the second source/drain epitaxy structures. this contact is made up of a metal plug and a metal liner that lines the plug.
Inventor(s): Chun-Heng Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yuan Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Li Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Fen Huang of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Tuo-Hsin Chien of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chi Chang of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01C17/075, H01C7/00, H01L23/522
CPC Code(s): H01L28/24
Abstract: resistors and method of forming the same are provided. a device structure according to the present disclosure includes a substrate, a first intermetal dielectric (imd) layer over the substrate, a resistor that includes a first resistor layer over the first imd layer, a second resistor layer over the first resistor layer, and a third resistor layer over the second resistor layer, a second imd layer over the first imd layer and the resistor, a first contact via extending through the second imd layer and the third resistor layer and terminating in the first resistor layer, and a second contact via extending through the second imd layer and the third resistor layer and terminating in the first resistor layer.
Inventor(s): Bo-Jiun LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-En LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tung Ying LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Ching CHENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L29/49, H01L29/66, H10K10/46
CPC Code(s): H01L29/401
Abstract: a method of forming a semiconductor device comprises the following steps. a dielectric layer is formed over a substrate. a 2d material layer is formed over the dielectric layer. an adhesion layer is formed over the 2d material layer. source/drain electrodes are formed on opposite sides of the adhesion layer. a first high-k gate dielectric layer is formed over the adhesion layer, wherein the adhesion layer has a material different from a material of the first high-k gate dielectric layer.
Inventor(s): Shih-Chuan Chiu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh Su of Tianzhong Township (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Yu Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yuan Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Zhen Yu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L29/06, H01L29/26, H01L29/40, H01L29/423, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a semiconductor structure includes an epitaxial region having a front side and a backside. the semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. the semiconductor structure includes a first silicide layer formed over the amorphous layer. the semiconductor structure includes a first metal contact formed over the first silicide layer.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Wing Yeung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Ming CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L27/092, H01L29/06, H01L29/08, H01L29/66, H01L29/775
CPC Code(s): H01L29/42392
Abstract: a semiconductor device and a manufacturing method thereof are provided. the semiconductor device includes a semiconductor substrate, semiconductor nanosheets vertically stacked upon one another and disposed above the semiconductor substrate, a gate structure surrounding each of the semiconductor nanosheets, inner spacers laterally covering the gate structure and interposed between the semiconductor nanosheets, and source/drain (s/d) regions disposed over the semiconductor substrate and laterally abutting the semiconductor nanosheets. the semiconductor nanosheets serve as channel regions. a bottommost inner spacer of the inner spacers underlying a bottommost semiconductor nanosheet of the semiconductor nanosheets is thinner than a topmost inner spacer of the inner spacers underlying a topmost semiconductor nanosheet of the semiconductor nanosheets. the s/d regions are separated from the gate structure through the inner spacers.
Inventor(s): Kao-Cheng LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yin WANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen Lin CHUNG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei Min CHAN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/786, H10B10/00
CPC Code(s): H01L29/66545
Abstract: a method includes forming a first bottom-tier transistor; forming a second bottom-tier transistor, the first and second bottom-tier transistors sharing a same source/drain region; forming a first top-tier transistor over the first bottom-tier transistor, the first top-tier transistor comprising a first channel layer and a first gate structure around the first channel layer; forming a second top-tier transistor over the second bottom-tier transistor, the second top-tier transistor comprising a second channel layer and a second gate structure around the second channel layer, the first and second top-tier transistors sharing a same source/drain region, wherein from a top view, a first dimension of the first channel layer in a lengthwise direction of the first gate structure is different than a second dimension of the second channel layer in the lengthwise direction of the first gate structure.
Inventor(s): Wei-Hsiang LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Han CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi On CHUI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L29/66545
Abstract: a method includes forming a fin structure including first and second sacrificial layers and first and second channel layers over a substrate; forming a dummy gate structure across the fin structure; forming gate spacers on opposite sides of the dummy gate structure; forming first source/drain epitaxial layers on opposite sides of the first channel layer; forming second source/drain epitaxial layers on opposite sides of the second channel layer; removing the dummy gate structure and the first and second sacrificial layers to form a gate trench defined by the gate spacers; forming an oxynitride layer in the gate trench to surround the first channel layer; forming a dipole layer to surround the oxynitride layer; performing an anneal process to drive dipole dopants into the oxynitride layer; and depositing a high-k gate dielectric layer and a work function metal layer in the gate trench to form a gate structure.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L29/06, H01L29/08, H01L29/423, H01L29/66
CPC Code(s): H01L29/775
Abstract: semiconductor structures and methods for manufacturing the same are provided. the semiconductor structure includes an isolation structure formed over a substrate, and first nanostructures formed over an isolation structure along a first direction. the semiconductor includes second nanostructures adjacent to the first nanostructure along the first direction. the semiconductor also includes a dielectric wall between the first nanostructures and the second nanostructures, and the dielectric wall includes a low-k dielectric material. the dielectric wall is in direct contact with the first nanostructures and the second nanostructures, and a top surface of the dielectric wall is higher than a top surface of the isolation structure. the semiconductor includes a gate structure formed over the first nanostructures along a second direction, and a cutting structure formed over the dielectric wall. the gate structure is divided into two portions by the cutting structure.
Inventor(s): Jhon Jhy LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L21/8234, H01L27/088, H01L29/423, H01L29/66
CPC Code(s): H01L29/775
Abstract: a device structure includes a substrate, a fin structure disposed on the substrate and elongated in an x direction, a gate structure formed on the fin structure and elongated in a y direction transverse to the x direction to terminate at two opposite ends, at least one dielectric portion connected to at least one of the two opposite ends of the gate structure, and having two sides that are opposite to each other in the x direction, and a pair of gate spacers which are spaced apart from each other in the x direction and are respectively disposed on two lateral sides of the gate structure, and which are elongated in the y direction to cover the two sides of the dielectric portion, respectively. a method for manufacturing the device structure is also disclosed.
Inventor(s): Cheng-I Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Han Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L29/06, H01L29/40, H01L29/417, H01L29/423, H01L29/49, H01L29/66
CPC Code(s): H01L29/775
Abstract: a method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate, patterning the first and second semiconductor layers into a fin structure, forming a dummy gate structure across the fin structure, depositing gate spacers over sidewalls of the dummy gate structure, removing the dummy gate structure to form a recess, removing the first semiconductor layers, depositing an interfacial layer wrapping the second semiconductor layers, depositing a high-k dielectric layer over the interfacial layer and over the sidewalls of the gate spacers, depositing a first gate electrode over the high-k dielectric layer, recessing the first gate electrode and the high-k dielectric layer to expose a top portion of the sidewalls of the gate spacers, depositing a low-k dielectric layer over the recessed high-k dielectric layer, and depositing a second gate electrode over the first gate electrode.
Inventor(s): Chi-Hsien LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ho-Hsiang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Yuan LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Jin YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ta LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03B5/12, H03B1/04, H03H7/01
CPC Code(s): H03B5/1228
Abstract: a voltage-controlled oscillator (vco) includes a power supply source, a voltage source, a reference voltage node, first and second transistors, each including a source terminal coupled to the reference voltage node, and first through fourth conductive structures. the first conductive structure includes a first terminal coupled to the power supply source, a first extending portion coupled between the first terminal and a drain terminal of the first transistor, and a second extending portion coupled between the first terminal and a drain terminal of the second transistor, and the second conductive structure includes a second terminal coupled to the voltage source, a third extending portion coupled in series with the third conductive structure between the second terminal and a gate of the first transistor, and a fourth extending portion coupled in series with the fourth conductive structure between the second terminal and a gate of the second transistor.
Inventor(s): Huizhi YANG of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Qinling MA of Nantong City (CN) for taiwan semiconductor manufacturing company, ltd., Lei PAN of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Yaqi MA of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K19/0175, H01L27/02, H02H9/04
CPC Code(s): H03K19/017545
Abstract: an integrated circuit is provided and includes a first active region of a first conductivity type coupled to a first voltage terminal and corresponding to a first terminal of a first transistor and a first terminal of a second transistor included in an inverter of a level shifter circuit, wherein the first transistor is configured to discharge electrostatic charges to the first voltage terminal; and second and third active regions, corresponding to a third transistor, of a second conductivity type different from the first conductivity type, wherein the second active region is coupled to a second voltage terminal, and the third active region is coupled to a first terminal, different from the second voltage terminal, of the level shifter circuit. the third transistor is configured to transmit a first supply voltage from the second voltage terminal for the integrated circuit.
Inventor(s): Je Syu Liu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chen Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yangsyu Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng Hung Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K19/20, G11C5/14
CPC Code(s): H03K19/20
Abstract: in some aspects of the present disclosure, a dual rail circuit is disclosed. in some aspects, the dual rail circuit includes a first circuit in a first power domain. the first circuit comprises an input port and an output port. in some aspects, the dual rail circuit includes a second circuit in a second power domain different from the first power domain. the second circuit coupled to the input port of the first circuit and the output port of the first circuit.
Inventor(s): Chia-Yu LING of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/00
Abstract: a semiconductor storage cell structure and a manufacturing method thereof are provided. the manufacturing method of the semiconductor storage cell structure includes the following steps. a first transistor, which is a gate-all-around (gaa) structure, is formed. a second transistor is formed on the first transistor. an assistance gate layer is disposed above a storage node.
Inventor(s): Chieh-Fang Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, H01L29/66, H01L29/78, H10B51/10
CPC Code(s): H10B51/20
Abstract: a memory device includes a plurality of first conductive pillars, a plurality of second conductive pillars, a plurality of gap filling pillars, a channel layer and first dielectric pillars. the gap filling pillars are located in between the first conductive pillars and the second conductive pillars. the channel layer is extending in a first direction, and located on side surfaces of the first conductive pillars and the second conductive pillars. the first dielectric pillars are located in between the channel layer and the plurality of gap filling pillars, wherein a length of an interface where the first dielectric pillars contact the gap filling pillars along the first direction is different from a length of the gap filling pillars along the first direction.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on January 2nd, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- G02B6/13
- CPC G02B6/13
- Taiwan semiconductor manufacturing company, ltd.
- G03F7/00
- G03F1/70
- H01L21/033
- CPC G03F7/705
- G05B19/4099
- CPC G05B19/4099
- G06F30/3308
- G06F30/394
- G06F30/398
- CPC G06F30/3308
- G06F30/392
- G06F30/3953
- H01L23/528
- CPC G06F30/398
- G11C11/412
- H10B10/00
- CPC G11C11/4125
- G11C11/418
- CPC G11C11/418
- G11C11/419
- CPC G11C11/419
- G11C17/16
- G11C17/18
- CPC G11C17/16
- H01L21/28
- H01L21/02
- H01L21/3105
- H01L21/762
- H01L21/8238
- H01L27/092
- H01L29/06
- H01L29/08
- H01L29/66
- H01L29/78
- CPC H01L21/28123
- H01L21/311
- H01L21/768
- H01L27/088
- CPC H01L21/31144
- H01L29/423
- CPC H01L21/76229
- H01L21/764
- H01L29/16
- H01L29/161
- H01L29/165
- H01L29/24
- CPC H01L21/764
- H01L23/00
- H01L23/48
- H01L25/065
- CPC H01L21/76849
- H01L21/8234
- H01L21/285
- H01L21/74
- H01L23/522
- CPC H01L21/823418
- H01L29/775
- H01L29/786
- CPC H01L21/823481
- H01L21/3065
- H01L21/822
- H01L29/417
- CPC H01L21/823814
- H01L21/66
- CPC H01L22/32
- H01L23/42
- H01L21/56
- H01L23/31
- H01L25/10
- CPC H01L23/42
- H01L23/532
- CPC H01L23/53276
- H01L23/538
- H01L23/498
- H01L25/16
- CPC H01L23/5381
- H01L23/66
- CPC H01L23/66
- CPC H01L24/08
- H01L23/373
- CPC H01L24/29
- H01L21/78
- H01L23/58
- CPC H01L25/0657
- H01L25/00
- H01L29/45
- CPC H01L27/0886
- H01L29/49
- CPC H01L27/0922
- H01L27/12
- H01L21/84
- CPC H01L27/12
- CPC H01L27/1207
- H01C17/075
- H01C7/00
- CPC H01L28/24
- H01L29/40
- H10K10/46
- CPC H01L29/401
- H01L29/26
- CPC H01L29/41733
- CPC H01L29/42392
- CPC H01L29/66545
- CPC H01L29/775
- H03B5/12
- H03B1/04
- H03H7/01
- CPC H03B5/1228
- H03K19/0175
- H01L27/02
- H02H9/04
- CPC H03K19/017545
- H03K19/20
- G11C5/14
- CPC H03K19/20
- H10B12/00
- CPC H10B12/00
- H10B51/20
- H10B51/10
- CPC H10B51/20