Taiwan Semiconductor Manufacturing Company, LTD. patent applications on February 27th, 2025
Patent Applications by Taiwan Semiconductor Manufacturing Company, LTD. on February 27th, 2025
Taiwan Semiconductor Manufacturing Company, LTD.: 84 patent applications
Taiwan Semiconductor Manufacturing Company, LTD. has applied for patents in the areas of H01L23/00 (22), H01L29/66 (15), H01L23/498 (12), H01L29/06 (11), H01L29/423 (10) H01L23/562 (3), H01L23/481 (3), H01L25/0657 (3), H01L29/7851 (3), H02M3/07 (2)
With keywords such as: layer, structure, semiconductor, gate, substrate, device, die, source, surface, and dielectric in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, LTD.
Inventor(s): Jyh-Shiou Hsu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsun Tsai of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chun Hu of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Wei Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Ju Huang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B01D46/10, B01D29/01, B01D35/30, B01D39/20, B01D61/18, H01L21/673
CPC Code(s): B01D46/10
Abstract: a method is provided for supporting environmental control in a semiconductor wafer processing space, the method includes: flowing a first gas under pressure in a first direction through a first diffuser tube, thereby generating a first lateral flow of gas through a sidewall of the first diffuser tube; flowing a second gas under pressure in a second direction through a second diffuser tube, thereby generating a second lateral flow of gas through a sidewall of the second diffuser tube, the second direction being opposite the first direction; combining the first and second lateral flows of gas within a housing; and outputting the combined lateral flows of gas from the housing to produce a laminar gas flow covering an opening to the semiconductor wafer processing space.
Inventor(s): Chun-Yen LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., I. LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Lan CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hsuan LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Yu CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Jung LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-I TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chien CHI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsing TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pei Shan CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C23C14/04, C23C14/34, C23C14/50, C23C14/54, C23C14/58
CPC Code(s): C23C14/046
Abstract: a method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.
Inventor(s): Hui CAO of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Jiyong ZHANG of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Tao ZHU of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): F26B11/00, F26B21/10
CPC Code(s): F26B11/00
Abstract: a method includes placing a ring-shaped bearing on a cylindrically-shaped sidewall in a chamber, the ring-shaped bearing comprising an inner race, an outer race, balls between the inner race and the outer race, and a grease among the balls; rotating the outer race of the ring-shaped bearing while the inner race of the ring-shaped bearing remains stationary relative to the cylindrically-shaped sidewall; heating the ring-shaped bearing; pumping the grease out of the chamber.
Inventor(s): Chih-Chieh Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hao Tsai of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/12, G02B6/122, G02B6/13
CPC Code(s): G02B6/12004
Abstract: a semiconductor package and a manufacturing method thereof are provided. the semiconductor package includes a photonic die, an encapsulant and a wave guide structure. the photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. the encapsulant laterally encapsulates the photonic die. the wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo Hsia of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hua-Kung Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui Lin Chao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42, H01L33/00
CPC Code(s): G02B6/428
Abstract: optical devices and methods of manufacture are presented herein. in an embodiment, an optical device is provided that includes an optical package having a first surface and a second surface opposite the first surface, a laser die package having a third surface and a fourth surface opposite the third surface, wherein the first surface is planar with the third surface and the second surface is planar with the fourth surface, a first silicon support attached to both the second surface and the fourth surface, and an interposer attached to both the first surface and the third surface, wherein the interposer is free of a silicon substrate.
Inventor(s): Chun-Fu YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Cheng HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Cheng LIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/82, G03F7/20
CPC Code(s): G03F1/82
Abstract: a method includes placing a photomask having a contamination on a surface thereof in a plasma processing chamber. the contaminated photomask is plasma processed in the plasma processing chamber to remove the contamination from the surface. the plasma includes oxygen plasma or hydrogen plasma.
Inventor(s): An-Ren ZI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/09, G03F7/004, G03F7/105, G03F7/11, H01L21/027, H01L21/308
CPC Code(s): G03F7/094
Abstract: a method for manufacturing a semiconductor device includes forming a resist structure including forming a resist layer including a resist composition over a substrate. after forming the resist layer, the resist layer is treated with an additive. the additive is one or more selected from the group consisting of a radical inhibitor, a thermal radical initiator, and a photo radical initiator.
Inventor(s): Guancyun LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Jung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Feng TUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Yin SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G05B19/4155, G06N20/00
CPC Code(s): G03F7/70866
Abstract: an euv stocker and an euv pod device is disclosed. the euv stocker includes an ai driven dynamic control circuitry, an ai controlled safety interlock, and an independent air return control device. the euv stocker includes a mass flow control (mfc) that operates in conjunction with one or more valves. the euv stocker further includes a hydrocarbon detecting assembly, oxygen detecting assembly, pressure detecting assembly, and temperature detecting assembly and more to maintain the required condition within the euv stocker. the euv stocker also includes automated transportation devices such as amhs, oht, mr, agv, rgv, or the like to provide a safe euv mask storage environment for operators.
Inventor(s): Je-Min Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Haruki Mori of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Fu Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hidehiro Fujiwara of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F7/499
CPC Code(s): G06F7/49915
Abstract: a system, circuit, and method of operation of the system and circuit are disclosed. in one aspect, a device includes a computation circuit, a memory array, and a controller. the controller can determine that one or more input data bits to the computation circuit or one or more memory bits provided from the memory array are all in a first logic state. in response to determining that the one or more input data bits or the one or more memory bits are all in the first logic state, the controller can generate a control signal to disable at least one component of the computation circuit.
Inventor(s): Ching-Fang Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ang-Chih Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Heng Lo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Heng-Yi Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/327, G06F30/392, G06F30/398
CPC Code(s): G06F30/327
Abstract: an integrated circuit design implementation system includes a synthesis tool configured to: receive a behavioral description of each of a plurality of first components; generate first netlists based on the behavioral descriptions of the first components; receive connection information of a plurality of second components, wherein the connection information comprises physical arrangement and connectivity among the first components and the second components; generate a plurality of third components, wherein each of the third components operatively corresponds to an interface between a pair of one of the first components and one of the second components; and transform the first netlists to a second netlist based on first vertices, second vertices, third vertices, and edges. the first vertices correspond to the first components, respectively, the second vertices correspond to the second components, respectively, and the third vertices correspond to the third components, respectively.
Inventor(s): Ranjith KUMAR of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mohammed Zackriya VANAIKAR of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/31
CPC Code(s): G06F30/392
Abstract: a method includes arranging first and second rows of gate regions in a cell. the first row has a first width extending from first to last gate regions and equal to a first multiple of a gate region pitch. the second row has a second width extending from first to last gate regions and equal to a second multiple of the gate region pitch greater than the first multiple. the method includes defining first through fourth cell border segments by extending the first and second segments along the first and last gate regions of the first row, and extending the third and fourth segments along the first and last gate regions of the second row, whereby the border is non-rectangular based on one or both of the first and third segments or the second and fourth segments being unaligned with each other, and storing the cell in a storage device.
Inventor(s): Win-San Khwa of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Cheng Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Lun Lu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Jen Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Fan Chang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/06, G11C7/08, G11C7/12
CPC Code(s): G11C7/065
Abstract: a sense amplifier of a memory device that includes sense amplifier circuits and a reference sharing circuit is introduced. the sense amplifier circuits are configured to sense the plurality of bit lines according to an enable signal. the reference sharing circuit includes first switches and second switches that are coupled to the reference nodes and second reference nodes of the sense amplifier circuits, respectively. the first switches and second switches are controlled according to a control signal to control a first electrical connection among the first reference nodes, and to control a second electrical connection among the second reference nodes. an operation method of the sense amplifier and a memory device including the sense amplifier are also introduced.
Inventor(s): Chen-Jun Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Feng Kao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chih Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H. Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/4096
CPC Code(s): G11C11/4096
Abstract: disclosed herein are related to a memory device. in one aspect, the memory device includes a memory array including a set of memory cells. in one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. in one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. in one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. in one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.
Inventor(s): Yih WANG of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Cheng CHANG of Xihu Township (TW) for taiwan semiconductor manufacturing company, ltd., Perng-Fei YUH of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Gu-Huan LI of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En HUANG of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Ying LEE of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C16/04, G11C16/08, G11C16/26, G11C16/30
CPC Code(s): G11C16/0433
Abstract: a memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. a first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. the first bitcell is coupled to a first of the source lines. the second bitcell is coupled to a second of the source lines. the first source line is different from the second source line.
Inventor(s): Meng-Sheng Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C17/16, H01L29/788, H10B20/00, H10B20/25
CPC Code(s): G11C17/16
Abstract: a memory device includes peripheral transistors formed along a first surface of a substate; memory cells formed in one or more of first metallization layers disposed over the first surface, each of the memory cells being operatively coupled to a subset of the peripheral transistors and including a programming transistor and at least a first reading transistor; and second metallization layers disposed over a second surface of the substrate opposite to the first surface. a first source/drain terminal of the first reading transistor is in electrical connection with a first source/drain terminal of the programming transistor. a second source/drain terminal of the first reading transistor is in electrical connection with a bit line that is formed in a corresponding one of the second metallization layers.
Inventor(s): Yu-Lun KE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chi LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Tsang HSIEH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsi TANG of Yunlin County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Teng LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/32, H01L21/311
CPC Code(s): H01J37/32642
Abstract: a method for manufacturing a semiconductor structure includes disposing a wafer in a processing chamber, in which the wafer is laterally surrounded by a focus ring. a plasma is formed in the processing chamber to process the wafer. a thickness of the focus ring is detected. a plasma direction of the plasma over a peripheral region of the wafer is adjusted according to the thickness of the focus ring.
Inventor(s): Wei-Lin CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chien WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chihy-Yuan CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sz-Fan CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hung LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Chang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Sen KUO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Jia SHIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L21/027
CPC Code(s): H01L21/0206
Abstract: embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. the method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. the photoresist layer is exposed to radiation. the photoresist layer is developed using a developer solution. the semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. a tetramethylammonium hydroxide (tmah) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.
Inventor(s): Hsu Ming HSIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shen WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kung Shu HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/311, H01L21/02, H01L21/3065, H01L21/762, H01L21/8234
CPC Code(s): H01L21/31105
Abstract: recesses may be formed in portions of an ild layer of a semiconductor device in a highly uniform manner. uniformity in depths of the recesses may be increased by configuring flows of gases in an etch tool to promote uniformity of etch rates (and thus, etch depth) across the semiconductor device, from semiconductor device to semiconductor device, and/or from wafer to wafer. in particular, the flow rates of gases at various inlets of the tch tool may be optimized to provide recess depth tuning, which increases the process window for forming the recesses in the portions of the ild layer. in this way, the increased uniformity of the recesses in the portions of the ild layer enables highly uniform capping layers to be formed in the recesses.
Inventor(s): Cheng-Ping Chen of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Shen Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Lung Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wen Cheng of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Chun Yan Chen of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, B08B1/12, F16L23/024
CPC Code(s): H01L21/67046
Abstract: a fitting for an upper brush in a double brush scrubbing chamber of a wafer cleaning system is disclosed. the fitting includes a base plate, a flanged pipe, and a threaded connector. the base plate includes a threaded hole with a stop surface therein and a channel extending from the stop surface through a lower surface of the base plate. the flanged pipe is inserted into the base plate such that the flange at the top end of a hollow tube rests on the stop surface and the hollow tube passes through the channel of the base plate. the threaded connector has a passage therethrough, and engages the threaded hole of the base plate to fix the flanged pipe in place. this structure is able to provide fluid while minimizing particle generation.
Inventor(s): Chia-Hsi Wang of Xihu Township (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Yu Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/683, H01L21/66, H01L21/67
CPC Code(s): H01L21/6833
Abstract: various embodiments of the present application are directed toward an adjustable wafer chuck. the adjustable wafer chuck is configured to hold a wafer. the adjustable wafer chuck comprises a base portion and a pad portion. the base portion comprises a plurality of adjustable base structures. the pad portion is disposed on a first side of the base portion. the pad portion comprises a plurality of contact pads disposed on the plurality of adjustable base structures. each of the adjustable base structures are configured to move along a plane in a first direction and configured to move along the plane in a second direction that is opposite the first direction.
Inventor(s): Bo-Ru CHEN of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Yan-Hong LIU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Che-Fu CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/687, C23C16/455, C23C16/458, H01J37/32, H01L21/683, H01L21/768
CPC Code(s): H01L21/68785
Abstract: in an embodiment, a system includes: a gas distributor assembly configured to dispense gas into a chamber; and a chuck assembly configured to secure a wafer within the chamber, wherein at least one of the gas distributor assembly and the chuck assembly includes: a first portion comprising a convex protrusion, and a second portion comprising a concave opening, wherein the convex protrusion is configured to engage the concave opening.
Inventor(s): Po-Han Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/56, H01L23/00, H01L23/31, H01L23/48, H01L23/522, H01L23/528, H01L23/532
CPC Code(s): H01L21/76898
Abstract: a method of fabricating a redistribution circuit structure including the following steps is provided. a conductive via is formed. a photosensitive dielectric layer is formed to cover the conductive via. the photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. a redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.
Inventor(s): Ying-Ju Chen of Tuku Township (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/78, B23K26/40, B23K103/00, H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L21/78
Abstract: a semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. a molding layer extends around the plurality of connectors. a sidewall of the molding layer that is closest to a scribe line is offset from the scribe line.
Inventor(s): Sheng-An Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Jung Yang of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jie Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L23/3114
Abstract: a semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. the second semiconductor die is stacked over the first semiconductor die. the passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. the anti-arcing pattern is disposed over the passivation layer. the conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.
Inventor(s): Wensen Hung of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Kang Huang of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Sao-Ling Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yu Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Shu Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Yuan Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hsiang Lao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L21/48, H01L23/00, H01L23/42, H01L23/495, H01L25/00, H01L25/065
CPC Code(s): H01L23/3675
Abstract: a semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. the semiconductor die is disposed on the circuit substrate. the cover is disposed over the semiconductor die and over the circuit substrate. the cover comprises a lid portion and a support portion. the structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.
Inventor(s): Shu-Shen YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Chia YANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Kuei HSU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chih YEW of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/373, H01L23/29, H01L23/58
CPC Code(s): H01L23/373
Abstract: a semiconductor die package and a method of forming the same are provided. the semiconductor die package includes a package substrate, semiconductor dies over the package substrate, and an underfill element over the package substrate and surrounding the semiconductor dies. a portion of the underfill element is located between the semiconductor dies. the semiconductor die package also includes lid structures respectively attached to the top surfaces of the semiconductor dies. in plan view, each lid structure is located within the periphery of the top surface of the corresponding semiconductor die. each lid structure is disconnected from other lid structures, and a gap is formed between adjacent lid structures and located over the portion of the underfill element.
Inventor(s): Kuo-Chiang Ting of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ta Hao Sung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Wei Hong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/373, H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L23/3735
Abstract: a method includes bonding a bottom die to a carrier, and bonding a top die to the bottom die. the top die includes a semiconductor substrate, and the semiconductor substrate has a first thermal conductivity. the method further includes encapsulating the top die in a gap-fill region, bonding a supporting substrate to the top die and the gap-fill region to form a reconstructed wafer, wherein the supporting substrate has a second thermal conductivity higher than the first thermal conductivity, de-bonding the reconstructed wafer from the carrier, and forming electrical connectors on the bottom die.
Inventor(s): Yen-Chih HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-An SUN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Chuan HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/768
CPC Code(s): H01L23/481
Abstract: a semiconductor device includes a feol structure and a beol structure. the beol structure is formed over the feol structure and includes a conductive layer, an etching stop layer (esl) structure, a through via and a barrier layer. the esl structure is formed over the conductive layer and has a first recess and a lateral surface. the through via passes through the esl structure to form the first recess and the lateral surface. the barrier layer covers the lateral surface and the first recess. the first recess is recessed with respect to the lateral surface, and the first recess has a first depth ranging between 1 nm and 7 nm.
Inventor(s): Yang-Hsin Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Hsun Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih Hsin Yang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/768, H01L23/00, H01L23/522, H01L23/58
CPC Code(s): H01L23/481
Abstract: an embodiment includes a device, the device including a first die including a first surface and a second surface opposite the first surface. the first die includes a plurality of through substrate vias (tsvs) exposed from the second surface of the first die. the device also includes a guard ring surrounding the plurality of tsvs. the device also includes a dummy metallization pattern surrounding the guard ring. the device also includes an active metallization pattern connected to active devices in the first die.
Inventor(s): Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Lin Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L29/06, H01L29/417, H01L29/775, H01L29/786, H10B10/00
CPC Code(s): H01L23/481
Abstract: a semiconductor structure includes a first source/drain (s/d) epitaxial feature, a second s/d epitaxial feature adjacent to the first s/d epitaxial feature, an insulating structure between the first and the second s/d epitaxial features, and a shared s/d contact over top surfaces of the first and the second s/d epitaxial features. a center portion of the shared s/d contact is directly between a side surface of the first s/d epitaxial feature and a side surface of the second s/d epitaxial feature. the center portion is directly above the insulating structure. the semiconductor structure further includes a backside via penetrating through the insulating structure to directly land on a bottom surface of the center portion.
Inventor(s): Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ju Chen of Yunlin County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/495, H01L21/48, H01L21/768, H01L23/00, H01L23/498, H01L23/528, H01L25/065
CPC Code(s): H01L23/49503
Abstract: provided is a package structure including a bottom die, a top die, an insulating layer, a circuit substrate, a dam structure, and an underfill. the top die is bonded on a front side of the bottom die. the insulating layer is disposed on the front side of the bottom die to laterally encapsulate a sidewall of the top die. the circuit substrate is bonded on a back side of the bottom die through a plurality of connectors. the dam structure is disposed between the circuit substrate and the back side of the bottom die, and connected to the back side of the bottom die. the underfill laterally encapsulates the connectors and the dam structure. the dam structure is electrically isolated from the circuit substrate by the underfill. a method of forming the package structure is also provided.
Inventor(s): Jing-Cheng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L23/00, H01L23/538, H01L25/00, H01L25/03, H01L25/10
CPC Code(s): H01L23/49816
Abstract: a method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. the vias may be in via chips with one or more dielectric layers separating the vias. the via chips may be formed separately from the carrier. the dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. an rdl having rdl contact pads and conductive lines may be formed on the molded substrate. a second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one rdl contact pad.
Inventor(s): Ping-Jung Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ken-Yu Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Wen Ko of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsang-Jiuh Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/768, H01L23/538, H01L27/06
CPC Code(s): H01L23/49827
Abstract: a method includes bonding a top die to a bottom die, depositing a first dielectric liner on the top die, and depositing a gap-fill layer on the first dielectric liner. the gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon oxide. the method further includes etching the gap-fill layer and the first dielectric liner to form a through-opening, wherein a metal pad in the bottom die is exposed to the through-opening, depositing a second dielectric liner lining the through-opening, filling the through-opening with a conductive material to form a through-via connecting to the metal pad, and forming a redistribution structure over and electrically connecting to the top die and the through-via.
Inventor(s): Ping-Jung Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ken-Yu Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Wen Ko of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsang-Jiuh Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/768, H01L23/538, H01L27/06
CPC Code(s): H01L23/49827
Abstract: a method includes bonding a top die to a bottom die, depositing a first dielectric liner on the top die, and depositing a gap-fill layer on the first dielectric liner. the gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon oxide. the method further includes etching the gap-fill layer and the first dielectric liner to form a through-opening, wherein a metal pad in the bottom die is exposed to the through-opening, depositing a second dielectric liner lining the through-opening, filling the through-opening with a conductive material to form a through-via connecting to the metal pad, and forming a redistribution structure over and electrically connecting to the top die and the through-via.
Inventor(s): Chih-Chao Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Wen Chang of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L23/00, H01L25/065
CPC Code(s): H01L23/49838
Abstract: a method includes forming first integrated circuit devices and second integrated circuit devices on a semiconductor substrate of a wafer, forming a metal layer as a part of the wafer, and forming a transistor comprising a first source/drain region connected to the first integrated circuit devices. the transistor is farther away from the semiconductor substrate than the metal layer. an electrical connector is formed on a surface of the wafer, and is electrically connected to a second source/drain region of the transistor.
Inventor(s): Chung-Ming Weng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shi Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chieh Hsieh of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Yi Kuo of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yuan Yu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hua-Kuei Lin of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Che Ho of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chewn-Pu Jou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Tse Tang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, G02B6/42, H01L21/768, H01L23/00
CPC Code(s): H01L23/49838
Abstract: a semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. the redistribution structure includes a plurality of connectors. the supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. the semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. the transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.
Inventor(s): Li-Shyue Lai of Hsinchu Country (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hao Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Yu Ling of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H CHIANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L23/522, H10B51/20, H10B51/30
CPC Code(s): H01L23/5283
Abstract: a manufacturing method of a semiconductor structure includes at least the following steps. a memory device is formed in an interconnect structure over a substrate. forming the memory device includes forming an alternating stack of dielectric material layers and conductive material layers, wherein the alternating stack includes a memory array region and a staircase region adjacent to the memory array region; forming a trench on the memory array region of the alternating stack; forming a data storage layer, channel layers, bit line pillars, and source line pillars in the trench; and performing patterning processes to from a staircase structure on the staircase region. the staircase structure steps downward from a first direction and makes a 180-degree turn to step downward in a second direction opposite to the first direction.
Inventor(s): Szu-Ping Tung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chien Chi of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Wen Su of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/02, H01L21/768, H01L23/522, H01L23/528
CPC Code(s): H01L23/5329
Abstract: a semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. a first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. a portion of the dielectric layer is removed to form an opening. a second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.
Inventor(s): Ming-Tsu Chung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chi Lin of Su-Lin City (TW) for taiwan semiconductor manufacturing company, ltd., Yan-Zuo Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yang-Chih Hsueh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/482, H01L23/498, H01L25/065
CPC Code(s): H01L23/562
Abstract: in a package device, wherein integrated circuit devices are bonded to a substrate, stress arising from mechanical strain, cte mismatch, and the like can be alleviated or eliminated by incorporating stress buffering air gaps into a protective material, such as a gap fill oxide. the air gaps can be formed by tuning and changing deposition parameters during the deposition process and/or by tuning the size and placement of adjacent integrated circuit devices in the package, and/or by forming trenches in the protective material prior to the bonding process.
Inventor(s): Cong-Wei Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu Chen Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hua Wang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/498
CPC Code(s): H01L23/562
Abstract: an integrated circuit includes a semiconductor substrate, an interconnection structure, a first dielectric layer, conductive pads, a second dielectric layer, conductive connectors, and an anti-stress layer. the interconnection structure is disposed on the semiconductor substrate. the first dielectric layer is disposed on the interconnection structure. the conductive pads are disposed on the first dielectric layer and are electrically connected to the interconnection structure. the second dielectric layer is disposed on the first dielectric layer to laterally surround the conductive pads. the conductive connectors are disposed on and electrically connected to the conductive pads. the anti-stress layer is disposed over the conductive pads and laterally surrounds some of the conductive connectors.
Inventor(s): Po-Chen LAI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hua WANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chih YEW of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Ling LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yen LEE of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L21/683, H01L23/16, H01L23/31, H01L23/538
CPC Code(s): H01L23/562
Abstract: a package structure is provided. the package structure includes a redistribution structure on a substrate, a semiconductor die on the redistribution structure and electrically connected to the substrate, a wall structure on the redistribution structure and electrically isolated from the substrate. the semiconductor die includes a first sidewall, a second sidewall connected to the first sidewall, and a third sidewall connected to the second sidewall. the wall structure includes a first partition, a second partition and a third partition respectively immediately adjacent to the first sidewall, the second sidewall, and the third sidewall of the semiconductor die. the first partition is located immediately adjacent to and spaced apart from the second partition by a first distance, the second partition is located immediately adjacent to and spaced apart from the third partition by a second distance, and the first distance is substantially equal to the second distance.
Inventor(s): Ke-Gang Wen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih Hsin Yang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Hsun Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Chieh Hsiao of Shetou Township (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Wei Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/78, H01L23/544, H01L23/58, H01L29/66
CPC Code(s): H01L23/564
Abstract: a method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming first gate structures around the first nanostructures; replacing the second nanostructures with isolation regions; and forming a seal ring over the substrate, wherein the seal ring is between the first region and the second region.
Inventor(s): Yuhsiang Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Sheng Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, G11C17/16, G11C17/18, H10B20/25
CPC Code(s): H01L23/573
Abstract: a semiconductor device includes a memory cell randomly presenting a first logic state or a second logic state and formed on a first side of a substrate, and a first and a second bit lines formed on a second side of the substrate opposite to the first side. the memory cell includes: a programming transistor having a first and a second source/drain terminals; a first reading transistor having a first source/drain terminal coupled to the first source/drain terminal of the programming transistor; and a second reading transistor having a first source/drain terminal coupled to the second source/drain terminal of the programming transistor. the first bit line is operatively coupled to a second source/drain terminal of the first reading transistor, and the second bit line is operatively coupled to a second source/drain terminal of the second reading transistor.
Inventor(s): Meng-Sheng Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, G11C17/16, H10B20/25
CPC Code(s): H01L23/573
Abstract: a memory device includes a transistor formed along a frontside surface of a substrate. the memory device includes a first fuse resistor formed in a first metallization layer that is vertically disposed with respect to the frontside surface. the memory device includes a second fuse resistor formed in a second metallization layer that is vertically disposed with respect to the frontside surface, the first metallization layer being different from the second metallization layer. the second fuse resistor and the first fuse resistor are each coupled to the transistor.
Inventor(s): Bo-Huan Hsin of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Han Chiou of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Cheng Chang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/498
CPC Code(s): H01L24/05
Abstract: provided are semiconductor dies and methods for forming semiconductor dies. a method includes forming a semiconductor die having under bump metal (ubm) pads in a dense region and in an isolated region; forming external electrical connectors in contact with the ubm pads; and limiting the external electrical connectors to a pre-selected vertical height.
Inventor(s): Ke-Gang Wen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Bey Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Wei Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Feng Chen of Yilan City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Chieh Hsiao of Shetou Township (TW) for taiwan semiconductor manufacturing company, ltd., Chih Chuan Su of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/48, H01L23/498, H01L25/00, H01L25/065
CPC Code(s): H01L24/08
Abstract: an embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. the device also includes an active device on the first surface of the substrate. the device also includes a first interconnect structure on the first surface of the substrate. the device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. the device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.
Inventor(s): Cheng-Shiuan Wong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Jan Pei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsuan-Ting Kuo of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yu Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Shen Cheng of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Philip Yu-Shuan Chung of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, B23K1/008, B23K101/40
CPC Code(s): H01L24/75
Abstract: a system for reflowing a semiconductor workpiece including a stage, a first vacuum module and a second vacuum module, and an energy source is provided. the stage includes a base and a protrusion connected to the base, the stage is movable along a height direction of the stage relative to the semiconductor workpiece, the protrusion operably holds and heats the semiconductor workpiece, and the protrusion includes a first portion and a second portion surrounded by and spatially separated from the first portion. the first vacuum module and the second vacuum module respectively coupled to the first portion and the second portion of the protrusion, and the first vacuum module and the second vacuum module are operable to respectively apply a pressure to the first portion and the second portion. the energy source is disposed over the stage to heat the semiconductor workpiece held by the protrusion of the stage.
Inventor(s): Tsang-Jiuh Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Che Lin of Toufen Township (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chun Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Jung Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Wen Ko of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L23/00
CPC Code(s): H01L25/0657
Abstract: a method includes: forming first bond pads along a wafer; bonding a first die to a first set of the first bond pads, the first die being electrically connected to the wafer; depositing a gap-fill dielectric over the wafer and around the first die; forming openings in the gap-fill dielectric; forming first active through vias in physical contact with the second set of the first bond pads and first dummy through vias in physical contact with the third set of the first bond pads, the first active through vias being electrically connected to the wafer, the first dummy through vias being electrically isolated from the wafer; forming second bond pads along the first die, the first active through vias, and the first dummy through vias; and bonding a second die to the first die and to a first active via of the first active through vias.
Inventor(s): Harry-Hak-Lay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Wu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Tuo Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Sheng Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei Chuang Wu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih Kuang Yang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Jen Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shun-Kuan Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chien Lin Liu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Tzu Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yung Chun Tu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L25/00
CPC Code(s): H01L25/0657
Abstract: various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3d) integrated circuit (ic), as well as the 3d ic and a method for forming the 3d ic. a second ic die underlies the first ic die, and a third ic die underlies the second ic die. a first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third ic dies. further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third ic dies. the second and third ic dies include individual pad/bridge structures at top metal (tm) layers of corresponding interconnect structures. the pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.
Inventor(s): Chao-I Wu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, G11C5/04, G11C5/06, H01L23/00, H01L23/538, H01L27/06, H10B61/00
CPC Code(s): H01L25/0657
Abstract: a semiconductor package includes a processor die, a storage module and a package substrate. the storage module includes an array of cache units and an array of memory units stacked over one another, and electrically connected to the processor die, wherein the array of cache units is configured to hold copies of data stored in the array of memory units and frequently used by the processor die. the package substrate is on which the processor die and the storage module are disposed.
Inventor(s): Wan-Hsueh Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H02M3/07, H02M3/158
CPC Code(s): H02M3/07
Abstract: a circuit includes first and second transistors coupled in series, respective gate terminals of which are coupled to a first node to receive a first signal through a first capacitor; third and fourth transistors coupled in series, respective gate terminals of which are coupled to a second node to receive a second signal logically inverse to the first signal through a second capacitor; a fifth transistor having its source/drain terminals coupled between the gate terminal of the first transistor and the first node; a sixth transistor having its source/drain terminals coupled between the first node and the gate terminal of the second transistor; a seventh transistor having its source/drain terminals coupled between the gate terminal of the third transistor and the second node; and an eighth transistor having its source/drain terminals coupled between the second node and the gate terminal of the fourth transistor.
Inventor(s): Yu-Wei Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Sheng Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H02M3/07
CPC Code(s): H02M3/07
Abstract: a semiconductor device includes a first switch, a second switch, a third switch, and a fourth switch formed on a first side of a substrate, wherein the first switch and the second switch are connected in series between a first reference voltage and an output voltage, and wherein the third switch and the fourth switch are connected in series between the first reference voltage and a second reference voltage. the semiconductor device includes a capacitor formed on a second side of the substrate opposite to the first side, and having a first terminal and a second terminal. the first terminal is coupled to a first node between the first and second switches, and the second terminal is coupled to a second node between the third and fourth switches.
Inventor(s): Tsung-Kai Chiu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Yun Wu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yin Wang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: in an embodiment, a device includes: a first transistor including a first gate structure; a second transistor including a second gate structure, the second gate structure disposed above and coupled to the first gate structure; a third gate structure; a fourth gate structure, the fourth gate structure disposed above and coupled to the third gate structure; a gate isolation region between the first gate structure and the third gate structure, the gate isolation region disposed between the second gate structure and the fourth gate structure; and a cross-coupling contact extending beneath the gate isolation region, the first gate structure, and the third gate structure, the cross-coupling contact coupled to the first gate structure.
Inventor(s): Shao-Ting Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Sheng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/25, G11C17/16
CPC Code(s): H10B20/25
Abstract: a memory device is disclosed. the memory device includes a memory array comprising a plurality of memory cells. at least a first one of the memory cells, by default, permanently presents a first logic state based on a short circuit. at least a second one of the memory cells, by default, permanently presents a second logic state opposite to the first logic state based on an open circuit.
Inventor(s): Bo-Feng Young of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, H01L29/786, H10B51/10, H10B53/20
CPC Code(s): H10B51/20
Abstract: a memory cell includes a thin film transistor over a semiconductor substrate. the thin film transistor includes a memory film contacting a word line, an oxide semiconductor (os) layer contacting a source line and a bit line, and a conductive feature interposed between the memory film and the os layer. the memory film is disposed between the os layer and the word line. a dielectric material covers sidewalls of the source line, the memory film, and the os layer.
Inventor(s): Tzu-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chu-Jie HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wen LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hung SHIH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chi TU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B53/30, H01L21/768, H01L23/522
CPC Code(s): H10B53/30
Abstract: a method for manufacturing a semiconductor device includes: forming an etch stop layer with an opening; forming a barrier layer on the etch stop layer to fill the opening, the barrier layer including a layer portion disposed on the etch stop layer and an insert portion protruding from the layer portion to be inserted into the opening of the etch stop layer; forming a bottom electrode layer on the layer portion of the barrier layer opposite to the etch stop layer; forming a ferroelectric layer on the bottom electrode layer opposite to the barrier layer; and forming a top electrode layer on the ferroelectric layer opposite to the bottom electrode layer.
Inventor(s): Meng-Han Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B53/30, H10B43/20, H10B43/30, H10B51/20, H10B51/30, H10B53/20
CPC Code(s): H10B53/30
Abstract: a semiconductor device includes a first memory cell that includes: a first conductor structure extending along a first lateral direction; a first portion of a first memory film wrapping around a first portion of the first conductor structure; a first semiconductor film wrapping around the first portion of the first memory film; a second conductor structure extending along a vertical direction and coupled to a first sidewall of the first semiconductor film, wherein the first sidewall faces toward or away from a second lateral direction perpendicular to the first lateral direction; and a third conductor structure extending along the vertical direction and coupled to a second sidewall of the first semiconductor film, wherein the second sidewall faces toward or away from the second lateral direction.
Inventor(s): Chun-Tsung Kuo of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Wen Hsu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jiech-Fun Lu of Madou Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N79/00, H01L23/522, H01L23/528, H01L27/08
CPC Code(s): H01L28/20
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including a thin film resistor (tfr) layer overlying a semiconductor substrate. a first conductive structure is disposed on an outer region of the tfr layer. the first conductive structure comprises a lateral portion adjacent to a vertical portion. a height of the vertical portion is greater than a height of the lateral portion. a capping structure is disposed on a middle region of the tfr layer and abuts the vertical portion of the first conductive structure.
Inventor(s): Cheng-Wei CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ying LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yueh-Ching PAI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/28, H01L21/285
CPC Code(s): H01L29/66507
Abstract: in method of manufacturing a semiconductor device, a source/drain epitaxial layer is formed, one or more dielectric layers are formed over the source/drain epitaxial layer, an opening is formed in the one or more dielectric layers to expose the source/drain epitaxial layer, a first silicide layer is formed on the exposed source/drain epitaxial layer, a second silicide layer different from the first silicide layer is formed on the first silicide layer, and a source/drain contact is formed over the second silicide layer.
Inventor(s): Yu-Rui CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Zefu ZHAO of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Wen CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chee-Wee LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/51, H01L29/78
CPC Code(s): H01L29/6684
Abstract: a device includes a substrate, a semiconductor layer and a ferroelectric layer. the semiconductor layer is over the substrate. the semiconductor layer is a single crystal silicon layer or a single crystal germanium layer. the ferroelectric layer is over the semiconductor layer. the ferroelectric layer is in physical contact with the semiconductor layer and has an orthorhombic phase.
Inventor(s): Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L21/8238, H01L21/84, H01L27/12, H01L29/06
CPC Code(s): H01L29/775
Abstract: an integrated circuit (ic) device includes a first nanostructure, a second nanostructure, a first gate structure, a first source/drain epitaxial structure, and a dielectric isolation layer. the first nanostructure is spaced apart from a semiconductor substrate by a first spacing. the second nanostructure is above and spaced apart from the first nanostructure by a second spacing less than the first spacing. the first gate structure surrounds the first nanostructure and the second nanostructure. the first source/drain epitaxial structure is adjacent to both the first nanostructure and the second nanostructure. the dielectric isolation layer is between the first source/drain epitaxial structure and the semiconductor substrate. a top surface of the dielectric isolation layer is higher than a top surface of the semiconductor substrate and lower than a bottom surface of the first nanostructure.
Inventor(s): Wei-Lun Min of Nantou County (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Miao Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Huiling Shang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/08, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/785
Abstract: the present disclosure provides a semiconductor device and a method of forming the same. a method according one embodiment of the present disclosure include bonding a first semiconductor substrate having (110) orientation on a second semiconductor substate having (100) orientation, forming a stack over the first semiconductor substrate, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers, patterning the stack to form a fin-shape structure, the fin-shape structure comprising a channel region and a source/drain region, recessing the source/drain region to form a source/drain trench, forming a dielectric film in the source/drain trench, and epitaxially growing an epitaxial feature over the dielectric film, the epitaxial feature being in contact with the plurality of channel layers. the epitaxial feature has (110) orientation.
Inventor(s): Yi Hong Wang of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Hsuan Kung of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Lii Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsiao Chen of Taichung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/8238, H01L27/092, H01L29/10, H01L29/417, H01L29/66
CPC Code(s): H01L29/7851
Abstract: embodiments of the present disclosure provide a finfet semiconductor including a first set of fin structures that are active, a source/drain (s/d) region in contact with the first set of fin structures, a second set of fin structures separated, via a shallow trench isolation (sti) feature, from the first set of fin structures, a contact etch stop layer (cesl) over the s/d region and over the second set of fin structures, and a gate over the first set of fin structures and over the second set of fin structures, the gate including a gate dielectric and a gate electrode over the gate dielectric. the second set of fin structures includes one or more non-active fin structures that are in contact with the cesl without being in contact with the s/d region.
Inventor(s): Yi-Hong Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Hsuan Kung of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tien Yu Chu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsiao Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chen Li of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L27/092, H01L29/417
CPC Code(s): H01L29/7851
Abstract: a semiconductor structure includes a first circuit area having first fin active regions extending lengthwise along a first direction, each of the first fin active regions includes first channel regions; a second circuit area having second fin active regions extending lengthwise along the first direction, each of the second fin active regions includes second channel regions; a gate connector area between and separating the first and the second circuit areas, the gate connector area having filter fins extending lengthwise along the first direction; and a gate structure extending across the first circuit area, the gate connector area, and the second circuit area along a second direction over the first and second channel regions and the filter fins. a portion of the gate structure in the gate connector area has a greater resistivity than portions of the gate structure in the first and the second circuit areas.
Inventor(s): Yi Chen Ho of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Yiting Chang of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Lun-Kuang Tan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L27/092, H01L29/66
CPC Code(s): H01L29/7851
Abstract: in an embodiment, a method includes forming a plurality of semiconductor fins over a substrate, the plurality of semiconductor fins comprising a first fin, a second fin, a third fin, and a fourth fin; forming a first dielectric layer over the plurality of semiconductor fins, the first dielectric layer filling an entirety of a first trench between the first fin and the second fin; forming a second dielectric layer over the first dielectric layer, the second dielectric layer filling an entirety of a second trench between the second fin and the third fin, the forming the second dielectric layer comprising: forming an oxynitride layer; and forming an oxide layer; and forming a third dielectric layer over the second dielectric layer, the third dielectric layer filling an entirety of a third trench between the third fin and the fourth fin.
Inventor(s): Szu-Chien WU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yuan CHEN of HsinChu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh SU of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/285, H01L29/06, H01L29/423, H01L29/45, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/41733
Abstract: the present disclosure describes a semiconductor device having a dielectric structure between a source/drain (s/d) structure and a contact structure. the semiconductor device includes a s/d structure on a substrate, a dielectric structure on a top surface of the s/d structure, and a s/d contact structure on the s/d structure and the dielectric structure. a portion of the s/d contact structure is in contact with a top surface of the dielectric structure.
Inventor(s): Chung-Wei HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lung-Kun CHU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Ni YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Fu LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8238, H01L27/092, H01L29/06, H01L29/66, H01L29/775
CPC Code(s): H01L29/42392
Abstract: an integrated circuit includes a transistor having a plurality of stacked channels each extending between the source/drain regions of the transistor. the transistor also includes a hard mask nanostructure above the highest channel and extending between the source/drain regions of the transistor. a gate dielectric and gate metals wrap around the channels and the hard mask nanostructure.
Inventor(s): Chih-Wei LEE of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Han TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tai-Wei HWANG of Kinmen County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8238, H01L27/092, H01L29/06, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/42392
Abstract: an exemplary gate stack includes a gate dielectric (e.g., a high-k dielectric layer over an interfacial layer) and a gate electrode (e.g., a work function layer over the high-k dielectric layer, a cap over the work function layer, and a bulk fill layer over the cap). the gate stack wraps and/or surrounds a first semiconductor layer disposed over a second semiconductor layer. the gate dielectric and the work function layer (and not the cap and/or the bulk fill layer) fill a space between the first semiconductor layer and the second semiconductor layer. a ratio of oxygen in outer portions of the gate stack to inner portions of the gate stack may be about 1 to about 1.25. a thickness of the work function layer at inner portions of the gate stack may be less than a thickness of the work function layer at outer portions of the gate stack.
Inventor(s): Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh SU of Tianzhong Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Ting PAN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/423, H01L29/78
CPC Code(s): H01L29/78651
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes multiple first semiconductor nanostructures over a substrate and multiple second semiconductor nanostructures over the substrate. the semiconductor device structure also includes a dielectric structure between the first semiconductor nanostructures and the second semiconductor nanostructures. the semiconductor device structure further includes a metal gate stack wrapped around the first semiconductor nanostructures and the second semiconductor nanostructures. the metal gate stack has a gate dielectric layer and a gate electrode. the gate dielectric layer extends along a sidewall of a lower portion of the dielectric structure. a topmost surface of the gate dielectric layer is between a topmost surface of the first semiconductor nanostructures and a topmost surface of the dielectric structure.
Inventor(s): Jer-Fu Wang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Goutham Arutchelvan of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Sheng Yun of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Ching Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Iuliana Radu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/06, H01L29/26, H01L29/417, H01L29/423, H01L29/45, H01L29/66, H01L29/775
CPC Code(s): H01L29/78696
Abstract: a semiconductor device structure and a manufacturing method thereof are provided. the semiconductor device structure includes a substrate, complex two-dimensional material layers disposed over the substrate, a gate structure and source and drain regions. the complex two-dimensional material layers are arranged spaced apart from one each other and in parallel to one another. the gate structure is disposed across and wraps around and surrounds first portions of the complex two-dimensional material layers. the source and drain regions are disposed on opposite sides of the gate structure and wrap around and surround second portions of the complex two-dimensional material layers.
Inventor(s): Jung-Hung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Cheng CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Cheng TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/764, H01L29/08, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/0653
Abstract: a device includes: a substrate; a stack of semiconductor channels on the substrate; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; and a hybrid structure between the source/drain region and the substrate. the hybrid structure includes: a first semiconductor layer under the source/drain region; and an isolation region extending vertically from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer.
Inventor(s): Meng-Hsuan HSIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Winnie Victoria Wei-Ning CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Tung Ying LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/10, H01L21/8238, H01L27/092, H01L29/06, H01L29/165, H01L29/66, H01L29/786
CPC Code(s): H01L29/1083
Abstract: semiconductor structures and methods for forming the same are provided. the semiconductor structure includes a first transistor over a substrate, including a first channel layer over the substrate, a second channel layer over and spaced apart from the first channel layer in a first direction, and a first source/drain structure attached to the first channel layer and the second channel layer. the semiconductor structure further includes a second transistor over the substrate, including a third channel layer over the substrate, a fourth channel layer over and spaced apart from the third channel layer in the first direction, and a second source/drain structure attached to the third channel layer and the fourth channel layer. in addition, a dimension of the first source/drain structure in the first direction is different from a dimension of the second source/drain structure in the first direction.
Inventor(s): Georgios Vellianitis of Heverlee (BE) for taiwan semiconductor manufacturing company, ltd., Gerben Doornbos of Kessel-Lo (BE) for taiwan semiconductor manufacturing company, ltd., Marcus Johannes Henricus Van Dal of Linden (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/22, H01L29/78
CPC Code(s): H01L29/22
Abstract: a semiconductor device and a manufacturing method thereof are provided. the semiconductor device has a semiconductor layer and a gate structure located on the semiconductor layer. the semiconductor device has source and drain terminals disposed on the semiconductor layer, and a binary oxide layer located between the semiconductor layer and the source and drain terminals.
Inventor(s): I-Chih CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Shang HSIAO of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Pin LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Mu HUANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Tsun TSAI of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/423
CPC Code(s): H01L29/6656
Abstract: a semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.
Inventor(s): Chuan-Hui LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Feng SHIEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Jhih KUO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Wen HSIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/033, H01L21/308
CPC Code(s): H01L21/823418
Abstract: in a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, a groove pattern is formed in the hard mask layer, one or more first resist layers are formed over the hard mask layer having the groove pattern, a first photo resist pattern is formed over the one or more first resist layers, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer with the groove pattern are patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.
Inventor(s): Kuei-Yu Kao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chiung-Yu Cho of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Ching Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/311, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L21/823481
Abstract: provided are devices and methods for forming devices. a method includes forming structures over a substrate; forming a layer between the structures; performing a first etch process to recess the layer to a surface having a serrated profile; optionally forming a film or films over the surface, wherein the film or films retain the serrated profile; depositing a material over the substrate; selectively masking the material to define a masked portion of the material and an unmasked portion of the material; and performing a second etch process to etch a portion of the material and form the material with a sidewall, wherein the second etch process uncovers the serrated profile, and wherein during the second etch process ions are reflected from the serrated profile.
Inventor(s): Chien-Te TU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Cheng LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chee-Wee LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/822, H01L21/761, H01L21/8238, H01L27/06, H01L27/092, H01L27/12, H01L29/06, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L21/8221
Abstract: a device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. the bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. the first source/drain epitaxial structures are on opposite sides of the first channel layer. the first gate structure is around the first channel layer. the top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. the second source/drain epitaxial structures are on opposite sides of the second channel layer. the second gate structure is around the second channel layer. the epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.
Inventor(s): Shu-Uei Jang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Yuan Ku of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L27/092
CPC Code(s): H01L21/823481
Abstract: a semiconductor device includes a first transistor, a second transistor, a third transistor, and a fourth transistor. the first and second transistors operate under a lower gate voltage than the third and fourth transistors. the first transistor has a first active gate structure and the second transistor has a second active gate structure. the first and second active gate structures are separated by a first gate isolation structure along a first direction. the third transistor has a third active gate structure and the fourth transistor has a fourth active gate structure. the third and fourth active gate structures are separated by a second gate isolation structure along the first direction. the variation of a first distance between respective sidewalls of the first gate isolation structure is equal to the variation of a second distance between respective sidewalls of the second gate isolation structure along the first direction.
Inventor(s): Chien-Yao HUANG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Wun-Jie LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei HSU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ti SU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L27/02, H01L27/08, H01L29/06, H01L29/08, H01L29/861, H01L29/94
CPC Code(s): H01L27/0928
Abstract: capacitor cells are provided. a first pmos transistor has a source connected to a power supply and a drain connected to a first node. a first nmos transistor has a source connected to a ground and a drain connected to a second node. a second pmos transistor has a source connected to the second node and a drain connected to the first node. a second nmos transistor has a source connected to the ground and a drain connected to the first node. a first p+ doped region is shared by drains of the first and second pmos transistors. a first gate metal is between the first p+ doped region and a second p+ doped region. a first n+ doped region is shared by sources of the first and second nmos transistors. a second gate metal is between the first n+ doped region and a second n+ doped region.
Inventor(s): Wei-Hsin TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Chun TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L21/8238, H01L23/522, H01L27/092
CPC Code(s): H01L27/0207
Abstract: a semiconductor device, includes a first metal layer, a second metal layer, and at least one conductive via. the first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction. the second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. the at least one conductive via connects the first conductor and the second conductor through the third conductor. the semiconductor device further includes at least one of a first gate electrode that extends in the second direction and is connected to the first conductor, or a drain/source contact that extends in the second direction and is connected to the second conductor.
Inventor(s): Li-Wen HUANG of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Liang CHENG of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Hao LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng LEE of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14623
Abstract: an electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. by using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. as a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.
Inventor(s): Yen-Ting Chiang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Yu Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Jui Wang of Fengshan City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1463
Abstract: in some embodiments, the present disclosure relates to an image sensor including a substrate having a first side and a second side opposite the first side; a photodetector region within the substrate; a gate structure on the first side of the substrate over the photodetector region; a deep trench isolation (dti) structure surrounding the photodetector region and extending from the first side of the substrate to the second side; a doped floating node region within the substrate at the first side and disposed between the gate structure and the dti structure; and a floating node on the first side of the substrate, contacting a top surface of the dti structure and overlying the doped floating node region.
Inventor(s): Yu Chi LIU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chieh-Jung LI of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Wen CHANG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N30/00, H10N30/078, H10N30/079, H10N30/50, H10N30/853
CPC Code(s): H10N30/708
Abstract: a diffusion barrier layer is included in a piezoelectric device that includes a plurality of piezoelectric layers. the diffusion barrier layer may be included to trap and/or block lead (pb) and/or lead oxide (pbo) from diffusing toward a first piezoelectric layer that occurs during a sol-gel process that used to form a second piezoelectric layer after the first piezoelectric layer formed. blocking and/or trapping the diffusion of lead (pb) and/or lead oxide (pbo) using the diffusion barrier layer may reduce the likelihood of and/or prevent delamination in the piezoelectric device.
Inventor(s): Che-Hao CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jiun-Yun LI of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Cheng LI of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Jul WU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N60/80, G06N10/40, H10N60/01, H10N60/10
CPC Code(s): H10N60/80
Abstract: an electronic device includes a substrate, a hyperbolic magnet, a pair of depletion gates, a pair of barrier gates and a accumulation gate. the hyperbolic magnet is over the substrate and has a first magnet portion and a second magnet portion separated from each other. the first magnet portion and the second magnet portion have a first convex surface and a second convex surface facing the first convex surface, respectively. the depletion gates are separated from each other and between the first convex surface and the second convex surface over the substrate. the barrier gates are between the depletion gates. the accumulation gate is over the depletion gates and between the barrier gates.
Taiwan Semiconductor Manufacturing Company, LTD. patent applications on February 27th, 2025
- Taiwan Semiconductor Manufacturing Company, LTD.
- B01D46/10
- B01D29/01
- B01D35/30
- B01D39/20
- B01D61/18
- H01L21/673
- CPC B01D46/10
- Taiwan semiconductor manufacturing company, ltd.
- C23C14/04
- C23C14/34
- C23C14/50
- C23C14/54
- C23C14/58
- CPC C23C14/046
- F26B11/00
- F26B21/10
- CPC F26B11/00
- G02B6/12
- G02B6/122
- G02B6/13
- CPC G02B6/12004
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- H01L33/00
- CPC G02B6/428
- G03F1/82
- G03F7/20
- CPC G03F1/82
- G03F7/09
- G03F7/004
- G03F7/105
- G03F7/11
- H01L21/027
- H01L21/308
- CPC G03F7/094
- G03F7/00
- G05B19/4155
- G06N20/00
- CPC G03F7/70866
- G06F7/499
- CPC G06F7/49915
- G06F30/327
- G06F30/392
- G06F30/398
- CPC G06F30/327
- G06F30/31
- CPC G06F30/392
- G11C7/06
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- CPC G11C7/065
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- CPC G11C11/4096
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- G11C16/26
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- CPC G11C16/0433
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- H10B20/00
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- CPC G11C17/16
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- CPC H01L21/0206
- H01L21/3065
- H01L21/762
- H01L21/8234
- CPC H01L21/31105
- H01L21/67
- B08B1/12
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- CPC H01L21/67046
- H01L21/683
- H01L21/66
- CPC H01L21/6833
- H01L21/687
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- CPC H01L21/68785
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- CPC H01L21/76898
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- CPC H01L21/78
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- CPC H01L23/3114
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- CPC H01L23/3675
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- CPC H01L23/373
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- CPC H01L23/481
- H01L29/06
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- H10B10/00
- CPC H01L23/49503
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- CPC H01L23/49816
- H01L27/06
- CPC H01L23/49827
- CPC H01L23/49838
- H10B51/20
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- CPC H01L23/5283
- CPC H01L23/5329
- H01L23/482
- CPC H01L23/562
- H01L23/16
- H01L23/544
- H01L29/66
- CPC H01L23/564
- G11C17/18
- CPC H01L23/573
- CPC H01L24/05
- CPC H01L24/08
- B23K1/008
- B23K101/40
- CPC H01L24/75
- CPC H01L25/0657
- G11C5/04
- G11C5/06
- H10B61/00
- H02M3/07
- H02M3/158
- CPC H02M3/07
- CPC H10B10/125
- CPC H10B20/25
- H10B51/10
- H10B53/20
- CPC H10B51/20
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- CPC H10B53/30
- H10B43/20
- H10B43/30
- H10N79/00
- H01L27/08
- CPC H01L28/20
- H01L21/28
- H01L21/285
- CPC H01L29/66507
- H01L29/51
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- CPC H01L29/6684
- H01L21/8238
- H01L21/84
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- CPC H01L29/775
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- H01L29/423
- CPC H01L29/785
- H01L27/092
- H01L29/10
- CPC H01L29/7851
- H01L29/45
- CPC H01L29/41733
- CPC H01L29/42392
- CPC H01L29/78651
- H01L29/26
- CPC H01L29/78696
- H01L21/764
- CPC H01L29/0653
- H01L29/165
- CPC H01L29/1083
- H01L29/22
- CPC H01L29/22
- H01L27/088
- CPC H01L29/6656
- H01L21/033
- CPC H01L21/823418
- CPC H01L21/823481
- H01L21/822
- H01L21/761
- CPC H01L21/8221
- H01L27/02
- H01L29/861
- H01L29/94
- CPC H01L27/0928
- CPC H01L27/0207
- H01L27/146
- CPC H01L27/14623
- CPC H01L27/1463
- H10N30/00
- H10N30/078
- H10N30/079
- H10N30/50
- H10N30/853
- CPC H10N30/708
- H10N60/80
- G06N10/40
- H10N60/01
- H10N60/10
- CPC H10N60/80