Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on March 20th, 2025
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on March 20th, 2025
Taiwan Semiconductor Manufacturing Co., Ltd.: 84 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L29/66 (20), H01L29/423 (15), H01L29/06 (14), H01L21/768 (13), H01L29/78 (13) H10D84/038 (4), H01L25/0657 (3), H10D64/017 (3), H10D30/6729 (2), H10D30/6219 (2)
With keywords such as: layer, structure, semiconductor, dielectric, gate, device, substrate, forming, memory, and region in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Chia-Hsi WANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yen-Yu CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yi-Chih CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shih-Wei BIH of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): C23C14/34, C23C14/14, H01J37/34, H01L21/285, H01L21/768, H01L23/532
CPC Code(s): C23C14/3407
Abstract: a physical vapor deposition (pvd) target for performing a pvd process is provided. the pvd target includes a backing plate and a target plate coupled to the backing plate. the target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. the sputtering source material includes a diffusion barrier material.
20250092892. GAS TRANSPORT SYSTEM_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Jheng-Syun LI of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Mao-Chou HUANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): F15D1/06, C23C16/44, C23C16/455, C23C16/50, H01J37/32, H01L21/67
CPC Code(s): F15D1/06
Abstract: a conduit system for transporting gas from a gas containing chamber for processing a substrate from which semiconductor devices are formed includes a liner with a spiral vent. the conduit system utilizes a curtain of gas to prevent or reduce deposition of material onto an inner surface of the conduit transporting the gas from the gas containing chamber.
Inventor(s): Ju-Ying CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Che-Yen LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chia-Fong CHANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hua-Tai LIN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Te-Chih HUANG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chi-Yuan SUN of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Jiann Yuan HUANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01N21/95, G01N21/88
CPC Code(s): G01N21/9501
Abstract: in a method for inspecting pattern defects, a plurality of patterns are formed over an underlying layer. the plurality of patterns are electrically isolated from each other. a part of the plurality of patterns are scanned with an electron beam to charge the plurality of patterns. an intensity of secondary electrons emitted from the scanned part of the plurality of patterns is obtained. one or more of the plurality of patterns that show an intensity of the secondary electrons different from others of the plurality of patterns are searched.
Inventor(s): Tai-Chun Huang of New Taipei TW for taiwan semiconductor manufacturing co., ltd., Stefan Rusu of Sunnyvale CA US for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/12, G02B1/00, G02B6/124, G02B6/34, G02B6/42
CPC Code(s): G02B6/12002
Abstract: a vertical grating coupler is disclosed. the grating coupler includes a first waveguide having a first grating, a second waveguide having a second grating, and a dielectric layer positioned between the first waveguide and the second waveguide. the first grating includes a plurality of first grating ridges separated by a plurality first grating gaps, and the second grating includes a plurality of second grating ridges separated by a plurality second grating gaps. the first grating, the second grating, and the dielectric layer are located in a vertical overlap region between the first waveguide and the second waveguide. the first grating and the second grating have different grating periods, and each of the plurality of first grating gaps and second grating gaps are filled with the dielectric layer.
Inventor(s): Wen-Chih Lin of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd., Cheng-Yu Kuo of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Yen-Hung Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsuan-Ting Kuo of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Chia-Shen Cheng of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Chao-Wei Li of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ching-Hua Hsieh of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wen-Chih Chiou of Zhunan Township TW for taiwan semiconductor manufacturing co., ltd., Ming-Fa Chen of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Shang-Yun Hou of Jubei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4214
Abstract: optical devices and methods of manufacture are presented in which a mirror structure is utilized to transmit and receive optical signals to and from an optical device. in embodiments the mirror structure receives optical signals from outside of an optical device and directs the optical signals through at least one mirror to an optical component of the optical device.
Inventor(s): Lee-Feng CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yen-Liang CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chien-Min LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuo Lun TAI of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shy-Jay LIN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/24
CPC Code(s): G03F1/24
Abstract: an euv lithography mask including a substrate, a patterned absorber layer including a first material and a second material. in some embodiments, the first material is a second row transition metal and the second material is a first row transition metal or second row transition metal. the disclosed euv lithography masks reduce undesirable mask 3d effects.
Inventor(s): Chih-Tsung SHIH of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Tsung-Chih CHIEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shih-Chi FU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chi-Hua FU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuotang CHENG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Bo-Tsun LIU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Tsung Chuan LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/24, G03F1/22, G03F1/38, G03F1/46, G03F7/20
CPC Code(s): G03F1/24
Abstract: an extreme ultraviolet (euv) mask includes a multilayer mo/si stack comprising alternating mo and si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (ru) disposed over the multilayer mo/si stack, and an absorber layer on the capping layer. the euv mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.
Inventor(s): Li-Po YANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wei-Han LAI of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/004, C08F212/14, C08F220/38, G03F7/038, G03F7/039, G03F7/16, G03F7/20, G03F7/36, G03F7/38
CPC Code(s): G03F7/0045
Abstract: method of forming pattern in photoresist layer includes forming photoresist layer over substrate, selectively exposing photoresist layer to actinic radiation forming latent pattern. latent pattern is developed by applying developer to form pattern. photoresist layer includes photoresist composition including polymer:
Inventor(s): Li-Po YANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wei-Han LAI of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/004, C08F212/14, C08F220/38, G03F7/038, G03F7/039, G03F7/16, G03F7/20, G03F7/36, G03F7/38
CPC Code(s): G03F7/0045
Abstract:
Inventor(s): Li-Po YANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wei-Han LAI of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/004, C08F212/14, C08F220/38, G03F7/038, G03F7/039, G03F7/16, G03F7/20, G03F7/36, G03F7/38
CPC Code(s): G03F7/0045
Abstract: a, a, l are direct bond, c4-c30 aromatic, c4-c30 alkyl, c4-c30 cycloalkyl, c4-c30 hydroxylalkyl, c4-c30 alkoxy, c4-c30 alkoxyl alkyl, c4-c30 acetyl, c4-c30 acetylalkyl, c4-c30 alkyl carboxyl, c4-c30 cycloalkyl carboxyl, c4-c30 hydrocarbon ring, c4-c30 heterocyclic, —coo—, a1 and a2 are not both direct bonds, and are unsubstituted or substituted with a halogen, carbonyl, or hydroxyl; ais c6-c14 aromatic, wherein ais unsubstituted or substituted with halogen, carbonyl, or hydroxyl; ris acid labile group; ra, rb are h or c1-c3 alkyl; ris direct bond or c1-c5 fluorocarbon; pag is photoacid generator; 0<x/(x+y+z)<1, 0<y/(x+y+z)<1, and 0<z/(x+y+z)<1.
Inventor(s): Chieh-Hsin HSIEH of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wei-Han LAI of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/09, G03F7/004, G03F7/105, H01L21/027
CPC Code(s): G03F7/094
Abstract: a method of manufacturing a semiconductor device includes forming a first layer including an organic material over a substrate. a second layer including a reaction product of a silicon-containing material and a photoacid generator is formed over the first layer. a photosensitive layer is formed over the second layer, and the second layer is patterned.
Inventor(s): Yen-Hsun CHEN of Taipei TW for taiwan semiconductor manufacturing co., ltd., Yi-Zhen CHEN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Jhan-Hong YEH of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Han-Lung CHANG of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Tzung-Chi FU of Miaoli City TW for taiwan semiconductor manufacturing co., ltd., Li-Jui CHEN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/00, H01L21/673, H01L21/683, H01L21/687
CPC Code(s): G03F7/70741
Abstract: a reticle carrier described herein is configured to quickly discharge the residual charge on a reticle so as to reduce, minimize, and/or prevent particles in the reticle carrier from being attracted to and/or transferred to the reticle. in particular, the reticle carrier may be configured to provide reduced capacitance between an inner baseplate of the reticle carrier and the reticle. the reduction in capacitance may reduce the resistance-capacitance (rc) time constant for discharging the residual charge on the reticle, which may increase the discharge speed for discharging the residual charge through support pins of the reticle carrier. the increase in discharge speed may reduce the likelihood that an electrostatic force in the reticle carrier may attract particles in the reticle carrier to the reticle. this may reduce pattern defects transferred to substrates that are patterned using the reticle, may increase semiconductor device manufacturing quality and yield, and may reduce scrap and rework of semiconductor devices and/or wafers.
Inventor(s): Win-San Khwa of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jui-Jen Wu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Meng-Fan Chang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ping-Chun Wu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ho-Yu Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F7/499, G06F7/50
CPC Code(s): G06F7/49915
Abstract: a circuit includes local computing cells. each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a first data type, a first sum including (i) a first product of a first input data element and a first weight data element; and (ii) a second product of a second input data element and a second weight data element. each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a second data type, (i) a second sum of a first portion of a third input data element and a first portion of a third weight data element; and (ii) a third product of a second portion of the third input data element and a second portion of the third weight data element.
Inventor(s): Yu-Der CHIH of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hidehiro FUJIWARA of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yi-Chun SHIH of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Po-Hao LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yen-Huei CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chia-Fu LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jonathan Tsung-Yung CHANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F7/501, G06F7/53, G11C7/10, G11C11/4074
CPC Code(s): G06F7/501
Abstract: a memory circuit includes a column of memory cells configured to receive a set of kth bits of a number h of bits of each input data element of a plurality of input data elements, and each memory cell of the column of memory cells is configured to multiply the kth bit of a corresponding input data element of the plurality of data elements with a first weight data element stored in the memory cell, and to generate a corresponding first product data element. the memory circuit includes an adder tree configured to generate a summation data element based on each of the first product data elements.
20250094682. Analog ECO Flow_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Ayushi Agrawal of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yu-Tao Yang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ming-Cheng Syu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wen-Shen Chou of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yung-Chow Peng of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/398, G06F30/394
CPC Code(s): G06F30/398
Abstract: methods of designing integrated circuits incorporating an analog eco flow are provided. an example method comprises receiving an initial design and performing an auto-marker process. the auto-marker process comprises performing a first auto-marker process to surround a first plurality of active cells of the design with first computer-aided design (cad) layers corresponding to a first plurality of engineering change order (eco) cells, performing an enhanced auto-marker process to cover irregular shapes of the design with second cad layers corresponding to a second plurality of eco cells, and performing a second auto-marker process to fill empty areas of the design with third cad layers corresponding to a third plurality of eco cells. the method further includes filling the design with the first plurality of eco cells, the second plurality of eco cells, and the third plurality of eco cells.
Inventor(s): Yi-Chun Shih of Taipei TW for taiwan semiconductor manufacturing co., ltd., Chia-Fu Lee of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yu-Der Chih of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Jonathan Tsung-Yung Chang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C7/12, G11C5/06, G11C7/10, G11C16/04, G11C16/30
CPC Code(s): G11C7/12
Abstract: systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. a voltage of the bit line is driven by the plurality of computing cells.
Inventor(s): Motoki TAMURA of Kawasaki city JP for taiwan semiconductor manufacturing co., ltd., Makoto YABUUCHI of Tokyo JP for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/408, G11C11/4074, G11C11/4099
CPC Code(s): G11C11/4085
Abstract: a memory driver includes a word line driver circuit, a reference circuit, and a bias circuit. the word line driver circuit is coupled to a word line and configured to selectively provide a reference voltage from a reference node to the word line according to an input signal. the reference circuit has a capacitor coupled to the reference node. the reference circuit is configured to store the reference voltage on the capacitor and lower the reference voltage from a first voltage level to a second voltage level when the reference voltage is provided by the word line driver circuit from the reference node to the word line. the bias circuit coupled to the reference node and configured to regulate the reference voltage at the reference node by the second voltage level.
Inventor(s): Atul Katoch of Kanata CA for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/418, G11C11/417
CPC Code(s): G11C11/418
Abstract: signal edge sharpener circuitry is operably connected to the word lines in a memory array to pull up a rising edge of a signal on the word line and/or to pull down a falling edge of the signal on the word line. pulling the signal up and/or down reduces the amount of time the word line is asserted and reduces the amount of time between precharge operations.
Inventor(s): Hengyuan Lee of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Yu-Sheng Chen of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd., Xinyu BAO of Fremont CA US for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/004
Abstract: a memory circuit and a method for reading a memory circuit are provided. the memory circuit includes reference memory cells and operation memory cells. the method includes reading a selected reference memory cell at a first time to get a first voltage; reading the selected reference memory cell at a second time after the first time to get a second voltage; adjusting a read voltage of the memory cell to be an adjusted read voltage of the memory cell according to the voltage difference between the first voltage and the second voltage; applying the adjusted read voltage on a selected operation memory cell corresponding to the selected reference memory cell; and applying the adjusted read voltage on other selected operation memory cells in a same row of the memory array corresponding to the selected reference memory cell. the time difference between the first time and the second time is within a range smaller than a predetermined time difference according to characteristics of a corresponding selector in the selected reference memory cell or the selected operation memory cell.
Inventor(s): Chin-I SU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chung-Cheng CHOU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yu-Der CHIH of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Zheng-Jun LIN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/0069
Abstract: a method of operating a memory circuit includes generating, by a first memory cell array, a first current in response to a first voltage, generating, by a tracking circuit, a second set of leakage currents, generating, by a first current source, a second write current, and mirroring, by a first current mirror. the first current includes a first set of leakage currents and a first write current. the first current is in a first path with a second current in a second path. the second current includes the second set of leakage currents and the second write current. the first write current corresponds to the second write current. the first set of leakage currents corresponds to the second set of leakage currents. the second set of leakage currents is configured to track the first set of leakage currents of the first memory cell array.
Inventor(s): Jui-Jen Wu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jen-Chieh Liu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yi-Lun Lu of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Win-San Khwa of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Meng-Fan Chang of Taichung City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C29/46, G11C7/24, G11C29/12, G11C29/50
CPC Code(s): G11C29/46
Abstract: a memory test circuit is provided. the memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.
Inventor(s): Tsung-Han KUO of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Po-Shu WANG of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Wei-Ming WANG of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01J37/34, C23C14/35, H01J37/32, H10N50/01
CPC Code(s): H01J37/3458
Abstract: a system and method for reducing particle contamination on substrates during a deposition process using a particle control system is disclosed here. in one embodiment, a film deposition system includes: a processing chamber sealable to create a pressurized environment and configured to contain a plasma, a target and a substrate in the pressurized environment; and a particle control unit, wherein the particle control unit is configured to provide an external force to each of at least one charged atom and at least one contamination particle in the plasma, wherein the at least one charged atom and the at last one contamination particle are generated by the target when it is in direct contact with the plasma, wherein the external force is configured to direct the at least one charged atom to a top surface of the substrate and to direct the at least one contamination particle away from the top surface of the substrate.
Inventor(s): Shih-Chi FU of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Kuei-Shun CHEN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Hsiang-Yu SU of New Taipei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/027, G03F7/00, G03F9/00, H01L21/311, H01L21/768, H01L23/544
CPC Code(s): H01L21/027
Abstract: a method includes forming a photoresist layer over a wafer; aligning a first photomask with a first area of the wafer; performing a first exposure process to a first portion of the photoresist layer within the first area of the wafer; aligning a second photomask with a second area of the wafer, wherein aligning the first photomask and aligning the second photomask are performed using an alignment mark within a stitching zone of the wafer, the stitching zone being an overlapping region of the first area and the second area; performing a second exposure process to a second portion of the photoresist layer within the second area of the wafer; and performing a development process to remove the first and second portions of the photoresist layer.
Inventor(s): Ya-Ting Lin of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yen-Ting Chen of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Wei-Han Lai of Taipei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/027, C08L25/08, G03F7/09, G03F7/34
CPC Code(s): H01L21/0276
Abstract: methods for making a semiconductor device using an improved barc (bottom anti-reflective coating) are provided herein. the improved barc comprises a polymer formed from at least a styrene monomer having at least one or two hydrophilic substituents. the monomer(s) and substituents can be varied as desired to obtain a balance between film adhesion and wet etch resistance. also provided is a semiconductor device produced using such methods.
Inventor(s): Kai-Chieh Yang of Kaohsiung TW for taiwan semiconductor manufacturing co., ltd., Kuan-Kan Hu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wei-Yen Woon of Taoyuan TW for taiwan semiconductor manufacturing co., ltd., Ku-Feng Yang of Baoshan Township TW for taiwan semiconductor manufacturing co., ltd., Szuya Liao of Zhubei TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/28, H01L21/822, H01L27/12, H01L29/49, H01L29/775, H01L29/786
CPC Code(s): H01L21/28088
Abstract: a method of forming a semiconductor device includes depositing a target metal layer in an opening. depositing the target metal layer comprises performing a plurality of deposition cycles. an initial deposition cycle of the plurality of deposition cycles comprises: flowing a first precursor in the opening, flowing a second precursor in the opening after flowing the first precursor, and flowing a reactant in the opening. the first precursor attaches to upper surfaces in the opening, and the second precursor attaches to remaining surfaces in the opening. the first precursor does not react with the second precursor, and the reactant reacts with the second precursor at a greater rate than the reactant reacts with the first precursor.
Inventor(s): Hsien-Wei Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L23/538, H01L25/00, H01L25/065, H01L25/10
CPC Code(s): H01L21/56
Abstract: packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. in some embodiments, a packaged semiconductor device includes an integrated circuit die and a first interconnect structure coupled to the integrated circuit die. through-vias are also coupled to the first interconnect structure. a molding material is disposed around the integrated circuit die and the through-vias over the first interconnect structure. the molding material has a pit disposed therein. a recovery material is disposed within the pit in the molding material. a second interconnect structure is disposed over the molding material, the recovery material, the integrated circuit die, and the through-vias.
Inventor(s): Yu-Meng Ou of Taoyuan TW for taiwan semiconductor manufacturing co., ltd., Kei-Wei Chen of Tainan TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/67, H01L21/687
CPC Code(s): H01L21/67126
Abstract: in an embodiment, a bevel sealing system includes a dispensing chamber that includes a first chuck configured to support a workpiece, the workpiece including a first wafer bonded to a second wafer, where the first wafer and the second wafer include beveled edges, a sealant dispenser configured to apply sealant along a perimeter of a bonding interface between the first wafer and the second wafer, a first charge-coupled device (ccd) camera configured to capture 2-dimensional (2d) images of edges of the workpiece, and a first laser edge profiler configured to measure and collect profile data of the edges of the workpiece.
Inventor(s): Ren-Hau WU of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Yan-Han CHEN of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Cheng-Kang HU of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Feng-Kuang WU of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Hsu-Shui LIU of Pingjhen City, Taoyuan County TW for taiwan semiconductor manufacturing co., ltd., Jiun-Rong PAI of Jhubei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/687, B25J9/16, B65G47/90, H01L21/67, H04N23/56
CPC Code(s): H01L21/68707
Abstract: apparatus and methods for handling semiconductor part carriers are disclosed. in one example, an apparatus for handling semiconductor part carriers is disclosed. the apparatus includes a mechanical arm and an imaging system coupled to the mechanical arm. the mechanical arm is configured for holding a semiconductor part carrier. the imaging system is configured for automatically locating a goal position on a surface onto which the semiconductor part carrier is to be placed.
Inventor(s): Gulbagh SINGH of Tainan City 741 TW for taiwan semiconductor manufacturing co., ltd., Tsung-Han TSAI of Miaoli County 350 TW for taiwan semiconductor manufacturing co., ltd., Shih-Lu HSU of Tainan City 741 TW for taiwan semiconductor manufacturing co., ltd., Kun-Tsang CHUANG of Miaoli County 360 TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/285, H01L23/532, H01L23/535, H01L29/45, H01L29/78
CPC Code(s): H01L21/7682
Abstract: a semiconductor device may include a source on a first side of a gate. the semiconductor device may include a drain on a second side of the gate, where the second side of the gate is opposite to the first side of the gate. the semiconductor device may include a first contact over the source. the semiconductor device may include a second contact over the drain. the semiconductor device may include an air gap over the gate between at least the first contact and the second contact. the semiconductor device may include at least two dielectric materials in each of a region between the air gap and the first contact and a region between the air gap and the second contact.
Inventor(s): Yu-Lien HUANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/528, H01L29/40, H01L29/423
CPC Code(s): H01L21/76831
Abstract: a device which includes a conductive element at least partially in a substrate; a dielectric material over the conductive element; a contact electrically connecting to the conductive element; and a dielectric liner between the contact and the dielectric material, wherein the dielectric liner has a liner thickness of not less than 0.5 nanometers (nm) and not greater than 10 nm.
Inventor(s): Meng-Han Chou of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Su-Hao Liu of Jhongpu Township TW for taiwan semiconductor manufacturing co., ltd., Kuo-Ju Chen of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Liang-Yin Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Huicheng Chang of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Yee-Chia Yeo of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/285, H01L21/311, H01L21/3213, H01L21/3215, H01L23/532, H01L23/535, H01L29/08, H01L29/417, H01L29/45, H01L29/66, H01L29/78
CPC Code(s): H01L21/76895
Abstract: a method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.
Inventor(s): Te-Chih Hsiung of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Yi-Chen Wang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Guang-Hong Cheng of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Wen Wang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yuan-Tien Tu of Puzih City TW for taiwan semiconductor manufacturing co., ltd., Huan-Just Lin of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532, H01L29/423, H01L29/78, H01L29/786
CPC Code(s): H01L21/76897
Abstract: a semiconductor device includes a channel structure, a first gate structure straddling the channel structure, and an epitaxial structure. the epitaxial structure is adjacent to the first gate structure and is coupled to an end of the channel structure. the semiconductor device further includes a first contact structure disposed over and in contact with the epitaxial structure and a nitride-based conformal layer extending at least over the first contact structure. the semiconductor device further includes an oxide-based layer disposed over the nitride-based conformal layer. a portion of the nitride-based conformal layer, disposed over the first contact structure, has a dip that is filled with a first portion of the oxide-based layer.
Inventor(s): Wei-Chung Chang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ming-Che Ho of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/48, H01L23/498, H01L25/10
CPC Code(s): H01L21/76898
Abstract: semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. first barrier layer extends on backside surface. second barrier layer extends along sidewalls of through hole and on frontside surface. routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. first routing pattern extends over first barrier layer on backside surface and over routing via. first routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. second routing pattern extends over second barrier layer on frontside surface. second routing pattern directly contacts another end of routing via. semiconductor die is electrically connected to routing via by first routing pattern.
Inventor(s): Wei-Chih Chen of Taipei TW for taiwan semiconductor manufacturing co., ltd., Sih-Hao Liao of New Taipei TW for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang Hu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/31, H01L23/498
CPC Code(s): H01L23/3178
Abstract: a redistribution structure is made using filler-free insulating materials with high shrinkage rate. as a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.
Inventor(s): Tsunyen Wu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Po-Yao Lin of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Sing-Da Jiang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shih-Wei Liu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kathy Yan of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/40, H01L23/00, H01L23/44, H01L25/00, H01L25/065
CPC Code(s): H01L23/4012
Abstract: provided are integrated circuit systems and methods for fabricating semiconductor packages. an integrated circuit system includes a circuit board having a top side and a bottom side and defining an opening from the top side to the bottom side; a bottom boiling plate having a recessed portion and having a projection with a terminal surface, wherein the recessed portion is located below the bottom side of the circuit board, wherein the projection extends through the opening, and wherein the terminal surface is located above the top side of the circuit board; a semiconductor substrate located over the top side of the circuit board and including semiconductor devices; and a top boiling plate located over the semiconductor substrate, wherein the bottom boiling plate and the top boiling plate are configured to dissipate heat away from the integrated circuit system.
Inventor(s): Jui-Lin CHEN of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Feng-Ming CHANG of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Ping-Wei WANG of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L23/522, H01L23/528, H10B10/00
CPC Code(s): H01L23/481
Abstract: an integrated circuit includes a first sram cell and a second sram cell, each including a plurality of field-effect transistors (fets), a front metal line over the fets and a back metal line below the fets, and a middle strap area disposed between the first sram cell and the second sram cell. the middle strap area includes a plurality of gate stacks extending lengthwise along a direction, a gate isolation structure extending through a gate stack of the plurality of gate stacks, a feedthrough via (ftv) embedded in the gate isolation structure, a first dielectric gate disposed between the conductive structure and the first sram cell, and a second dielectric gate disposed between the conductive structure and the second sram cell. the ftv electrically couples the front metal line and the back metal line.
Inventor(s): Che-Yu Yeh of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Tsung-Shu Lin of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Wei-Cheng Wu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Tsung-Yu Chen of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Li-Han Hsu of Hsin-Chu City TW for taiwan semiconductor manufacturing co., ltd., Chien-Fu Tseng of Taipei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/498, H01L23/00, H01L23/48, H01L25/065
CPC Code(s): H01L23/49822
Abstract: a stacked via structure disposed on a conductive pillar of a semiconductor die is provided. the stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. the first dielectric layer covers the semiconductor die. the first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. the first redistribution wiring covers the first conductive via and the first dielectric layer. the second dielectric layer covers the first dielectric layer and the first redistribution wiring. the second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. the second redistribution wiring covers the second conductive via and the second dielectric layer. a lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
Inventor(s): Shih-Yu LIAO of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chung-Liang Cheng of Changhua TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
CPC Code(s): H01L23/5228
Abstract: the present disclosure describes a resistor structure with a dielectric layer, trenches, a metal layer, a semiconductor layer, and an insulating layer. the dielectric layer is disposed above electrical components formed on a substrate. the trenches are disposed in the dielectric layer and separated from each other by a dielectric region of the dielectric layer. the metal layer is disposed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. the semiconductor layer is disposed on a bottom surface, side surfaces, and a top surface of the metal layer. the insulating layer is disposed in the trenches and in contact with side surfaces of the semiconductor layer and on a top surface of the semiconductor layer.
Inventor(s): Hsien-Chang WU of Taichung TW for taiwan semiconductor manufacturing co., ltd., Shih-Kang FU of Taoyuan TW for taiwan semiconductor manufacturing co., ltd., Shin-Yi YANG of New Taipei TW for taiwan semiconductor manufacturing co., ltd., Gary LIU of Taichung TW for taiwan semiconductor manufacturing co., ltd., Ting-Ya LO of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ming-Han LEE of Taipei TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/532, H01L21/768
CPC Code(s): H01L23/53266
Abstract: an interconnect structure, along with methods of forming such, are described. the structure includes a dielectric layer, a conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer, wherein the conductive layer includes a first portion and a second portion adjacent the first portion. the structure also includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a dielectric material disposed between and in contact with the first and second barrier layers, wherein a bottom surface of the second barrier layer and a bottom surface of the dielectric material are substantially co-planar.
Inventor(s): Hao Chu Liao of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Wei Tse Hsu of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Chen-Yen Kao of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/544, G03F1/42, G03F7/00, G03F9/00
CPC Code(s): H01L23/544
Abstract: a semiconductor device includes a substrate having a plurality of chip regions. in some embodiments, the semiconductor device further includes a plurality of scribe lines interposing the plurality of chip regions. in some examples, the semiconductor device further includes a first plurality of alignment mark regions distributed within the plurality of scribe lines. in some embodiments, the semiconductor device further includes a second plurality of alignment mark regions distributed within each of the plurality of chip regions.
Inventor(s): Wen-Chieh LO of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Wei-Tse HSU of Zhubei City TW for taiwan semiconductor manufacturing co., ltd., Ya-Ching TSENG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yung-Shih CHENG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/3105, H01L21/56, H01L21/768, H01L23/528
CPC Code(s): H01L23/562
Abstract: a method for forming a semiconductor device is provided. the method includes forming a device layer over a device substrate and forming a front-side interconnect structure over the device layer. the method also includes forming a bevel oxide over an edge portion of the device substrate, an edge portion of the device layer, and an edge portion of the front-side interconnect structure. the method further includes forming an oxide layer over the device layer, the front-side interconnect structure, and the bevel oxide, polishing the bevel oxide and the oxide layer until a top surface of the bevel oxide is substantially level with a top surface of the oxide layer, and attaching a carrier substrate to the bevel oxide and the oxide layer.
Inventor(s): Meng-Sheng Chang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, G11C17/16, G11C17/18, H10B20/25
CPC Code(s): H01L23/573
Abstract: a memory device includes an anti-fuse memory cell that randomly presents either a first logic state or a second logic state. the memory cell is formed on a frontside of a substrate and at least includes a first programming transistor that is formed in a first one of a plurality of metallization layers disposed over the frontside and gated by a first programming word line, and a first reading transistor that is formed in a second one of the plurality of metallization layers disposed over the frontside or along a major surface on the frontside, coupled to the first programming transistor and a first bit line in series, and gated by a first reading word line.
Inventor(s): Chen-Hua Yu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuo Lung Pan of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Tin-Hao Kuo of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hao-Yi Tsai of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/64, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L23/538
CPC Code(s): H01L23/645
Abstract: a semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. the interposer includes a plurality of embedded passive components. each die of the first plurality of dies is electrically connected to the interposer. the interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.
Inventor(s): Feng-Wei Kuo of Zhudong Township TW for taiwan semiconductor manufacturing co., ltd., Wen-Shiang Liao of Toufen Township TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/66, H01L21/48, H01L23/00, H01L23/538, H01Q1/22, H01Q9/04
CPC Code(s): H01L23/66
Abstract: a package structure includes a first die, a second die over and electrically connected to the first die, an insulating material around the second die, a first antenna extending through the insulating material and electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die, wherein the first antenna includes a first conductive plate extending through the insulating material, and a plurality of first conductive pillars extending through the insulating material, wherein the first conductive plate is between the plurality of first conductive pillars and the first sidewall of the second die.
Inventor(s): Po-Yu Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Cheng Hung Wu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hui-Ling Lin of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yu Hsiang Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L23/373, H01L23/498, H01L23/522
CPC Code(s): H01L24/32
Abstract: a semiconductor structure can include a first substrate having a frontside and a backside opposite the frontside. the semiconductor structure can include devices on the frontside. the semiconductor structure can include first interconnect structures on the frontside and coupled to the devices. the semiconductor structure can include a heat distribution layer on the frontside and electrically isolated from the first interconnect structures, where the heat distribution layer includes a thermally conductive material. the semiconductor structure can include a second substrate coupled to the first substrate on the frontside. the semiconductor structure can include second interconnect structures on the backside and coupled to the devices.
Inventor(s): Chen-Hua Yu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Kuo-Chung Yee of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/48, H01L21/56, H01L23/31, H01L23/367, H01L23/538, H01L25/00
CPC Code(s): H01L25/0652
Abstract: an integrated circuit package includes a package structure, at least one conductive pillar, at least one second die and a second encapsulant. the package structure includes at least one first die, a first encapsulant encapsulating the at least one first die and a first redistribution structure over the first encapsulant. the at least one conductive pillar and the at least one second die are disposed between and electrically connected to the package structure and the second redistribution structure. the second encapsulant encapsulates the at least one conductive pillar and the at least one second die, wherein the at least one second die includes a plurality of connectors bonded to the second redistribution structure, and the second encapsulant is disposed between the connectors.
Inventor(s): Tin-Hao Kuo of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chung-Shi Liu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Hao-Yi Tsai of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yu-Chia Lai of Miaoli County TW for taiwan semiconductor manufacturing co., ltd., Po-Yuan Teng of Hsinchu city TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/31, H01L23/522, H01L23/528, H01L23/532, H01L23/538, H01L25/00, H05K1/02
CPC Code(s): H01L25/0655
Abstract: a semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. a circuit board structure includes a core layer, a first build-up layer and a second build-up layer. the first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. the circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.
Inventor(s): Yen-Liang Lin of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Tzuan-Horng Liu of Longtan Township TW for taiwan semiconductor manufacturing co., ltd., An-Jhih Su of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/48, H01L23/522, H01L25/10
CPC Code(s): H01L25/0657
Abstract: an embodiment is a method including forming a first die, the forming including forming through vias in a first substrate. the method also includes forming a first redistribution structure over the through vias and the first substrate, the first redistribution structure being electrically coupled to the through vias. the method also includes forming a first set of die connectors over and electrically coupled to the first redistribution structure, the first set of die connectors being on a first side of the first substrate. the method also includes bonding the first die to a second die. the method also includes encapsulating the first die with a first encapsulant. the method also includes forming a second set of die connectors over and electrically coupled to the first set of die connectors, the first and second sets of die connectors forming stacked die connectors.
Inventor(s): Wei-Kang Hsieh of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hung-Yi Kuo of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Hao-Yi Tsai of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Kuo-Lung Pan of Hsinchu city TW for taiwan semiconductor manufacturing co., ltd., Ting Hao Kuo of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yu-Chia Lai of Miaoli County TW for taiwan semiconductor manufacturing co., ltd., Mao-Yen Chang of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Po-Yuan Teng of Hsinchu city TW for taiwan semiconductor manufacturing co., ltd., Shu-Rong Chun of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/31, H01L23/538, H01L25/00
CPC Code(s): H01L25/0657
Abstract: a manufacturing method of a semiconductor package includes the following steps. a first lower semiconductor device and a second lower semiconductor device are provided. a plurality of first conductive pillars are formed on the first lower semiconductor device along a first direction parallel to a side of the first lower semiconductor device. a plurality of second conductive pillars are formed on the second lower semiconductor device along a second direction parallel to a side of the second lower semiconductor device, wherein the first direction is substantially collinear with the second direction. an upper semiconductor device is disposed on the first lower semiconductor device and the second lower semiconductor device and revealing a portion where the plurality of first conductive pillars and the plurality of second conductive pillars are disposed. the first lower semiconductor device, the second lower semiconductor device, the plurality of first conductive pillars, the plurality of second conductive pillars, and the upper semiconductor device are encapsulated by an encapsulating material. a redistribution structure is formed over the upper semiconductor device and the encapsulating material.
Inventor(s): Hsien-Wei Chen of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Jie Chen of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Ming-Fa Chen of Taichung City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L21/78, H01L23/00, H01L25/00
CPC Code(s): H01L25/0657
Abstract: a stacking structure including a first die, a second die stacked on the first die, and a filling material is provided. the first die has a first bonding structure, and the first bonding structure includes first bonding pads and a first heat dissipating element. the second die has a second bonding structure, and the second bonding structure includes second bonding pads and a second heat dissipating element. the first bonding pads are bonded with the second bonding pads. the first heat dissipating element is connected to one first bonding pad of the first bonding pads and the second heat dissipating element is connected to one second bonding pad of the second bonding pads. the filling material is disposed over the first die and laterally around the second die. the first and second dies are bonded through the first and second bonding structures.
20250096684. POWER MODULE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Ying-Chih Hsu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Eric Soenen of Austin TX US for taiwan semiconductor manufacturing co., ltd., Alan Roth of Leander TX US for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H02M3/158, H01L25/11, H02M3/155, H03H7/01
CPC Code(s): H02M3/158
Abstract: a power converter module includes a ground terminal, an input voltage terminal configured to receive a raw input voltage, and an interconnection terminal configured to provide a regulated output voltage to a load such as a soc or sip system to be powered. a voltage regulator is connected to the ground terminal and the input voltage terminal. an inductor has an inductor output connected to the interconnection terminal.
Inventor(s): Feng-Wei KUO of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Kai XU of Dongying CN for taiwan semiconductor manufacturing co., ltd., Robert Bogdan STASZEWSKI of Dublin IE for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03F1/56, H03F3/20, H03F3/45
CPC Code(s): H03F1/565
Abstract: systems and methods for suppressing and mitigating harmonic distortion in a circuit are disclosed. in one example, a disclosed circuit includes a radio frequency (rf) oscillator and a power amplifier. the rf oscillator is configured to generate an rf signal. the power amplifier is configured to generate an amplified rf signal based on the rf signal. the power amplifier includes a transformer including a primary winding and a secondary winding, and a feedback capacitor electrically coupled to the primary winding and the secondary winding.
Inventor(s): Huaixin XIAN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Tzu-Ying LIN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Liu HAN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jerry Chang Jui KAO of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Qingchao MENG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Xiangdong CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K3/037, G01R31/3177, G01R31/3185, H03K19/00, H03K19/0948
CPC Code(s): H03K3/037
Abstract: a scan flip-flop circuit includes first and second i/o nodes, a flip-flop circuit, a selection circuit configured to receive a scan direction signal and including input terminals coupled to the first and second i/o nodes and an output terminal coupled to an input terminal of the flip-flop circuit, and first and second drivers configured to receive the scan direction signal and a scan enable signal, each including an input terminal coupled to an output terminal of the flip-flop circuit and an output terminal coupled to a respective first or second input terminal of the selection circuit. responsive to the scan direction and scan enable signals, one of the first driver is configured to output a first signal responsive to a second signal received at the second input terminal or the second driver is configured to output a third signal responsive to a fourth signal received at the first input terminal.
Inventor(s): Cormac Michael O'Connell of Kanata CA for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H04L9/32, G11C11/412, G11C11/418, G11C11/419
CPC Code(s): H04L9/3278
Abstract: disclosed is a physical unclonable function generator circuit and method. in one embodiment, a physical unclonable function (puf) generator includes: a puf cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two pre-charge transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-charged with substantially the same voltages by the respective at least two pre-charge transistors allowing each of the plurality of bit cells having a first metastable logical state; and an authentication circuit, coupled to the puf cell array, wherein the authentication circuit is configured to access and determine second logical states of bit cells in at least one row of the puf cell array by turning on the at least one enable transistor and turning off the at least two pre-charge transistors of each of the bit cell in the at least one row of the puf cell array, and based on the determined second logical states of the bit cell in the at least one row of the puf cell array, to generate a puf signature.
Inventor(s): Ping-Wei Wang of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Feng-Ming Chang of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Jui-Lin Chen of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Yu-Bey Wu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: semiconductor structures and methods are provided. an exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (sram) cell having a write port portion and a read port portion electrically coupled to the write port portion. the read port portion includes a transistor having a first source/drain feature and a second source/drain feature. the semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source/drain feature. the semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source/drain feature.
Inventor(s): Ping-Wei Wang of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Feng-Ming Chang of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Jui-Lin Chen of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Yu-Bey Wu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: semiconductor structures and methods are provided. an exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (sram) cell having a write port portion and a read port portion electrically coupled to the write port portion. the read port portion includes a transistor having a gate structure. the semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line are positioned at a first interconnect layer disposed over the gate structure and a read word line positioned at a second interconnect layer and electrically coupled to the gate structure, the second interconnect layer is disposed under the gate structure.
20250098139. MEMORY DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Xiu-Li YANG of Shanghai City CN for taiwan semiconductor manufacturing co., ltd., He-Zhou WAN of Shanghai City CN for taiwan semiconductor manufacturing co., ltd., Yan-Bo SONG of Shanghai City CN for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00, G11C11/418
CPC Code(s): H10B10/18
Abstract: a memory device includes a first memory array, a first isolation cell abutting a first side of the first memory array, a first edge cell array abutting a second side, opposite to the first side, of the first memory array, a second memory array arranged at a first side, opposite to the first memory array, of the first isolation cell, a second edge cell array, and multiple first word lines passing through the first edge cell array, the first memory array and being terminated at the first isolation cell. a first width of the first isolation cell is different from a second width of the first edge cell array. the second memory array is sandwiched between the second edge cell array and the first isolation cell.
Inventor(s): Yong-Sheng Huang of Taipei TW for taiwan semiconductor manufacturing co., ltd., Ming Chyi Liu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chih-Pin Huang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B41/30, H01L21/28, H01L21/311, H01L21/3213, H01L21/762, H01L21/768, H01L23/522, H01L23/528, H01L29/423, H01L29/66, H01L29/788
CPC Code(s): H10B41/30
Abstract: various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. an erase gate line (egl) and the source line are formed elongated in parallel. the source line underlies the egl and is separated from the egl by a dielectric layer. a first etch is performed to form a first opening through the egl and stops on the dielectric layer. a second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. a silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. a via is formed extending through the egl to the silicide layer.
Inventor(s): Yu-Chien CHIU of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Chen-Han CHOU of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Ya-Yun CHENG of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Ya-Chun CHANG of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Wen-Ling LU of Taoyuan County TW for taiwan semiconductor manufacturing co., ltd., Yu-Kai CHANG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Pei-Chun LIAO of Ju-Bei City TW for taiwan semiconductor manufacturing co., ltd., Chung-Wei WU of Ju-Bei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10D1/696
Abstract: a memory cell structure includes a transistor structure and a capacitor structure, where the capacitor structure includes a hydrogen absorption layer. the hydrogen absorption layer absorbs hydrogen, which prevents or reduces the likelihood of the hydrogen diffusing into an underlying metal-oxide channel of the transistor structure. in this way, the hydrogen absorption layer minimizes and/or reduces the likelihood of hydrogen contamination in the metal-oxide channel, which may enable a low current leakage to be achieved for the memory cell structure and reduces the likelihood of data corruption and/or failure of the memory cell structure, among other examples.
Inventor(s): Tzu-Ging LIN of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Ya-Yi TSAI of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yun-Chen WU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shu-Yuan KU of Zhubei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/423, H01L29/775
CPC Code(s): H10D30/014
Abstract: continuous polysilicon on oxide diffusion edge (cpode) processes are described herein in which one or more semiconductor device parameters are tuned to reduce the likelihood of etching of source/drain regions on opposing sides of cpode structures formed in a semiconductor device, to reduce the likelihood of depth loading in the semiconductor device, and/or to reduce the likelihood of gate deformation in the semiconductor device, among other examples. thus, the cpode processes described herein may reduce the likelihood of epitaxial damage to the source/drain regions, may reduce current leakage between the source/drain regions, and/or may reduce the likelihood of threshold voltage shifting for transistors of the semiconductor device. the reduced likelihood of threshold voltage shifting may provide more uniform and/or faster switching speeds for the transistors, more uniform and/or lower power consumption for the transistors, and/or increased device performance for the transistors, among other examples.
Inventor(s): Ming-Ho Lin of Taipei TW for taiwan semiconductor manufacturing co., ltd., Chun-Heng Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Xiong-Fei Yu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chi On Chui of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L29/66, H01L29/78
CPC Code(s): H10D30/6219
Abstract: a method includes forming a fin protruding over a substrate; forming a conformal oxide layer over an upper surface and along sidewalls of the fin; performing an anisotropic oxide deposition or an anisotropic plasma treatment to form a non-conformal oxide layer over the upper surface and along the sidewalls of the fin; and forming a gate electrode over the fin, the conformal oxide layer and the non-conformal oxide layer being between the fin and the gate electrode.
Inventor(s): Meng-Han Chou of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yi-Syuan Siao of Changhua City TW for taiwan semiconductor manufacturing co., ltd., Su-Hao Liu of Jhongpu Township TW for taiwan semiconductor manufacturing co., ltd., Huicheng Chang of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Yee-Chia Yeo of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/40, H01L29/66, H01L29/78
CPC Code(s): H10D30/6219
Abstract: a method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. the source/drain region is exposed to the contact opening. the method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.
Inventor(s): Yao-Wen HSU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chun-Cheng CHOU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/49, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H10D30/6729
Abstract: a semiconductor device is provided, including a substrate, a transistor structure, a metal silicide layer, and a metal silicon nitride layer. the transistor structure is formed on the substrate. the transistor structure includes a source region, a drain region and a gate structure. the gate structure is located between the source region and the drain region. the metal silicide layer is formed on the top surface of the source region and the top surface of the drain region, and the metal silicon nitride layer is formed on the surface of the metal silicide layer.
Inventor(s): Ta-Chun LIN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D30/6729
Abstract: a semiconductor device includes a first channel region, a second channel region, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a contact etch stop layer, and an interlayer dielectric layer. the gate structure is across the first channel region and the second channel region. the first source/drain epitaxial structure is on a side of the first channel region. the second source/drain epitaxial structure is on a side of the second channel region. the contact etch stop layer surrounds the first source/drain epitaxial structure and the second source/drain epitaxial structure. a first portion of the contact etch stop layer over the first source/drain epitaxial structure is thicker than a second portion of the contact etch stop layer over the second source/drain epitaxial structure. the interlayer dielectric layer is over the contact etch stop layer.
Inventor(s): Yu-Xuan HUANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hou-Yu CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jin CAI of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Zhi-Chang LIN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/22, H01L29/06, H01L29/66
CPC Code(s): H10D30/6735
Abstract: a device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. the gate structure wraps around the semiconductor nanostructures. the first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. the dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.
Inventor(s): Hsin-Yi Lee of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Cheng-Lung Hung of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chi On Chui of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/28, H01L29/06, H01L29/10, H01L29/49, H01L29/78
CPC Code(s): H10D30/6735
Abstract: a device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. a portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material over the first p-type work function metal; and a second p-type work function metal over the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal.
Inventor(s): Tzu-Ging LIN of Kaohsiung TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L27/02, H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H10D62/102
Abstract: embodiments of present disclosure relates to forming isolation structures in gate structures to prevent current leakage through source/drain regions (epi), transistors, and silicon substrate. the isolation structures may be formed in the gate structure prior to or after the replacement gate sequence.
Inventor(s): Jung-Hung Chang of Changhua County TW for taiwan semiconductor manufacturing co., ltd., Shih-Cheng Chen of Zhonghe Dist. TW for taiwan semiconductor manufacturing co., ltd., Tsung-Han Chuang of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Wen-Ting Lan of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chia-Cheng Tsai of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng Chiang of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/08, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/116
Abstract: semiconductor structures and methods of forming the same are provided. in an embodiment, an exemplary semiconductor structure includes a first transistor. the first transistor includes a first gate structure wrapping around a plurality of first nanostructures disposed over a substrate, a first source/drain feature electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer, and a first semiconductor layer disposed between the substrate and the first source/drain feature, wherein the first source/drain feature is in direct contact with a top surface of the first semiconductor layer.
Inventor(s): Chung-Liang CHENG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L27/088, H01L29/423, H01L29/49, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/121
Abstract: a semiconductor process system etches gate metals on semiconductor wafers. the semiconductor process system includes a machine learning based analysis model. the analysis model dynamically selects process conditions for an atomic layer etching process. the process system then uses the selected process conditions data for the next etching process.
Inventor(s): Hou-Hsueh Wu of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Wei Hsin Lin of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Hui-Hsuan Kung of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Yi-Lii Huang of Zhubei City TW for taiwan semiconductor manufacturing co., ltd., Chih-Hsiao Chen of Taichung City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H10D64/017
Abstract: the present disclosure provides a semiconductor device and a method of forming the same. a method according to one embodiment includes forming a plurality of fins protruding from a substrate, forming first and second dummy gate stacks over the fins, and depositing a cover structure over the fins. a first portion of the cover structure extends between the first and second dummy gate stacks. the method also includes etching the fins to form a first trench between the first dummy gate stack and the first portion of the cover structure and a second trench between the second dummy gate stack and the first portion of the cover structure, removing the cover structure, epitaxially growing a first epitaxial feature from the first trench and a second epitaxial feature from the second trench. the first and second epitaxial features merge after rising above a top surface of the fins.
Inventor(s): Yung-Shih CHENG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D64/017
Abstract: an integrated circuit device includes a transistor, a dielectric layer, a first vertical connecting structure. the transistor includes a gate structure. the dielectric layer surrounds the transistor. the first vertical connecting structure extends through the dielectric layer. the gate contact via is over the gate structure. the front-side metallization pattern is over the transistor. the front-side metallization pattern includes a first conductive path and a dummy conductive pattern. the first conductive path connects the gate contact via to a top end of the first vertical connecting structure. the dummy conductive pattern is connected to the first conductive path. the back-side metallization layer is below the transistor, wherein the back-side metallization layer is connected with a bottom end of the first vertical connecting structure.
Inventor(s): Yi-Hsuan HSIAO of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Shu-Yuan KU of Zhubei City TW for taiwan semiconductor manufacturing co., ltd., Chih-Chang HUNG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., I-Wei YANG of Yilan County TW for taiwan semiconductor manufacturing co., ltd., Chih-Ming SUN of New Taipei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L21/84, H01L27/092, H01L27/12, H01L29/06, H01L29/417, H01L29/78
CPC Code(s): H10D64/017
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a substrate and a first dielectric layer over the substrate. the semiconductor device structure also includes a first metal gate stack and a second metal gate stack over the substrate and the first dielectric layer. the semiconductor device structure further includes a second dielectric layer beside the first metal gate stack and an insulating structure over the substrate. a portion of the insulating structure is between the first metal gate stack and the second metal gate stack. the insulating structure penetrates into the second dielectric layer.
Inventor(s): Ya-Wen CHIU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yi-Hua CHENG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Szu-Ying CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Zheng-Yang PAN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/762, H01L27/088
CPC Code(s): H10D64/021
Abstract: embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. the method includes forming a first fin structure and a second fin structure from a substrate, depositing a first conformal layer over the first and second fin structures and between the first and second fin structures, depositing a second conformal layer on the first conformal layer, depositing a third conformal layer on the second conformal layer, depositing a fourth conformal layer on the third conformal layer, depositing a first insulating material on the fourth conformal layer between the first and second fin structures, and depositing a second insulating material on the first insulating material. the first and second fin structures are embedded by the second insulating material. the method further includes removing portions of the second insulating material and the first, second, third, and fourth conformal layers to expose the first and second fin structures.
Inventor(s): Yi-Hong Wang of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Hui-Hsuan Kung of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Yao-Zhong Dong of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Yi-Li Huang of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Yi-Chen Li of Taichung City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L29/417, H01L29/78
CPC Code(s): H10D64/021
Abstract: semiconductor structures and methods of forming the same are provided. in an embodiment, an exemplary method includes depositing a dummy gate material layer over a first fin-shaped active region, patterning the dummy gate material layer to form a dummy gate electrode, wherein the dummy gate electrode has a footing feature at an interface between the first fin-shaped active region and the dummy gate electrode, oxidizing the footing feature and a sidewall portion of the dummy gate electrode to form a dielectric gate spacer, and replacing a remaining portion of the dummy gate electrode with a gate structure.
Inventor(s): Hsin-Che CHIANG of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Ju-Yuan TZENG of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chun-Sheng LIANG of Changhua County TW for taiwan semiconductor manufacturing co., ltd., Chih-Yang YEH of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Shu-Hui WANG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Jeng-Ya David YEH of New Taipei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/28, H01L21/768, H01L23/528, H01L23/532, H01L29/165, H01L29/49, H01L29/51, H01L29/66, H01L29/78
CPC Code(s): H10D64/517
Abstract: a method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin, the gate structure comprising: a first metallic layer; a second metallic layer over the first metallic layer, wherein the first metallic layer is a metal compound of a first element and a second element and the second metallic layer is a single-element metal of the second element; and an oxide layer between the first metallic layer and the second metallic layer.
Inventor(s): Kai-Chun CHANG of Pingtung City TW for taiwan semiconductor manufacturing co., ltd., Chi-Hsun LIN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yi Chen HO of Taichung TW for taiwan semiconductor manufacturing co., ltd., Hung Cheng LIN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H10D84/038
Abstract: methods for forming a semiconductor device structure are described. the method includes forming first and second fin structures over a substrate and forming a dielectric wall between the first and second fin structures. the forming the dielectric wall includes depositing a first dielectric layer between the first and second fin structures, and a seam is formed in the first dielectric layer. the forming the dielectric wall further includes performing an anisotropic etch process to remove a portion of the first dielectric layer to expose the seam, performing an isotropic etch process to enlarge an opening of the seam, and the seam has a “v” shaped cross-sectional profile. the forming the dielectric wall further includes depositing a second dielectric layer between the first and second fin structures, and the seam is filled. the method further includes forming shallow trench isolation regions adjacent the first and second fin structures.
Inventor(s): Minghwei HONG of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Juei-Nai KWO of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Tun-Wen PI of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Hsien-Wen WAN of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Yi-Ting CHENG of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Yu-Jie HONG of New Taipei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L21/324, H01L29/06, H01L29/10, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H10D84/038
Abstract: a method includes forming a semiconductive channel structure over a substrate. a semiconductive layer is deposited over the semiconductive channel structure. the semiconductive layer and the semiconductive channel structure includes different materials. an oxidation process is performed to the semiconductive layer to form an oxidation layer over a remaining portion of the semiconductive layer. the oxidation layer is heated after the oxidation process is performed. a gate structure is formed over the oxidation layer.
Inventor(s): Yi-Cheng Li of Yunlin TW for taiwan semiconductor manufacturing co., ltd., Pin-Ju Liang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ta-Chun Ma of New Taipei TW for taiwan semiconductor manufacturing co., ltd., Pei-Ren Jeng of Chu-Bei TW for taiwan semiconductor manufacturing co., ltd., Yee-Chia Yeo of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/306, H01L27/092
CPC Code(s): H10D84/038
Abstract: a method includes forming a fin extending from a substrate; depositing a liner over a top surface and sidewalls of the fin, where the minimum thickness of the liner is dependent on selected according to a first germanium concentration of the fin; forming a shallow trench isolation (sti) region adjacent the fin; removing a first portion of the liner on sidewalls of the fin, the first portion of the liner being above a topmost surface of the sti region; and forming a gate stack on sidewalls and a top surface of the fin, where the gate stack is in physical contact with the liner.
Inventor(s): Yu-Lien Huang of Jhubei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L21/762, H01L21/8238, H01L29/08, H01L29/66, H01L29/78
CPC Code(s): H10D84/038
Abstract: a method includes forming a gate stack on a plurality of semiconductor fins. the plurality of semiconductor fins includes a plurality of inner fins, and a first outer fin and a second outer fin on opposite sides of the plurality of inner fins. epitaxy regions are grown based on the plurality of semiconductor fins, and a first height of the epitaxy regions measured along an outer sidewall of the first outer fin is smaller than a second height of the epitaxy regions measured along an inner sidewall of the first outer fin.
Inventor(s): Jing-Yi Lin of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chih-Chuan Yang of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Shih-Hao Lin of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L27/02
CPC Code(s): H10D84/856
Abstract: various embodiments of the present disclosure are directed towards a method for forming an integrated chip. the method includes forming an epitaxial structure having a first doping type over a first portion of a semiconductor substrate. a second portion of the semiconductor substrate is formed over the epitaxial structure and the first portion of the semiconductor substrate. a first doped region having the first doping type is formed in the second portion of the semiconductor substrate and directly over the epitaxial structure. a second doped region having a second doping type opposite the first doping type is formed in the second portion of the semiconductor substrate, where the second doped region is formed on a side of the epitaxial structure. a plurality of fins of the semiconductor substrate are formed by selectively removing portions of the second portion of the semiconductor substrate.
Inventor(s): Tzu-Hao CHIANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wun-Jie LIN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jam-Wem LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/02, H01L29/06
CPC Code(s): H10D89/60
Abstract: a semiconductor device includes a substrate. the semiconductor device further includes a doped region in the substrate. the semiconductor device further includes an active area, and wherein the active area comprises an emitter region and a collector region, wherein the emitter region is electrically connected to the doped region. the semiconductor device further includes a deep trench isolation (dti) structure extending through the active area and between the emitter region and the collector region.
Inventor(s): Cheng Yu Huang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chun-Hao Chuang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Kazuaki Hashimoto of Zhubei City TW for taiwan semiconductor manufacturing co., ltd., Keng-Yu Chou of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Wei Chieh Chiang of Yuanlin Township TW for taiwan semiconductor manufacturing co., ltd., Wen-Hau Wu of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chih-Kung Chang of Zhudong Township TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146, G02B27/64, H04N25/76
CPC Code(s): H10F39/18
Abstract: various embodiments of the present application are directed towards an image sensor including a wavelength tunable narrow band filter, as well as methods for forming the image sensor. in some embodiments, the image sensor includes a substrate, a first photodetector, a second photodetector, and a filter. the first and second photodetectors neighbor in the substrate. the filter overlies the first and second photodetectors and includes a first distributed bragg reflector (dbr), a second dbr, and a first interlayer between the first and second dbrs. a thickness of the first interlayer has a first thickness value overlying the first photodetector and a second thickness value overlying the second photodetector. in some embodiments, the filter is limited to a single interlayer. in other embodiments the filter further includes a second interlayer defining columnar structures embedded in the first interlayer and having a different refractive index than the first interlayer.
Inventor(s): Wen-Chung Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chia-Yu Wei of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng Lee of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Cheng-Hao Chiu of Changhua County TW for taiwan semiconductor manufacturing co., ltd., Hsiu Chi Yu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsun-Ying Huang of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Ming-Hong Su of Tainan City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/80377
Abstract: an image sensor structure and methods of forming the same are provided. an image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. the second channel area is greater than the first channel area, the third channel area or the fourth channel area.
Inventor(s): Sheng-Chan Li of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Cheng-Hsien Chou of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Cheng-Yuan Tsai of Chu-Pei City TW for taiwan semiconductor manufacturing co., ltd., Keng-Yu Chou of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Yeur-Luen Tu of Taichung TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/8067
Abstract: the present disclosure, in some embodiments, relates to an integrated chip. the integrated chip includes a substrate having an image sensor region arranged between sidewalls of the substrate that form one or more trenches. one or more dielectric materials are arranged along the sidewalls of the substrate that form the one or more trenches. a reflective region is disposed within the one or more trenches and laterally surrounded by the one or more dielectric materials. the reflective region includes a plurality of reflective portions that are arranged at different vertical positions within the reflective region and that have different reflective properties.
Inventor(s): Tzu-Jui Wang of Fengshan City TW for taiwan semiconductor manufacturing co., ltd., Dun-Nian Yaung of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chen-Jong Wang of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Ming-Chieh Hsu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Wei-Cheng Hsu of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Yuichiro Yamashita of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146, H04N25/77
CPC Code(s): H10F39/807
Abstract: various embodiments of the present disclosure are directed towards an image sensor. the image sensor includes a deep trench isolation (dti) structure disposed in a substrate. a pixel region of the substrate is disposed within an inner perimeter of the dti structure. a photodetector is disposed in the pixel region of the substrate. a gate electrode structure overlies, at least partially, the pixel region of the substrate. a first gate dielectric structure partially overlies the pixel region of the substrate. a second gate dielectric structure partially overlies the pixel region of the substrate. the gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure. the first gate dielectric structure has a first thickness. the second gate dielectric structure has a second thickness that is greater than the first thickness.
Inventor(s): Martin Christopher HOLLAND of San Jose CA US for taiwan semiconductor manufacturing co., ltd., Timothy VASEN of Linthicum Heights MD US for taiwan semiconductor manufacturing co., ltd., Blandine DURIEZ of Bruxelles BE for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10K85/20, C23C16/26, C30B25/02, C30B29/02, H10K10/46, H10K10/84, H10K71/10
CPC Code(s): H10K85/221
Abstract: a method includes placing a first charged metal dot on a first position of a surface of a semiconductor substrate. a first charged region is formed on a second position of the surface of the semiconductor substrate. a precursor gas is flowed along a first direction from the first position toward the second position on the semiconductor substrate, thereby forming a first carbon nanotube (cnt) on the semiconductor substrate. a dielectric layer is deposited to cover the first cnt and the semiconductor substrate. a second charged metal dot is placed on a third position of a surface of the dielectric layer. a second charged region is formed on a fourth position of the surface of the dielectric layer. the precursor gas is flowed along a second direction from the third position toward the fourth position on the semiconductor substrate, thereby forming a second cnt on the first cnt.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on March 20th, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- C23C14/34
- C23C14/14
- H01J37/34
- H01L21/285
- H01L21/768
- H01L23/532
- CPC C23C14/3407
- Taiwan semiconductor manufacturing co., ltd.
- F15D1/06
- C23C16/44
- C23C16/455
- C23C16/50
- H01J37/32
- H01L21/67
- CPC F15D1/06
- G01N21/95
- G01N21/88
- CPC G01N21/9501
- G02B6/12
- G02B1/00
- G02B6/124
- G02B6/34
- G02B6/42
- CPC G02B6/12002
- CPC G02B6/4214
- G03F1/24
- CPC G03F1/24
- G03F1/22
- G03F1/38
- G03F1/46
- G03F7/20
- G03F7/004
- C08F212/14
- C08F220/38
- G03F7/038
- G03F7/039
- G03F7/16
- G03F7/36
- G03F7/38
- CPC G03F7/0045
- G03F7/09
- G03F7/105
- H01L21/027
- CPC G03F7/094
- G03F7/00
- H01L21/673
- H01L21/683
- H01L21/687
- CPC G03F7/70741
- G06F7/499
- G06F7/50
- CPC G06F7/49915
- G06F7/501
- G06F7/53
- G11C7/10
- G11C11/4074
- CPC G06F7/501
- G06F30/398
- G06F30/394
- CPC G06F30/398
- G11C7/12
- G11C5/06
- G11C16/04
- G11C16/30
- CPC G11C7/12
- G11C11/408
- G11C11/4099
- CPC G11C11/4085
- G11C11/418
- G11C11/417
- CPC G11C11/418
- G11C13/00
- CPC G11C13/004
- CPC G11C13/0069
- G11C29/46
- G11C7/24
- G11C29/12
- G11C29/50
- CPC G11C29/46
- C23C14/35
- H10N50/01
- CPC H01J37/3458
- G03F9/00
- H01L21/311
- H01L23/544
- CPC H01L21/027
- C08L25/08
- G03F7/34
- CPC H01L21/0276
- H01L21/28
- H01L21/822
- H01L27/12
- H01L29/49
- H01L29/775
- H01L29/786
- CPC H01L21/28088
- H01L21/56
- H01L23/00
- H01L23/31
- H01L23/498
- H01L23/538
- H01L25/00
- H01L25/065
- H01L25/10
- CPC H01L21/56
- CPC H01L21/67126
- B25J9/16
- B65G47/90
- H04N23/56
- CPC H01L21/68707
- H01L23/535
- H01L29/45
- H01L29/78
- CPC H01L21/7682
- H01L23/522
- H01L23/528
- H01L29/40
- H01L29/423
- CPC H01L21/76831
- H01L21/3213
- H01L21/3215
- H01L29/08
- H01L29/417
- H01L29/66
- CPC H01L21/76895
- CPC H01L21/76897
- H01L23/48
- CPC H01L21/76898
- CPC H01L23/3178
- H01L23/40
- H01L23/44
- CPC H01L23/4012
- H10B10/00
- CPC H01L23/481
- CPC H01L23/49822
- CPC H01L23/5228
- CPC H01L23/53266
- G03F1/42
- CPC H01L23/544
- H01L21/3105
- CPC H01L23/562
- G11C17/16
- G11C17/18
- H10B20/25
- CPC H01L23/573
- H01L23/64
- H01L21/48
- CPC H01L23/645
- H01L23/66
- H01Q1/22
- H01Q9/04
- CPC H01L23/66
- H01L23/373
- CPC H01L24/32
- H01L23/367
- CPC H01L25/0652
- H05K1/02
- CPC H01L25/0655
- CPC H01L25/0657
- H01L21/78
- H02M3/158
- H01L25/11
- H02M3/155
- H03H7/01
- CPC H02M3/158
- H03F1/56
- H03F3/20
- H03F3/45
- CPC H03F1/565
- H03K3/037
- G01R31/3177
- G01R31/3185
- H03K19/00
- H03K19/0948
- CPC H03K3/037
- H04L9/32
- G11C11/412
- G11C11/419
- CPC H04L9/3278
- CPC H10B10/125
- CPC H10B10/18
- H10B41/30
- H01L21/762
- H01L29/788
- CPC H10B41/30
- H10B12/00
- CPC H10D1/696
- H01L29/06
- CPC H10D30/014
- H01L21/8234
- CPC H10D30/6219
- H01L21/8238
- H01L27/092
- CPC H10D30/6729
- H01L21/22
- CPC H10D30/6735
- H01L29/10
- H01L27/02
- CPC H10D62/102
- CPC H10D62/116
- H01L27/088
- CPC H10D62/121
- CPC H10D64/017
- H01L21/84
- CPC H10D64/021
- H01L29/165
- H01L29/51
- CPC H10D64/517
- CPC H10D84/038
- H01L21/324
- H01L21/02
- H01L21/306
- CPC H10D84/856
- CPC H10D89/60
- H01L27/146
- G02B27/64
- H04N25/76
- CPC H10F39/18
- CPC H10F39/80377
- CPC H10F39/8067
- H04N25/77
- CPC H10F39/807
- H10K85/20
- C23C16/26
- C30B25/02
- C30B29/02
- H10K10/46
- H10K10/84
- H10K71/10
- CPC H10K85/221