Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on March 13th, 2025
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on March 13th, 2025
Taiwan Semiconductor Manufacturing Co., Ltd.: 79 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L29/66 (24), H01L23/00 (19), H01L29/06 (14), H01L25/065 (12), H01L29/423 (12) H10D64/017 (4), H01L25/0652 (2), H01L23/5226 (2), H01L21/76224 (2), H01L23/5383 (2)
With keywords such as: layer, structure, gate, semiconductor, forming, substrate, dielectric, source, circuit, and device in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Tai-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsiao-Lun CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shang-Chieh CHIEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01N21/31, G01N21/95
CPC Code(s): G01N21/31
Abstract: a method includes positioning a substrate in an optical path of a multiwavelength light source; generating a first detection result by exposing a first region of the substrate to a first light having a first wavelength band selected by the light source; and generating a second detection result by exposing a second region of the substrate to a second light having a second wavelength band selected by the multiwavelength light source. a system includes a multiwavelength light source including a light source and a wavelength selector in an optical path of light generated by the light source. the system further includes a spectrometer operable to measure a spectrum of a first light selected by the wavelength selector; a mask stage operable to position a mask in the optical path; and a controller operable to adjust a parameter of the multiwavelength light source responsive to the spectrum of the first light.
20250085472. OPTICAL DEVICES_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Hao Tsai of Huatan Township (TW) for taiwan semiconductor manufacturing co., ltd., Chieh-Yen Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/12, H01L23/00, H01L23/48, H01L25/16
CPC Code(s): G02B6/12004
Abstract: optical devices are presented herein. in an embodiment, the optical devices comprise a first active layer of first optical components, a first metallization layer over the first active layer, a first capacitor located within the first metallization layer, a first bond layer over the first metallization layer, and a first semiconductor device bonded to the first bond layer.
Inventor(s): Chien-Ying WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yuehying LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sui-Ying HSU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hao HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Chang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Ping LAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/13, G02B6/12, G02B6/136, G02B6/30, G02B6/34
CPC Code(s): G02B6/13
Abstract: a photonic device includes a silicon layer, wherein the silicon layer includes a waveguide portion. the photonic device further includes a cladding layer over the waveguide portion, wherein the cladding layer partially exposes a surface of the waveguide portion. the photonic device further includes a low refractive index layer in direct contact with the cladding layer, wherein the low refractive index layer comprises silicon oxide, silicon carbide, silicon oxynitride, silicon carbon oxynitride, aluminum oxide or hafnium oxide. the photonic device further includes an interconnect structure over the low refractive index layer.
Inventor(s): Chun-Lang CHEN of Tainan County (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Yang HUANG of Chiayi County (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Hao YANG of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Yun HUANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Ting CHEN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/24
CPC Code(s): G03F1/24
Abstract: euv masks and methods of fabrication thereof are described herein. an exemplary method includes receiving an euv mask having a multilayer structure, a capping layer disposed over the multilayer structure, a patterned absorber layer disposed over the capping layer, and a patterned hard mask disposed over the patterned absorber layer. the method further includes removing the patterned hard mask by performing a first etching process to partially remove the patterned hard mask and performing a second etching process to remove a remainder of the patterned hard mask. the first etching process uses a first etchant, and the second etching process uses a second etchant. the second etchant is different than the first etchant. in some embodiments, the first etchant is a halogen-based plasma (e.g., a clplasma), and the second etchant is a halogen-and-oxygen-based plasma (e.g., a cl+oplasma).
Inventor(s): Pei-Cheng HSU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Ling LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Chang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chin-Kun WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/62, H01L21/027
CPC Code(s): G03F1/62
Abstract: a pellicle comprising a pellicle membrane with improved stability to hydrogen plasma is provided. the pellicle membrane includes a network of a plurality of carbon nanotubes. at least one carbon nanotube of the plurality of carbon nanotubes is surrounded by a multilayer protective coating that includes a stress control layer and a hydrogen permeation barrier layer over the stress control layer. the stress control layer and the hydrogen permeation barrier layer independently include an me-containing nitride or an me-containing oxynitride with me selected from the group consisting of si, ti, y, hf, zr, zn, mo, cr and combinations thereof. the me-containing nitride or the me-containing oxynitride in the stress control layer has a first me concentration, and the me-containing nitride or the me-containing oxynitride in the hydrogen permeation barrier layer has a second me concentration less than the first me concentration.
Inventor(s): Yu-Chung SU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Yilang County (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Yu KUO of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/039, G03F7/09, G03F7/11, G03F7/20, G03F7/38, H01L21/027
CPC Code(s): G03F7/039
Abstract: a semiconductor device may be manufactured using a multiple-layer photoresist that is formed of one or more materials that reduce the likelihood and/or amount of residual material retained in the multiple-layer photoresist. a photoresist underlayer of the multiple-layer photoresist includes a polymer having a highly uniform distribution of polar group monomers. additionally and/or alternatively, the photoresist underlayer includes a polymer that includes a main chain and a plurality of side chains coupled with the main chain. the side chains include an acid generator component. since the acid generator component is coupled with the main chain of the polymer by the side chains as opposed to uncontrollably diffusing into the photoresist layer, the acid generated by the acid generator component upon exposure to radiation collects under the bottom of the photoresist layer in a uniform manner and enables the bottommost portions of the photoresist layer to be developed and removed.
Inventor(s): Li-Chung HSU of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Pin CHEN of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Sung-Yen YEH of Jiadong Township (TW) for taiwan semiconductor manufacturing co., ltd., Jerry Chang-Jui KAO of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Hsing WANG of Hinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/392, G06F30/367, G06F113/18, G06F119/06
CPC Code(s): G06F30/392
Abstract: systems and methods for context aware circuit design are described herein. a method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.
Inventor(s): Chen-Wei LIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Gu-Huan LI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C8/18
CPC Code(s): G11C8/18
Abstract: a memory circuit includes a memory array, and a peripheral circuit. the peripheral circuit includes an internal clock generating circuit, and a first access signal generating circuit. the internal clock generating circuit is configured to, in response to a control signal pulse, generate a series of internal clock pulses at an internal clock period corresponding to a pulse width of the control signal pulse. the first access signal generating circuit is configured to, in response to a first edge of the control signal pulse, generate a first access signal. the peripheral circuit is configured to control an access operation in the memory array, based on at least one internal clock pulse in the series of internal clock pulses, and the first access signal.
Inventor(s): Hon-Jarn LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Fu LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Chun SHIH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/4099, G11C11/4072, G11C11/4074, G11C11/408, G11C11/4094
CPC Code(s): G11C11/4099
Abstract: a memory cell includes a memory circuit and a computing-in memory (cim) circuit. the memory cell is configured to store a first value of a first signal of a first storage node. the cim circuit is coupled to the memory cell, and configured to generate an output signal in response to the first signal and a second signal. the output signal corresponding to a cim product operation of the first signal and the second signal. the cim circuit includes an output node configured to output the output signal, a first transistor coupled to the output node and the memory cell, and being configured to receive at least the second signal, and an initialization circuit coupled to the first transistor by the output node, and being configured to initialize the cim circuit in response to a third signal.
Inventor(s): Meng-Sheng CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C17/16, G11C17/18, H01L21/8238, H01L27/092, H01L29/06, H01L29/66, H01L29/78, H01L29/786, H10B20/25
CPC Code(s): G11C17/16
Abstract: a method includes forming a first gate structure across a first active region on a substrate within a memory region, wherein the first gate structure is of a first transistor being of a first conductivity type; forming a second gate structure across a second active region on the substrate within a peripheral region, wherein the second gate structure is of a second transistor being of a second conductivity type, the second conductivity type is opposite to the first conductivity type; forming a first gate contact over the first gate structure, the first gate contact overlapping with the first active region; forming a second gate contact over the second gate structure, the second gate contact non-overlapping with the second active region.
Inventor(s): Meng-Sheng Chang of Chu-bei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-En Huang of Xinfeng Township (TW) for taiwan semiconductor manufacturing co., ltd., Yih Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C17/16, H10B20/25
CPC Code(s): G11C17/165
Abstract: a memory device is disclosed. the memory device includes a plurality of memory cells, each of the memory cells including an access transistor and a resistor coupled to each other in series. the resistors of the memory cells are each formed as one of a plurality of interconnect structures disposed over a substrate. the access transistors of the memory cells are disposed opposite a first metallization layer containing the plurality of interconnect structures from the substrate.
Inventor(s): Min-Shin Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Meng-Sheng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C17/18, G11C11/4074, G11C11/408, G11C11/4094, G11C17/16
CPC Code(s): G11C17/18
Abstract: a memory circuit may comprise a memory array comprising a plurality of memory cells, an input/output (i/o) circuit, and a power management circuit. the i/o circuit can be operatively coupled to the memory array and configured to read or write each of the memory cells. the power management circuit can be operatively coupled to the memory array and the i/o circuit. the power management circuit can be configured to provide a first gate control signal and a second gate control signal based on a received first supply voltage and a received second supply voltage. the first supply voltage can be substantially higher than two times the second supply voltage.
Inventor(s): Chun-Yi CHOU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Hsien CHENG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Tse-An CHEN of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Miin-Jang CHEN of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/02, C23C16/04, H01L21/28, H01L21/762, H01L21/768, H01L21/8238, H01L23/522, H01L27/092, H01L29/06, H01L29/40, H01L29/66, H01L29/78
CPC Code(s): H01L21/0228
Abstract: a device includes gate spacers, a gate dielectric layer, and one or more gate metals. the gate spacers are over a substrate. the gate dielectric layer is between the gate spacers. the gate dielectric layer includes a horizontal portion extending parallel to a top surface of the substrate, and vertical portions extending upwards from the horizontal portion. a first one of the vertical portions has a thickness less than a thickness of the horizontal portion.
Inventor(s): Chia-Che CHUNG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Jung TSEN of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chee-Wee LIU of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/02, H01L21/47
CPC Code(s): H01L21/02697
Abstract: a method of forming a semiconductor device includes forming a semiconductor strip extending above a semiconductor substrate, forming shallow trench isolation (sti) regions on opposite sides of the semiconductor strip, recessing a portion of the semiconductor strip, etching the sti regions to form a recess in the sti regions, forming a first thermal conductive layer in the recess, forming a source/drain epitaxy structure on the first thermal conductive layer, and forming a gate stack across the semiconductor strip and extending over the sti regions.
Inventor(s): Jui-Ping Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Ming Lee of Yangmei City (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Kai Yang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Mei-Yun Wang of Chu-Pei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/285, H01L21/02, H01L21/3065, H01L21/311, H01L21/768, H01L21/8234, H01L29/06, H01L29/08, H01L29/40, H01L29/417, H01L29/423, H01L29/45, H01L29/66, H01L29/786
CPC Code(s): H01L21/28518
Abstract: a method includes forming a gate stack, growing a source/drain region on a side of the gate stack through epitaxy, depositing a contact etch stop layer (cesl) over the source/drain region, depositing an inter-layer dielectric over the cesl, etching the inter-layer dielectric and the cesl to form a contact opening, and etching the source/drain region so that the contact opening extends into the source/drain region. the method further includes depositing a metal layer extending into the contact opening. horizontal portions, vertical portions, and corner portions of the metal layer have a substantially uniform thickness. an annealing process is performed to react the metal layer with the source/drain region to form a source/drain silicide region. the contact opening is filled to form a source/drain contact plug.
Inventor(s): Yi-Nien SU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/311, H01L21/033, H01L21/768
CPC Code(s): H01L21/31144
Abstract: embodiments of the present disclosure relates to method of forming trench and via features using dielectric and metal mask layers. particularly, embodiments of present disclosure provide a hard mask stack including a first dielectric mask layer, and second dielectric mask layer and a metal mask layer, wherein the first dielectric mask layer and second dielectric mask layer have a high etch selectivity.
Inventor(s): Yunn-Shiuan Liu of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Fong Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hui Lin of Dajia Township (TW) for taiwan semiconductor manufacturing co., ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/762, H01L27/088, H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L21/76224
Abstract: a method includes forming a gate stack, and etching the gate stack to form a trench penetrating through the gate stack. a dielectric isolation region underlying the gate stack is exposed to the trench, and a first portion and a second portion of the gate stack are separated by the trench. the method includes performing a first deposition process to form a first dielectric layer extending into the trench and lining sidewalls of the first portion and the second portion of the gate stack, and performing a second deposition process to form a second dielectric layer on the first dielectric layer. the second dielectric layer fills the trench. the first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant greater than the first dielectric constant.
Inventor(s): Po-Hsien CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tai-Chun HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Ting KO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Yu FANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sung-En LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Yun PENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/762, H01L21/02
CPC Code(s): H01L21/76224
Abstract: a method for filling a gap includes: filling a dielectric layer in the gap so that a seam is formed in the dielectric layer, the dielectric layer including two surface portions at two opposite sides of the seam, respectively; introducing a surface modification agent into the seam such that each of the two surface portions has first functional groups and second functional groups; forming a stress layer on the dielectric layer to cover the seam, the stress layer including a material different from that of the dielectric layer; and applying an energy field to permit the two surface portions to bond with each other through reaction between the first functional groups and the second functional groups.
Inventor(s): Kuang-Wei YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chin LEE of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shao-Kuan LEE of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Jing Ting SU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Ning HUNG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Yen HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsiao-Kang CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/528
CPC Code(s): H01L21/76834
Abstract: a method includes forming a metal layer over a dielectric layer; forming hard masks over the metal layer; etching the metal layer using the hard masks as etch mask to form metal features; selectively forming dielectric liners on opposite sidewalls of each of the metal features, while leaving surfaces of the hard masks and the dielectric layer exposed by the dielectric liners; and forming an inter-metal dielectric layer laterally surrounding the metal features.
Inventor(s): Ming-Hsing Tsai of Chu-Pei (TW) for taiwan semiconductor manufacturing co., ltd., Ya-Lien Lee of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Han Tseng of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Kuei-Wen Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Hung Ho of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Uei Hung of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Cheng Kuo of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Yi-An Lai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Ting Chen of Taichung (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/8234, H01L23/522, H01L29/66, H01L29/78
CPC Code(s): H01L21/76843
Abstract: a method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.
Inventor(s): Wen-Hao CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsuan-Chih CHU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Ming DAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/66, C23C14/35, C23C14/54, H01J37/32, H01J37/34
CPC Code(s): H01L22/26
Abstract: a deposition system provides a feature that may reduce costs of the sputtering process by increasing a target change interval. the deposition system provides an array of magnet members which generate a magnetic field and redirect the magnetic field based on target thickness measurement data. to adjust or redirect the magnetic field, at least one of the magnet members in the array tilts to focus on an area of the target where more target material remains than other areas. as a result, more ion, e.g., argon ion bombardment occurs on the area, creating more uniform erosion on the target surface.
Inventor(s): Wei-Chih Lai of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Chia Chiu of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Der-Chyang Yeh of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Hsien Hsieh of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Han Hsu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Shu Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Cheng Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Chen Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L21/52, H01L21/56, H01L23/31, H01L23/498, H01L23/538, H01L25/00, H01L25/065
CPC Code(s): H01L23/3675
Abstract: a semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. the die is disposed on the circuit substrate and electrically connected with the circuit substrate. the die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. the frame structure is disposed on the circuit substrate and surrounding the die. the heat sink lid is disposed on the die and the frame structure. the head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.
Inventor(s): Jhon-Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L21/8238, H01L23/48, H01L27/092, H01L27/12, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H01L23/3677
Abstract: an ic structure includes a plurality of first channel regions and a plurality of second channel regions over a substrate, a plurality of first gate structures traversing the plurality of first channel regions, and a plurality of second gate structures traversing the plurality of second channel regions. the first gate structures have a first gate pitch. the second gate structures have a second gate pitch different than the first gate pitch. the ic structure further includes first gate contact over a first one of the second gate structures. the first gate contact overlaps a location where the first one of the second gate structures traverses across a first one of the second channel regions. the first gate contact further overlaps a location where the first one of the second gate structures traverses across a second one of the second channel regions.
Inventor(s): Yang-Che CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huang-Wen TSENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Victor Chiang LIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chwen-Ming LIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/373, H01L23/00, H01L23/367
CPC Code(s): H01L23/3736
Abstract: a method includes forming a solder layer on a surface of one or more chips. a lid is positioned over the solder layer on each of the one or more chips. heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. the solder layer has a thermal conductivity of ≥50 w/mk.
Inventor(s): Kuo-Chiang Ting of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ta Hao Sung of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ken-Yu Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/42, H01L23/00, H01L23/29, H01L23/36, H01L23/48, H01L25/065
CPC Code(s): H01L23/42
Abstract: in an embodiment, a device includes: a lower integrated circuit die; an upper integrated circuit die bonded to the lower integrated circuit die with a dielectric-to-dielectric bonding region and with a metal-to-metal bonding region; a first buffer layer around the upper integrated circuit die, the first buffer layer including a buffer material having a first thermal conductivity, the buffer material having a columnar crystalline structure, the columnar crystalline structure including crystalline columns having a substantially uniform orientation in a direction that extends away from the lower integrated circuit die; and a gap-fill dielectric over the first buffer layer and around the upper integrated circuit die, the gap-fill dielectric having a second thermal conductivity, the first thermal conductivity greater than the second thermal conductivity.
Inventor(s): Sung-Yueh Wu of Chiayi County (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Ling Hwang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jen-Chun Liao of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Hsuan Lee of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hung Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H01L23/31
CPC Code(s): H01L23/49827
Abstract: a package structure includes a carrier substrate and a die. the carrier substrate includes through carrier vias (tcv). the die is disposed over the carrier substrate. the die includes a semiconductor substrate and conductive posts disposed over the semiconductor substrate. the semiconductor substrate is located between the conductive posts and the carrier substrate.
Inventor(s): Chun-Yuan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Tsung Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Chieh Su of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Meng-Huan Jao of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L29/417
CPC Code(s): H01L23/5226
Abstract: a semiconductor device and a method of manufacturing thereof are provided. the method comprises: forming a gate electrode over a substrate; forming source/drain regions beside the gate electrode; forming contact plugs on the source/drain regions; forming a dielectric layer over the contact plugs and the gate electrode; forming first openings and a second opening in the dielectric layer to expose portions of the contact plugs and a portion of the gate electrode respectively; performing a pre-clean process such as applying an ozone-containing source to the exposed portions of the contact plugs and the gate electrode; performing a surface treatment to the first and second openings to passivate sidewalls of the first and second openings; forming a conductive layer to fill the first openings and the second opening in a same deposition process by using a same metal precursor; and performing a planarization process.
Inventor(s): Yi-Lin CHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Fang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jia-Jye SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, G06F30/392, G06F30/394, G06F30/3947, G06F30/398, G06F119/12, H01L23/528
CPC Code(s): H01L23/5226
Abstract: a method of forming a three dimensional integrated circuit (3dic) structure includes forming a first inter-layer via which connects at a location of a first device layer, wherein the first inter-layer via has a footprint that is at least one factor of ten smaller than a footprint of a first circuit region. the method further includes forming a first conductive segment in a second device layer, different from the first device layer, wherein the first conductive segment electrically connects to the first inter-layer via.
20250087582. EFUSE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Meng-Sheng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yao-Jen YANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/525, H10B20/25
CPC Code(s): H01L23/5252
Abstract: a metal fuse structure may be provided. the metal fuse structure may comprise a first fuse element and a second fuse element. the second fuse element may be adjacent to the first fuse element for a length l. the second fuse element may be spaced apart from first fuse element by a width w.
Inventor(s): Monsen Liu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shuo-Mao Chen of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L23/28, H01L25/00, H01L25/065, H10B80/00
CPC Code(s): H01L23/5383
Abstract: a method includes forming first conductive elements on and extending through a first composite layer; forming a first polymer layer on the first composite layer; forming a first metallization pattern extending through the first polymer layer; forming a second polymer layer over the first polymer layer, wherein the second polymer layer is thinner than the first polymer layer; forming a second metallization pattern on and extending through the second polymer layer, wherein the second metallization pattern is thinner than the first metallization pattern; forming a second composite layer on the first composite layer; and forming second conductive elements extending through the second composite layer.
Inventor(s): Chou-Kun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Harsha Vardhan PENUGONDA of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Monsen LIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., King-Ho TAM of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L23/498
CPC Code(s): H01L23/5383
Abstract: an interconnection structure (for a multi-chip interposer) includes: a first via stack at a first one amongst locations, the locations correspondingly being defined relative to first and second perpendicular directions, the via stack including vias stacked over each other in a third direction perpendicular to each of the first and second directions; a transition segment in a transition layer and overlapping and coupled to an uppermost one of the vias in the via stack at the first location, the transition segment being conductive and extending in at least the first direction or the second direction to overlap a second one of locations offset from the first location; and a first contact bump at the second location and over and coupled to the via stack.
Inventor(s): Geng-Ming CHANG of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Kewei ZUO of Xinbei City (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Cheng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hang TUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chih CHIOU of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Yao CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua YU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/544, H01L23/00, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L23/544
Abstract: a package structure includes a first bonding film on a first package component and a first alignment mark in the first bonding film. the first alignment mark includes a plurality of first patterns spaced apart from each other. the package structure includes a second bonding film on a second package component and bonded to the first bonding film, and a second alignment mark in the second bonding film. the second alignment mark includes a plurality of second patterns spaced apart from each other, and the first patterns overlap the second patterns. in this case, an interference pattern can be formed by the optical signal passing through the varying spacing between the gratings of top wafer and bottom wafer due to pitch difference between first pitch and second pitch. by reading the optical signal, the resolution of overlay (misalignment) measurement is improved.
Inventor(s): Po-Yao Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Meng-Wei Chou of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/552, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/498
CPC Code(s): H01L23/552
Abstract: semiconductor devices and method of manufacture are provided. in embodiments a conductive connector is utilized to provide an electrical connection between a substrate and an overlying shield. the conductive connector is placed on the substrate and encapsulated with an encapsulant. once encapsulated, an opening is formed through the encapsulant to expose a portion of the conductive connector. the shield is deposited through the encapsulant to make an electrical connection to the conductive connector.
Inventor(s): Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei Ling Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chieh-Yen Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/768, H01L23/532
CPC Code(s): H01L24/08
Abstract: in an embodiment, a method includes forming a device layer over a first substrate; forming a first interconnect structure over a front-side of the device layer; attaching a second substrate to the first interconnect structure; forming a second interconnect structure over a back-side of the device layer, the second interconnect structure comprising back-side memory elements, wherein the back-side memory elements and a first plurality of active devices of the device layer provide a first memory array; and forming conductive connectors over the second interconnect structure.
Inventor(s): Ching Ju Yang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yao-Wen Chang of Taipei (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/498, H01L25/00, H01L25/065
CPC Code(s): H01L24/09
Abstract: various embodiments of the present disclosure are directed towards an integrated chip having an interconnect structure overlying a substrate. the interconnect structure includes a conductive wire disposed in a dielectric structure. the conductive wire comprises a body structure. a passivation structure overlies the interconnect structure. a bond pad overlies the passivation structure. the bond pad comprises an upper pad structure on the passivation structure and a plurality of lower bond structures extending through the passivation structure to the conductive wire. the lower bond structures respectively comprise a vertical bond structure and a diffusion barrier layer disposed along a lower surface and opposing sidewalls of the vertical bond structure. the upper pad structure comprises a first conductive layer vertically stacked with a second conductive layer
Inventor(s): Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Shi Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Tin-Hao Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L23/31, H01L23/40, H01L23/498
CPC Code(s): H01L24/20
Abstract: a package structure includes at least one semiconductor die, a plurality of hollow cylinders, an insulating encapsulant, a redistribution layer and through holes. the plurality of hollow cylinders is surrounding the at least one semiconductor die. the insulating encapsulant has a top surface and a bottom surface opposite to the top surface, wherein the insulating encapsulant encapsulates the at least one semiconductor die and the plurality of hollow cylinders. the redistribution layer is disposed on the top surface of the insulant encapsulant and over the at least one semiconductor die. the through holes are penetrating through the plurality of hollow cylinders.
Inventor(s): Yu-Young WANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Min LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Min-Yu WU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Jen WU of Chu-Dong Town (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, B23K1/00, B23K1/012, B23K3/04, B23K3/08
CPC Code(s): H01L24/75
Abstract: a zone heater assembly of a reflow solder tool includes a gas deflector having a single-layer structure. the single-layer structure may include one or more gas-permeating patterns through which a process gas is to flow from one or more gas outlets to a gas exhaust of the zone heater assembly. the one or more gas-permeating patterns in the single-layer structure promote uniformity of gas flow through the gas exhaust and into a heating zone of the reflow solder tool. the uniformity of the gas flow of the process gas enables convection heat provided by the process gas to be uniformly distributed across the heating zone. in this way, the gas deflector described herein may decrease hot spots and/or cold spots in the heating zone, which enables greater flexibility in placement of semiconductor package substrates on a conveyor device of the reflow solder tool.
Inventor(s): Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Jung Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Wei Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Tzu Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/538, H01L25/065, H01L27/06
CPC Code(s): H01L24/82
Abstract: a method of forming a semiconductor package includes the following operations. a first integrated circuit structure is provided, and the first integrated circuit structure includes a first substrate and a silicon layer over the first substrate. a plasma treatment is performed to transform a top portion of the silicon layer to a first bonding layer on the remaining silicon layer of the first integrated circuit structure. a second integrated circuit structure is provided, and the second integrated circuit structure includes a second substrate and a second bonding layer over the second substrate. the second integrated circuit structure is bonded to the first integrated circuit structure through the second bonding layer of the second integrated circuit structure and the first bonding layer of the first integrated circuit structure.
Inventor(s): Chih-Chao Chou of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Wei Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsun Chiu of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/768, H01L23/00, H01L23/48, H01L23/528
CPC Code(s): H01L25/0652
Abstract: a semiconductor package includes a first semiconductor die and a second semiconductor die bonded over the first semiconductor die. the second semiconductor die includes a first backside interconnect structure having a first power rail structure. an integrated voltage regulator die is bonded over the second semiconductor die such that the integrated voltage regulator die is electrically connected to the first power rail structure. a through via is on the first semiconductor die and is electrically coupled to the first semiconductor die. the through via is disposed outside of and adjacent to the second semiconductor die. the through via also electrically couples the first semiconductor die to the second semiconductor die through the integrated voltage regulator die.
Inventor(s): Yu-Chia Lai of Zhunan Township (TW) for taiwan semiconductor manufacturing co., ltd., Ting Hao Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Shien Chen of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Sheng Li of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/498, H01L23/522, H01L25/00
CPC Code(s): H01L25/0652
Abstract: a device includes a package component including an interconnect structure on a first side of a substrate; metal pads on the interconnect structure; a semiconductor die connected to a second side of the substrate; a dielectric material surrounding the package component; a passivation layer extending over the package component and over the dielectric material; a first buffer layer over the passivation layer, wherein the first buffer layer extends over the package component and over the dielectric material, wherein a width of the first buffer layer is greater than a width of the package component and is less than a width of the passivation layer; and conductive connectors penetrating the passivation layer and the first buffer layer to physically contact the metal pads.
20250087638. PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Chin-Hua WANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Shen YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Sheng LIN of Zhubei (TW) for taiwan semiconductor manufacturing co., ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/48, H01L23/00
CPC Code(s): H01L25/0655
Abstract: a package structure is provided. the package structure includes a first package component mounted on a substrate, a lid structure disposed on the substrate and around the first package component, and a thermal interface material vertically sandwiched between the plurality of integrated circuit dies of the first package component and the lid structure. the first package component includes a plurality of integrated circuit dies and an underfill formed between the integrated circuit dies. the lid structure covers the integrated circuit dies and exposes the underfill. a first portion and a second portion of the thermal interface material are laterally separated from each other, and a space between the first portion and the second portion is exposed from the lid structure.
Inventor(s): Ke-Gang Wen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Bey Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Chieh Hsiao of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Liang-Wei Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/768, H01L23/00, H01L23/48
CPC Code(s): H01L25/0657
Abstract: a method includes forming first integrated circuits on a front side of a semiconductor substrate of a first device die, forming a trench capacitor extending from a backside of the semiconductor substrate into the semiconductor substrate, and forming a first through-via and a second through-via penetrating through the semiconductor substrate. the trench capacitor is electrically coupled between the first through-via and the second through-via. a second device die is bonded to the first die. the second device die includes second integrated circuits, and power nodes of the second integrated circuits are electrically coupled to the first through-via and the second through-via.
Inventor(s): Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L23/00, H01L23/538
CPC Code(s): H01L25/0657
Abstract: a structure includes core substrates attached to a first side of a redistribution structure, wherein the redistribution structure includes first conductive features and first dielectric layers, wherein each core substrate includes conductive pillars, wherein the conductive pillars of the core substrates physically and electrically contact first conductive features; an encapsulant extending over the first side of the redistribution structure, wherein the encapsulant extends along sidewalls of each core substrate; and an integrated device package connected to a second side of the redistribution structure.
Inventor(s): Jing-Cheng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Hao TSAI of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/11, H01L21/02, H01L21/48, H01L21/56, H01L21/66, H01L21/683, H01L21/768, H01L23/00, H01L23/31, H01L23/427, H01L23/498, H01L23/538, H01L25/00, H01L25/065, H01L25/10
CPC Code(s): H01L25/117
Abstract: a package structure includes a first semiconductor package and a second semiconductor package over the first semiconductor package. the first semiconductor package includes a dielectric structure, a semiconductor device on the dielectric structure, under bump metallization (ubm) structures in the dielectric structure. the usb structures each include a first region and a second region surrounded by the first region. the first region has more metal layers than the second region. the bumps are respectively on the second regions of the ubm structures.
Inventor(s): Wei-Yu Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Shiuan Wong of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Shen Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsuan-Ting Kuo of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Jan Pei of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsiu-Jen Lin of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Mao-Yen Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/18, H01L21/56, H01L23/00, H01L23/31, H01L23/538, H01L25/00
CPC Code(s): H01L25/18
Abstract: a semiconductor package includes an interposer that has a first side and a second side opposing the first side. a semiconductor device that is on the first side of the interposer and an optical device that is on the first side of the interposer and next to the semiconductor device. a first encapsulant layer includes a first portion and a second portion. the first portion of the first encapsulant layer is on the first side of the interposer and along sidewalls of the semiconductor device. a gap is between a first sidewall of the optical device and a second sidewall of the first portion of the first encapsulant layer. a substrate is over the second side of the interposer. the semiconductor device and the optical device are electrically coupled to the substrate through the interposer.
Inventor(s): Shih-Yu Liao of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Liang Cheng of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00, H01L23/522, H01L23/528, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10B10/125
Abstract: various embodiments of the present disclosure are directed to a vertical gate-all-around (gaa) memory cell. a middle conductor overlies a lower conductor and decreases in width towards the lower conductor to culminate in a point spaced from the lower conductor. an insulator structure is between the lower conductor and the middle conductor. a semiconductor channel overlies the middle conductor, and a gate electrode laterally surrounds the semiconductor channel on a sidewall of the semiconductor channel. a gate dielectric layer separates the gate electrode from the semiconductor channel, and an upper conductor overlies the semiconductor channel. the lower and middle conductors and the insulator structure correspond to a resistor, whereas the middle conductor, the upper conductor, the gate electrode, the gate dielectric layer, and the semiconductor channel correspond to a transistor atop the resistor.
Inventor(s): Meng-Han LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-En HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B51/20, H10B51/10, H10B51/30
CPC Code(s): H10B51/20
Abstract: a semiconductor memory device includes pairs of metal lines and memory arrays. each of the memory arrays includes first and second sets of thin film transistors (tfts), a first switch transistor, and a second switch transistor. the tfts in the first and second sets are electrically connected to each other in parallel. the first switch transistor is electrically connected in series to one of the tfts in the first set and one of the metal lines in a corresponding one of the pairs of the metal lines. the second switch transistor is electrically connected in series to one of the tfts in the second set and the other one of the metal lines in the corresponding one of the pairs of the metal lines.
Inventor(s): Sheng-Chen Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Cheng Yang of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Han-Jong Chia of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B51/20, H10B51/10, H10B51/30
CPC Code(s): H10B51/20
Abstract: a 3d memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. the 3d memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. the conductive strips may be laterally indented from the dielectric strips to form recesses. a data storage film may be disposed within these recesses. any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3d memory array. the data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. the data storage film may also be made discontinuous between horizontally adjacent memory cells.
Inventor(s): Ya-Ling LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., I-Cheng CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Chieh HUANG of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., I-Chee LEE of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B51/30, H01L21/28, H01L29/08, H01L29/51, H01L29/66, H01L29/78
CPC Code(s): H10B51/30
Abstract: a ferroelectric random access memory (feram) cell may include an oxide insertion layer between the electron barrier layer and the metal glue layer of the source/drain regions of the feram cell. the oxide insertion layer may improve the thermal stability of the electron barrier layer and minimize or prevent dissociation and/or out-diffusion of the electron barrier layer at high processing temperatures. thus, the oxide insertion layer may enable the metal glue layer to be formed over the electron barrier layer with low surface roughness, which may enable increased adhesion between the metal glue layer and the source/drain electrodes of the source/drain regions. in this way, the oxide insertion layer may enable low electrical resistance to be achieved for the feram cell and/or may reduce the likelihood of failures in the feram cell, among other examples.
Inventor(s): Ming-Che Lee of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chau Chen of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Yuan Tsai of Hsin-Chu county (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01G4/30, H01L21/768, H01L23/522
CPC Code(s): H10D1/042
Abstract: provided are an integrated circuit (ic) and a method of forming the same. the ic includes a substrate; a conductive layer, disposed on the substrate; a barrier layer, disposed on the conductive layer; an etching stop layer, covering a sidewall of the barrier layer and extending on a first portion of a top surface of the barrier layer; and at least one capacitor structure, disposed on a second portion of the top surface of the barrier layer.
Inventor(s): Hui-Hung Shen of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ke-Jing Yu of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Chen Chang of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Anhao Cheng of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Liang Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Ru-Shang Hsiao of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/94, H01L27/06, H01L29/66
CPC Code(s): H10D1/66
Abstract: a semiconductor device and method of manufacturing the same are provided. the semiconductor device includes a substrate and a capacitor structure. the capacitor structure is disposed on the substrate. the capacitor structure includes a first electrode and a plurality of second electrodes. at least one of the plurality of second electrodes is embedded within the first electrode.
Inventor(s): Chia-Yueh Chou of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Hsiang-Ku Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Chiu Huang of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Hao Hou of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kun-Yu Lee of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Ho Lin of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Alvin Universe Tang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Hsiu Chiang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01G15/00, H01L21/02, H01L21/285, H01L21/3213
CPC Code(s): H10D1/68
Abstract: semiconductor structures and methods are provided. an exemplary method includes depositing forming a first metal-insulator-metal (mim) capacitor over a substrate and forming a second mim capacitor over the first mim capacitor. the forming of the first mim capacitor includes forming a first conductor plate over a substrate, the first conductor plate comprising a first metal element, conformally depositing a first dielectric layer on the first conductor plate, the first dielectric layer comprising the first metal element, forming a first high-k dielectric layer on the first dielectric layer, conformally depositing a second dielectric layer on the first high-k dielectric layer, the second dielectric layer comprising a second metal element, and forming a second conductor plate over the second dielectric layer, the second conductor plate comprises the second metal element.
Inventor(s): Ta-Chun Ma of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L29/10, H01L29/78
CPC Code(s): H10D30/024
Abstract: a fin field effect transistor device structure includes a fin structure formed over a substrate. the structure also includes a liner layer and an isolation structure surrounding the fin structure. the structure also includes a gate dielectric layer formed over the fin structure and the isolation structure. the structure also includes a gate structure formed over the gate dielectric layer. the structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. the fin structure includes a protruding portion laterally extending over the liner layer.
Inventor(s): Yan-Ting Lin of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ru Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Chang Su of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Yun Chin of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Wei Lee of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Pang-Yen Tsai of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Chii-Horng Li of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/786, H01L21/02, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H10D30/6713
Abstract: a nano-fet and a method of forming is provided. in some embodiments, a nano-fet includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. the epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. a second semiconductor material layer is formed over the first segment and the second segment. the second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. the second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.
Inventor(s): Mauricio MANFRINI of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Han-Jong Chia of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/28, H01L29/66
CPC Code(s): H10D30/701
Abstract: a semiconductor device includes a transistor and a ferroelectric tunnel junction. the ferroelectric tunnel junction is connected to a drain contact of the transistor. the ferroelectric tunnel junction includes a first electrode, a second electrode, a crystalline oxide layer, and a ferroelectric layer. the second electrode is disposed over the first electrode. the crystalline oxide layer and the ferroelectric layer are disposed in direct contact with each other in between the first electrode and the second electrode. the crystalline oxide layer comprises a crystalline oxide material. the ferroelectric layer comprises a ferroelectric material.
Inventor(s): Tzu-Ging LIN of Kaohsiung (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H10D62/115
Abstract: a semiconductor device structure, along with methods of forming such, are described. the semiconductor device structure includes a substrate, a source/drain feature disposed over the substrate, a gate spacer disposed over the source/drain feature, and a first isolation trench structure disposed over the substrate. the first isolation trench includes an upper portion adjacent to the gate spacer, a middle portion disposed below the upper portion and adjacent to a first side of the source/drain feature, and a lower portion disposed below the middle portion and extending into the substrate, wherein the lower portion has a bowing profile extending outwardly from one side of the first isolation trench structure.
Inventor(s): Hung-Chih Tsai of Daliao Township (TW) for taiwan semiconductor manufacturing co., ltd., Liang-Yu Su of Yunlin County (TW) for taiwan semiconductor manufacturing co., ltd., Ruey-Hsin Liu of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Hsueh-Liang Chou of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Ta Lei of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L29/40, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H10D62/116
Abstract: in some embodiments, the present disclosure relates to an integrated device, including a substrate comprising a channel region; a gate structure disposed on the substrate over the channel region; a first doped region of a first doping type on a first side of the gate structure; a second doped region of the first doping type on a second side of the gate structure; a shallow trench isolation (sti) structure disposed on an opposite side of the first doped region from the gate structure and having a bottom surface at a first depth beneath a top surface of the substrate; a shallow-shallow trench isolation (ssti) structure extending from the second doped region to the gate structure, the ssti structure having a bottom surface at a second depth beneath the top surface of the substrate, where the second depth is less than the first depth.
Inventor(s): Chen-Fong Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Han-De Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/02, H01L21/8238, H01L27/092, H01L29/04, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/121
Abstract: a method includes: epitaxially growing a first multi-layer stack over a first substrate; epitaxially growing a second multi-layer stack over a second substrate; and bonding the first multi-layer stack to the second multi-layer stack. the first substrate and the second substrate have different crystalline orientations. the method further includes patterning the first multi-layer stack and the second multi-layer stack to form a fin, the fin comprising a plurality of lower nanostructures alternatingly stacked with first dummy nanostructures and a plurality of upper nanostructures alternatingly stacked with second dummy nanostructure; replacing the first dummy nanostructures with a first gate stack, the first gate stack surrounding each of the plurality of lower nanostructures; and replacing the second dummy nanostructures with a second gate stack, the second gate stack surrounding each of the plurality of upper nanostructures.
Inventor(s): Jhon-Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/08, H01L21/8234, H01L27/088, H01L29/417, H10B10/00
CPC Code(s): H10D62/159
Abstract: an integrated circuit (ic) structure includes first and second semiconductor channel patterns extending over a substrate. from a plan view, the second semiconductor channel pattern has a longitudinal axis aligned with a longitudinal axis of the first semiconductor channel pattern, the first semiconductor channel pattern has a first longitudinal side and a second longitudinal side separated from the first longitudinal side by a first distance, and the second channel pattern has a third longitudinal side and a fourth longitudinal side separated from the third longitudinal side by a second distance less than the first distance.
Inventor(s): Yao-Wen Hsu of New Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Yun-Ting Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Cheng Chou of Taichung (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/40, H01L21/02, H01L21/8238, H01L27/092, H01L29/417, H01L29/45
CPC Code(s): H10D64/01
Abstract: a method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising a plurality of sacrificial layers that alternate with a plurality of channel layers, forming a dummy gate stack over a top surface and sidewalls of the multi-layer stack, forming first spacers on sidewalls of the dummy gate stack, growing an epitaxial source/drain region that extends through the plurality of sacrificial layers and the plurality of channel layers, forming a metal-semiconductor alloy region on first portions of the epitaxial source/drain region, forming a coating layer on the metal-semiconductor alloy region, wherein during the forming of the metal-semiconductor alloy region and the coating layer, a residual layer is formed on sidewalls of the first spacers, and performing a wet clean process to selectively etch the residual layer from the sidewalls of the first spacers.
Inventor(s): Kuei-Yu Kao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chiung-Yu Cho of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Ching Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L29/40, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D64/017
Abstract: semiconductor devices and methods for forming the semiconductor devices using a cap layer are provided. the semiconductor devices include a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers, and a gate spacer that extends along a sidewall of the upper portion of the gate structure. in some examples, a gap dimension measured between the gate spacer and an adjacent one of the plurality of semiconductor layers is sufficiently small such that the gate structure does not contact the source/drain structures. in some examples, the gate spacer and an adjacent one of the one or more semiconductor layers of the fin structure are separated by a cap layer.
Inventor(s): Cheng-Yu Wei of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-I Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Ming Tang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Han Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D64/017
Abstract: a method includes forming a protruding fin, and forming a first dielectric layer including a first dielectric layer and a second dielectric layer over the first dielectric layer. the first dielectric layer includes a first top portion on a top surface of the protruding fin, and a sidewall portion on a sidewall of the protruding fin. the second dielectric layer is over the first top portion and the top surface of the protruding fin, and is formed using an anisotropic deposition process. the method further includes forming a dummy gate electrode on the second dielectric layer, forming a gate spacer on a sidewall of the dummy gate electrode, removing the dummy gate electrode, and forming a replacement gate electrode in a space left by the dummy gate electrode.
Inventor(s): Tze-Chung LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Han-Yu LIN of Nantou County (TW) for taiwan semiconductor manufacturing co., ltd., Li-Te LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Pinyen LIN of Rochester NY (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/423, H01L29/78
CPC Code(s): H10D64/017
Abstract: a method for forming a semiconductor device structure is provided. the method includes forming a stack structure over a substrate, and the stack structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked. the method includes forming a dummy gate electrode over the first semiconductor layers and the second semiconductor layers, and forming a gate spacer layer adjacent to the dummy gate electrode. the method includes removing the second semiconductor layers to form a recess between two adjacent first semiconductor layers, and forming a dummy dielectric layer in the recess after the dummy gate electrode is formed. the dummy dielectric layer is between two adjacent first semiconductor layers. the method includes replacing the dummy gate electrode and the dummy dielectric layer with a gate structure.
Inventor(s): Zhi-Qiang WU of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-An LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chan-Lon YANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Bharath Kumar PULICHERLA of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Te LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Cheng WU of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Gwan-Sin CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Pinyen LIN of Rochester NY (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/311, H01L21/3213, H01L29/40, H01L29/49, H01L29/78
CPC Code(s): H10D64/017
Abstract: a semiconductor device includes a substrate having a semiconductor fin. a gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. a work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. a gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. an epitaxy structure is over the semiconductor fin.
Inventor(s): Hung-Ju Chou of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Ching Wang of Kinmen County (TW) for taiwan semiconductor manufacturing co., ltd., Yuan-Ching Peng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D64/018
Abstract: the present disclosure provides a semiconductor device and a method of forming the same. a method according one embodiment of the present disclosure include forming an epitaxial stack of channel layers and sacrificial layers on a semiconductor substrate, patterning the epitaxial stack to form a first fin-shape structure in a first region and a second fin-shape structure in a second region, etching the first fin-shape structure to form a first source/drain recess, etching the second fin-shape structure to form a second source/drain recess, forming first inner spacers in the first region, forming second inner spacers in the second region, laterally recessing the second inner spacers, forming a first source/drain feature in the first source/drain recess, and forming a second source/drain feature in the second source/drain recess. after the laterally recessing of the second inner spacers, the second inner spacers have a thickness less than the first inner spacers.
Inventor(s): Viraj Nilesh MADHIWALA of Kessel-Lo (BE) for taiwan semiconductor manufacturing co., ltd., Georgios VELLIANITIS of Heverlee (BE) for taiwan semiconductor manufacturing co., ltd., Marcus Johannes Henricus VAN DAL of Linden (BE) for taiwan semiconductor manufacturing co., ltd., Oreste MADIA of Bruxelles (BE) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D64/258
Abstract: a semiconductor device includes a substrate. semiconductor channel layers are over the substrate. a gate structure wraps around each of the semiconductor channel layers. source/drain epitaxial structures are on opposite sides of the gate structure. an inner spacer is vertically between adjacent two of the semiconductor channel layers. a dielectric protective layer is on a sidewall of the inner spacer.
Inventor(s): Jet-Rung Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Fang Pai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/45, H01L21/285, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H10D64/62
Abstract: a semiconductor device and the method of forming the same are provided. the semiconductor device may comprise a first plurality of nanostructures, a second plurality of nanostructures over a substrate, a first gate stack extending between the nanostructures of the first plurality of nanostructures, a second gate stack extending between the nanostructures of the second plurality of nanostructures, a first source/drain region in contact with a first nanostructure of the first plurality of nanostructures, a second source/drain region in contact with a first nanostructure of the second plurality of nanostructures, wherein the second source/drain region may be separated from the first source/drain region, a silicide layer between the first source/drain region and the second source/drain region, and an isolation layer between the silicide layer and the substrate.
Inventor(s): Shahaji B. MORE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Hsien YEH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Yu MA of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L27/088
CPC Code(s): H10D84/038
Abstract: embodiments of the present disclosure provide methods for forming merged source/drain features from two or more fin structures. the merged source/drain features according to the present disclosure have a merged portion with an increased height percentage over the overall height of the source/drain feature. the increase height percentage provides an increased landing range for source/drain contact features, therefore, reducing the connection resistance between the source/drain feature and the source/drain contact features. in some embodiments, the emerged source/drain features include one or more voids formed within the merged portion.
Inventor(s): Chia-Chung CHEN of Keelung (TW) for taiwan semiconductor manufacturing co., ltd., Szu-Lin LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jaw-Juinn HORNG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Zhong ZHUANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Liang CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ya Yun LIU of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/082, G01K7/01, H01L21/8228, H01L29/06, H01L29/08, H01L29/10, H01L29/66, H01L29/735
CPC Code(s): H10D84/645
Abstract: a semiconductor device includes a bipolar junction transistor (bjt) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. the bjt structure includes active regions having different widths that form the emitters, the collectors, and the bases.
Inventor(s): Chieh-Ning Yang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Nai-Hsin Ting of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Fang-Ting Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ping-Pang Hsieh of Tainan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/06, H01L29/66, H01L29/78
CPC Code(s): H10D84/811
Abstract: a semiconductor device structure and methods of forming the same are described. the structure includes a first gate structure disposed over a substrate in an active device region, an insulating material disposed over the substrate in a passive device region, a resistor structure disposed over the insulating material in the passive device region, a first conductive contact electrically connected to the resistor structure, a second conductive contact disposed over the resistor structure, and a dielectric layer in contact with the second conductive contact and the resistor structure.
Inventor(s): Hao-Ming LIEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yen WOON of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Kun LO of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/12
CPC Code(s): H10D86/0214
Abstract: a method includes forming a fin structure over a bottom dielectric isolator and a substrate. the fin structure includes a bottom channel layer, a sacrificial layer over the bottom channel layer, and a top channel layer over the sacrificial layer. a dummy gate is formed across the fin structure. portions of the fin structure not covered by the gate structure are removed to expose a top surface of the bottom dielectric isolator. first source/drain epitaxial structures are epitaxially grown over the bottom dielectric isolator and are connected to the bottom channel layer. second source/drain epitaxial structures are epitaxially grown over the first source/drain epitaxial structures and are connected to the top channel layer. the dummy gate and the sacrificial layer are replaced with a gate structure.
Inventor(s): Cheng-Ling WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Yu LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Yi CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ting-Yun WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/12, H03K17/687
CPC Code(s): H10D86/60
Abstract: a integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. the first and third gate are on a first level. the second and fourth gate are on a second level. the second gate is coupled to the first gate. the fourth gate is coupled to the third gate. the first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. the first input pin is electrically coupled to the third gate by the first, second or fourth gate. the first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.
Inventor(s): Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/06, H01L21/768, H01L23/00, H01L23/522
CPC Code(s): H10D88/00
Abstract: a method of forming a semiconductor structure includes: forming an interconnect structure over a substrate; forming a pad over the interconnect structure, wherein the pad is electrically connected to the interconnect structure; forming a bonding dielectric layer over the interconnect structure; and forming a bonding metal layer in the bonding dielectric layer to electrically connect to the interconnect structure, wherein the bonding metal layer includes a via plug and a metal feature formed over the via plug, a height of the metal feature is greater than or equal to a height of the via plug.
Inventor(s): Tao-Yi HUNG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Wun-Jie LIN of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Jam-Wem LEE of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Ji CHEN of Wu-Ku, Taipei County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/02, H02H9/04
CPC Code(s): H10D89/911
Abstract: an electrostatic discharge (esd) protection apparatus and method for fabricating the same are disclosed herein. in some embodiments, the esd protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (esd) circuits patterned in a carrier wafer, where the esd circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient esd events, and where the device wafer is bonded to the carrier wafer.
Inventor(s): Cheng Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Hao Chuang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Hsien Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kazuaki Hashimoto of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Keng-Yu Chou of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Chieh Chiang of Yuanlin Township (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Hau Wu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146, H01L31/0216
CPC Code(s): H10F39/8067
Abstract: various embodiments of the present application are directed to a narrow band filter with high transmission and an image sensor comprising the narrow band filter. in some embodiments, the filter comprises a first distributed bragg reflector (dbr), a second dbr, a defect layer between the first and second dbrs, and a plurality of columnar structures. the columnar structures extend through the defect layer and have a refractive index different than a refractive index of the defect layer. the first and second dbrs define a low transmission band, and the defect layer defines a high transmission band dividing the low transmission band. the columnar structures shift the high transmission band towards lower or higher wavelengths depending upon a refractive index of the columnar structures and a fill factor of the columnar structures.
Inventor(s): Hau-Yan LU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Yen PENG of Chiayi City (TW) for taiwan semiconductor manufacturing co., ltd., YingKit Felix TSUI of Cupertino CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L31/0352, H01L31/0232
CPC Code(s): H10F77/147
Abstract: a photodetector may include an absorption region that is formed to have an increasing depth (or thickness) in a direction that is approximately parallel to the direction of incident light that is to be projected onto the absorption region. the increasing depth of the absorption region in the direction that is approximately parallel with the direction of incident light enables the incident light to be more uniformly distributed along the length of the absorption region in the direction that is approximately parallel with the direction of incident light. this reduces the likelihood that a particular area of the absorption region reaches optical saturation, which may enable the photodetector to operate a sustained high photodetector sensitivity and/or a sustained high light detection performance, among other examples.
Inventor(s): Jiun-Yun LI of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Jui WU of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-You LIU of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Tse TAI of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Ying LI of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N50/01, H10N50/20
CPC Code(s): H10N50/01
Abstract: a method includes epitaxially growing a gesnchannel layer over a substrate. the gesnchannel layer is in a metastable state. a gesnbarrier layer is epitaxially grown over the gesnchannel layer to form a two-dimensional hole gas in the gesnchannel layer. the gesnchannel layer and the gesnbarrier layer are etched to form a first opening and a second opening in the gesnchannel layer and the gesnbarrier layer. a first source/drain electrode and a second source/drain electrode are deposited in the first opening and the second opening, respectively. a gate electrode is formed over the gesnbarrier layer.
Inventor(s): Chia-Hua LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Che KU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Min-Yung KO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Ting SUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Zhen-Yu GUAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N50/10, H10B61/00, H10N50/01, H10N50/80
CPC Code(s): H10N50/10
Abstract: a semiconductor structure includes a conductive layer, an imd layer and a plurality of protrusions. the imd layer is formed on the conductive layer and has a first etch rate. each protrusion includes an etching slowing layer, a lower electrode and a mtj layer, wherein the etching slowing layer is formed on the imd layer and has a second etch rate, the lower electrode passes through the imd layer and the etching slowing layer, and the mtj layer is formed on the lower electrode. the second etch rate is less than the first etch rate.
Inventor(s): Zhi-Ren Xiao of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Nuo Xu of San Jose CA (US) for taiwan semiconductor manufacturing co., ltd., Po-Sheng Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yuan-Hao Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Zhiqiang Wu of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Jen WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N50/85, G11C11/16, H10B61/00, H10N50/10
CPC Code(s): H10N50/85
Abstract: a magnetic tunnel junction (mtj) structure and a memory cell are provided. the mtj includes a barrier layer, a free layer and a metal oxide cap layer. the free layer is disposed on the barrier layer. the metal oxide cap layer is disposed on the free layer. the metal oxide cap layer has a first surface and a second surface opposite to the first surface. the first surface of the metal oxide cap layer is in contact with the free layer. in a direction of a thickness of the metal oxide cap layer, both of an oxygen concentration at the first surface of the metal oxide cap layer and an oxygen concentration at the second surface of the metal oxide cap layer are higher than an oxygen concentration in a middle portion of the metal oxide cap layer.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on March 13th, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- G01N21/31
- G01N21/95
- CPC G01N21/31
- Taiwan semiconductor manufacturing co., ltd.
- G02B6/12
- H01L23/00
- H01L23/48
- H01L25/16
- CPC G02B6/12004
- G02B6/13
- G02B6/136
- G02B6/30
- G02B6/34
- CPC G02B6/13
- G03F1/24
- CPC G03F1/24
- G03F1/62
- H01L21/027
- CPC G03F1/62
- G03F7/039
- G03F7/09
- G03F7/11
- G03F7/20
- G03F7/38
- CPC G03F7/039
- G06F30/392
- G06F30/367
- G06F113/18
- G06F119/06
- CPC G06F30/392
- G11C8/18
- CPC G11C8/18
- G11C11/4099
- G11C11/4072
- G11C11/4074
- G11C11/408
- G11C11/4094
- CPC G11C11/4099
- G11C17/16
- G11C17/18
- H01L21/8238
- H01L27/092
- H01L29/06
- H01L29/66
- H01L29/78
- H01L29/786
- H10B20/25
- CPC G11C17/16
- CPC G11C17/165
- CPC G11C17/18
- H01L21/02
- C23C16/04
- H01L21/28
- H01L21/762
- H01L21/768
- H01L23/522
- H01L29/40
- CPC H01L21/0228
- H01L21/47
- CPC H01L21/02697
- H01L21/285
- H01L21/3065
- H01L21/311
- H01L21/8234
- H01L29/08
- H01L29/417
- H01L29/423
- H01L29/45
- CPC H01L21/28518
- H01L21/033
- CPC H01L21/31144
- H01L27/088
- H01L29/775
- CPC H01L21/76224
- H01L23/528
- CPC H01L21/76834
- CPC H01L21/76843
- H01L21/66
- C23C14/35
- C23C14/54
- H01J37/32
- H01J37/34
- CPC H01L22/26
- H01L23/367
- H01L21/52
- H01L21/56
- H01L23/31
- H01L23/498
- H01L23/538
- H01L25/00
- H01L25/065
- CPC H01L23/3675
- H01L27/12
- CPC H01L23/3677
- H01L23/373
- CPC H01L23/3736
- H01L23/42
- H01L23/29
- H01L23/36
- CPC H01L23/42
- H01L21/48
- CPC H01L23/49827
- CPC H01L23/5226
- G06F30/394
- G06F30/3947
- G06F30/398
- G06F119/12
- H01L23/525
- CPC H01L23/5252
- H01L23/28
- H10B80/00
- CPC H01L23/5383
- H01L23/544
- CPC H01L23/544
- H01L23/552
- CPC H01L23/552
- H01L23/532
- CPC H01L24/08
- CPC H01L24/09
- H01L23/40
- CPC H01L24/20
- B23K1/00
- B23K1/012
- B23K3/04
- B23K3/08
- CPC H01L24/75
- H01L27/06
- CPC H01L24/82
- CPC H01L25/0652
- CPC H01L25/0655
- CPC H01L25/0657
- H01L25/11
- H01L21/683
- H01L23/427
- H01L25/10
- CPC H01L25/117
- H01L25/18
- CPC H01L25/18
- H10B10/00
- CPC H10B10/125
- H10B51/20
- H10B51/10
- H10B51/30
- CPC H10B51/20
- H01L29/51
- CPC H10B51/30
- H01G4/30
- CPC H10D1/042
- H01L29/94
- CPC H10D1/66
- H01G15/00
- H01L21/3213
- CPC H10D1/68
- H01L29/10
- CPC H10D30/024
- CPC H10D30/6713
- CPC H10D30/701
- CPC H10D62/115
- CPC H10D62/116
- H01L29/04
- CPC H10D62/121
- CPC H10D62/159
- CPC H10D64/01
- CPC H10D64/017
- H01L29/49
- CPC H10D64/018
- CPC H10D64/258
- CPC H10D64/62
- CPC H10D84/038
- H01L27/082
- G01K7/01
- H01L21/8228
- H01L29/735
- CPC H10D84/645
- CPC H10D84/811
- CPC H10D86/0214
- H03K17/687
- CPC H10D86/60
- CPC H10D88/00
- H01L27/02
- H02H9/04
- CPC H10D89/911
- H01L27/146
- H01L31/0216
- CPC H10F39/8067
- H01L31/0352
- H01L31/0232
- CPC H10F77/147
- H10N50/01
- H10N50/20
- CPC H10N50/01
- H10N50/10
- H10B61/00
- H10N50/80
- CPC H10N50/10
- H10N50/85
- G11C11/16
- CPC H10N50/85