Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on January 30th, 2025
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on January 30th, 2025
Taiwan Semiconductor Manufacturing Co., Ltd.: 37 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L29/66 (10), H01L29/06 (9), H01L21/768 (9), H01L29/423 (8), H01L23/48 (7) H01L23/481 (6), H01L29/0673 (2), B08B3/02 (1), H03K19/018521 (1), H01L27/0688 (1)
With keywords such as: layer, structure, semiconductor, forming, device, dielectric, gate, substrate, drain, and source in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Shao-Yen KU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ying-Chuan SU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hao Yu WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Yung LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B08B3/02, A46B17/06
CPC Code(s): B08B3/02
Abstract: a brush wetting and cleaning system or tool including a brush wetting and cleaning housing. a wetting nozzle in fluid communication with a cavity in the brush wetting and cleaning housing. the wetting nozzle is configured to, in operation, wet a brush of a brush head inserted into the cavity of the brush wetting and cleaning housing. a spray nozzle in fluid communication with the cavity in the brush wetting and cleaning housing. the spray nozzle is configured to, in operation, clean the brush of the brush head inserted into the cavity of the brush wetting and cleaning housing. in a method of utilizing the brush wetting and cleaning system or tool, the brush of the brush head is wetted and cleaned between cleaning successive wafers or workpieces.
Inventor(s): ChunHung CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chen WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B32B43/00, B24B37/34, B32B7/12, B32B37/12
CPC Code(s): B32B43/006
Abstract: a pad removal device includes a pad guide extending along a first direction. the pad guide includes a first affixing component configured to affix a first end of the pad guide to a pad at a first pad location, and a second affixing component configured to affix a second end of the pad guide to the pad at a second pad location different from the first pad location. the pad removal device further includes a first actuator attached to the first end of the pad guide. the pad removal device further includes a control assembly coupled to the actuator, wherein the control assembly is configured to cause the first actuator to move the first end toward the second end along the first direction.
Inventor(s): Chun-Ming Wang of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Hsien-Li He of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chieh Chen of Taoyuan (TW) for taiwan semiconductor manufacturing co., ltd., Po-Hsuan Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wan-Yu Chao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): C01B11/04
CPC Code(s): C01B11/04
Abstract: a hypochlorous acid preparation system is provided. the hypochlorous acid preparation system includes: a hypochlorous acid preparation apparatus comprising: a first inlet, wherein sulfuric acid collected from a clean room located in a semiconductor fabrication plant enters the hypochlorous acid preparation apparatus through the first inlet; a second inlet, wherein sodium hypochlorite solution enters the hypochlorous acid preparation apparatus through the second inlet; a third inlet, wherein deionized water enters the hypochlorous acid preparation apparatus through the third inlet; and an outlet, wherein hypochlorous acid is produced in situ by mixing the sulfuric acid, the sodium hypochlorite solution, and the deionized water and exits the hypochlorous acid preparation apparatus through the outlet.
Inventor(s): Allen Timothy Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jui-Cheng Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chuan Tai of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Jie Huang of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01N33/543, G01N27/414
CPC Code(s): G01N33/54373
Abstract: a biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a buried oxide (box) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; a multi-layer interconnect (mli) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the mli structure; and a cap structure attached to the buried oxide layer, the cap structure comprising a microneedle.
Inventor(s): Sheng-Min WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ken-Hsien HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/24
CPC Code(s): G03F1/24
Abstract: an extreme ultraviolet (euv) photolithography reticle includes a substrate and a reflective multilayer on the substrate. the reflective multilayer includes a plurality of stacked first pairs of layers, each pair include a first layer of a first material and a second layer of a second material on the first layer. the reflective multilayer includes a second pair of layers between two of the first pairs and including a first process assistance layer and a third layer of the second material on the process assistance layer. the first material and the second material are selectively etchable with respect to the first process assistance layer. the reticle includes a plurality of first absorption structures extending from a top of the reflective multilayer to the first process assistance layer and configured to absorb extreme ultraviolet light.
Inventor(s): Jia-Hong GAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/392, H01L21/04, H01L27/02
CPC Code(s): G06F30/392
Abstract: a method of manufacturing an integrated circuit (ic) includes forming a first active region in a first cell. the method further includes forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell, and a height of the second cell is different from a height of the first cell. the method further includes forming a plurality of gate structures extending across each of the first active region and the plurality of second active regions. the method further includes removing a first portion of a first gate structure of the plurality of gate structures at an interface between the first cell and the second cell, wherein the first portion of the first gate structure is between the first active region and the plurality of second active regions.
Inventor(s): Chia-Cheng Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu Jie Hsiao of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Wei Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/4076, G11C11/408, G11C11/4093
CPC Code(s): G11C11/4076
Abstract: a memory device includes a memory array comprising a plurality of word lines, the plurality of word lines operatively coupled to a plurality of sets of memory cells, respectively. the memory device includes a controller operatively coupled to the memory array, and comprising an adaptive tracking circuit. the adaptive tracking circuit is configured to: receive a first signal conducted through a first tracking line; receive an address signal indicating one of the word lines to be asserted; and adjust, based on the address signal, a timing of a transition edge of a second signal conducted through a second tracking line.
Inventor(s): Chih-Wei Lee of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Han Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., You Tai Tsai of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/28, H01L29/06, H01L29/423, H01L29/49, H01L29/66, H01L29/775
CPC Code(s): H01L21/28088
Abstract: an exemplary method for forming a gate stack of a multigate device includes forming a gate dielectric over a channel layer and forming a gate electrode over the gate dielectric. forming the gate electrode includes forming a work function layer over the gate dielectric and forming a cap over the work function layer. forming the cap includes forming a metal nitride layer over the work function layer and forming a silicon-comprising layer over the metal nitride layer. forming the gate electrode includes forming a fluorine-free tungsten layer over the silicon-comprising layer of the cap without breaking vacuum. forming the fluorine-free tungsten layer over the silicon-comprising layer includes co-flowing a tungsten-comprising precursor (e.g., wcl) and a hydrogen-comprising precursor (e.g., h).
Inventor(s): Ming-Hsiang Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ting-Kui Chang of New Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Ming Huang of Changhua (TW) for taiwan semiconductor manufacturing co., ltd., Li-Chieh Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Che-Hao Tu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/321, C09G1/02, H01L21/768
CPC Code(s): H01L21/3212
Abstract: methods for chemical mechanical polishing (cmp), and methods for forming an interconnect structure of a semiconductor device are provided. the methods include performing cmp on a surface of a dielectric structure with a cmp slurry to remove a portion of a metal layer formed in the dielectric structure and having at least a first layer exposed through the surface. in some examples, the cmp slurry that includes an abrasive, an oxidizing agent, and a compound configured to reduce aggregation of the abrasive on the surface of the dielectric structure. in some examples, the compound has positively charged ions that interact with the abrasive to reduce aggregation of the abrasive on a dielectric material. in some examples, the cmp slurry includes potassium hydroxide. in some examples, the compound includes an ammonium salt.
Inventor(s): Yen Yu Chen of Pingtung City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Liang Cheng of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Ying-Han Chiou of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/522
CPC Code(s): H01L21/76844
Abstract: a method of forming a semiconductor structure includes forming a conductive capping layer over a conductive feature, forming a dielectric layer over the conductive capping layer, forming an opening in the dielectric layer to expose a top surface of the conductive capping layer, forming an inhibitor film at the top surface of the conductive capping layer, depositing a barrier layer on sidewalls of the opening, removing the inhibitor film to expose the top surface of the conductive capping layer, depositing a supplementary liner on the barrier layer and the top surface of the conductive capping layer, and depositing a conductive material on the supplementary liner and filling the opening.
Inventor(s): Yi-Yi Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Yu Lu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Liang Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., LI-CHUN TIEN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/8238, H01L27/092, H01L29/08, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H01L23/481
Abstract: a device including a first vertical field effect transistor having a first drain/source region and a second drain/source region, and a second vertical field effect transistor having a third drain/source region and a fourth drain/source region. the device including a first power contact situated on a frontside of the device and coupled to the first drain/source region, a second power contact situated on the frontside of the device and coupled to the third drain/source region, and a contact situated on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region.
Inventor(s): Wei-Cheng TZENG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Wei PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Yen LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Cheng LIN of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Jiann-Tyng TZENG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/8238, H01L27/092
CPC Code(s): H01L23/481
Abstract: an integrated circuit is provided, including a first transistor of a first conductivity type comprising first and second active regions, a second transistor of a second conductivity type comprising third and fourth active regions and arranged under the first transistor along a first direction, a first gate structure extending in the first direction and shared by the first and second transistors, an isolation layer sandwiched between the first and second transistors and extending along a second direction to pass through the first gate structure, and a connection layer surrounded by the isolation layer and extending along the second direction to pass through the first gate structure. the isolation layer has a first surface contacting the first and second active regions and a second surface contacting the third and fourth active regions. the connection layer comprises first and second portions are electrically coupled to the first and fourth active regions.
Inventor(s): Hsin-Yuan LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Kai YANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ken-Hsien HSIEH of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ya Hui CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/768, H01L23/367
CPC Code(s): H01L23/481
Abstract: a semiconductor die includes a substrate, a semiconductor device, a back-end-of-line (beol) structure, and a heat dissipation structure. the substrate includes a device region and a non-device region. the beol structure includes a plurality of metallization layers. each of the metallization layers includes a dielectric layer, interconnect features, and metal patterns. the interconnect features is in the dielectric layer and over the device region of the substrate, in which the interconnect features are electrically connected with the semiconductor device. the metal patterns are in the dielectric layer and over the non-device region of the substrate, in which the metal patterns are electrically isolated from the semiconductor device. the heat dissipation structure is over the non-device region of the substrate and extending through at least two of the metallization layers, in which the heat dissipation structure is in contact with the metal patterns of one of the metallization layers.
Inventor(s): Ke-Han SHEN of Chiayi City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Yuan CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Jiung WU of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Yi Kuo of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Ju LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Tung-He CHOU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ji CUI of Bolingbrook IL (US) for taiwan semiconductor manufacturing co., ltd., Kuo-Chung YEE of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua YU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chieh HSIEH of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Jen LIEN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Yian-Liang KUO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Hao TSENG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jen Yu WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Chieh Chou of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/768, H01L23/00, H01L29/06, H01L29/423, H01L29/775
CPC Code(s): H01L23/481
Abstract: a package structure and a method for forming the same are provided. the package structure includes a first package structure and a second package structure. the first package structure includes a first device formed over a first substrate. the first device includes a first conductive plug connected to a through substrate via (tsv) structure formed in the first substrate. a buffer layer surrounds the first substrate. a first bonding layer is formed over the first substrate and the buffer layer. the second package structure includes a second device formed over a second substrate. a second bonding layer is formed over the second device. a hybrid bonding structure is between the first package structure and the second package structure by bonding the first bonding layer to the second bonding layer.
Inventor(s): Tsung-Chieh Hsiao of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Yi Ling Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yun-Sheng Li of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ke-Gang Wen of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Bey Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Liang-Wei Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/768, H01L23/522, H01L23/528
CPC Code(s): H01L23/481
Abstract: a method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. the second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.
Inventor(s): Hung-Ling Shih of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Ming Chyi Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jiech-Fun Lu of Madou Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/768, H01L27/146
CPC Code(s): H01L23/481
Abstract: in some embodiments, the present disclosure relates to an integrated chip. the integrated chip includes a conductive structure disposed within a dielectric structure along a first side of a substrate. an insulating structure is disposed along inner sidewalls of the substrate and a blocking layer is disposed along a first inner sidewall and a second inner sidewall of the insulating structure, as viewed in a cross-sectional view. a through-substrate via (tsv) extends vertically through the substrate and along a horizontally-extending surface of the insulating structure. the horizontally-extending surface protrudes outward from the first inner sidewall of the insulating structure and towards the second inner sidewall of the insulating structure.
Inventor(s): Po-Hao Tsai of Zhongli (TW) for taiwan semiconductor manufacturing co., ltd., Po-Yao Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Techi Wong of Zhubei (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L25/00, H01L25/065
CPC Code(s): H01L23/49822
Abstract: a semiconductor device and method of manufacture are provided whereby an interposer and a first semiconductor device are placed onto a carrier substrate and encapsulated. the interposer comprises a first portion and conductive pillars extending away from the first portion. a redistribution layer located on a first side of the encapsulant electrically connects the conductive pillars to the first semiconductor device.
Inventor(s): Wen-Chiung Tu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsiang-Ku Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Chiu Huang of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shu Fang Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L21/768, H01L23/522, H01L23/58
CPC Code(s): H01L23/528
Abstract: the present disclosure provides a semiconductor structure that includes a substrate having a circuit region and a seal ring region around the circuit region. the seal ring region includes a multi-layer interconnect to form a seal ring structure. and a redistribution layer is formed over the seal ring structure. the redistribution layer is formed on the edges of the seal ring region, and excluded from corner regions of the seal ring.
Inventor(s): Kuo-Chang Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Katherine Chiang of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te Lin of Tainan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/552, H01L29/786
CPC Code(s): H01L23/552
Abstract: a transistor comprises a colored light shielding layer over the semiconductor layer thereof. the colored light shielding layer reduces exposure of the semiconductor layer to radiation having a wavelength of about 10 nanometers (nm) to about 400 nm. the colored light shielding layer may have a white, black, red, yellow, or gray color. the colored light shielding layer can be formed from a metal oxide film, a p-type oxide semiconductor, or a perovskite. the colored light shielding layer reduces defects that may be generated in the semiconductor layer due to uv light exposure during the manufacturing process, improving device performance and reliability.
Inventor(s): Wei-Chih Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jhih-Yu Wang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Han Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang Hu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/48, H01L23/522, H01L25/00, H10B80/00
CPC Code(s): H01L25/0652
Abstract: a method includes forming a metal post over a first redistribution structure; attaching a first device die to the first redistribution structure, the first device die comprising a through via embedded in a semiconductor substrate; encapsulating the metal post and the first device die in an encapsulant, a first top surface of the encapsulant being level with a second top surface of the semiconductor substrate; recessing the second top surface to expose the through via; forming a dielectric isolation layer around the through via; forming a dielectric layer over the dielectric isolation layer; etching the dielectric layer to form a first opening and a second opening in the dielectric layer; forming a first metal via in the first opening and a second metal via in the second opening; and forming a second redistribution structure over the dielectric layer.
Inventor(s): Jam-Wem Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wun-Jie Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Jung Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Wei Chu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H02H9/04
CPC Code(s): H02H9/045
Abstract: devices, circuits, and methods for electrostatic discharge (esd) protection are provided. an electrostatic discharge (esd) protection circuit comprises a first transistor connected between a first voltage and a second voltage, and a first control circuit connected between the first voltage and the second voltage, and configured to supply a control signal to the first transistor. the circuit further comprises a second transistor connected between the second voltage and a third voltage, and a second control circuit connected between the second voltage and the third voltage, and configured to supply a control signal to the second transistor. the first control circuit and the second control circuit are connected to each other via a first interconnect and a second interconnect. the first and second transistors are configured to turn on in response to an esd event.
20250038748. LEVEL SHIFTER ENABLE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Srinivasan Ramarajan of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K19/0185, H03K3/037, H03K3/356, H03K19/00
CPC Code(s): H03K19/018521
Abstract: a multi-bit level shifter that has a plurality of level shifters, each of which is configured to receive an input signal in a first voltage domain and provide a corresponding output signal in a second voltage domain. the level shifters each have an enable node. an enable circuit includes an output terminal connected to the enable node of each of the plurality of level shifters, and each of the plurality of level shifters is configured to output the corresponding output signals in response an enable signal received by the enable circuit.
Inventor(s): Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-En Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Ching Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B51/20, H10B51/30
CPC Code(s): H10B51/20
Abstract: one aspect of this description relates to a semiconductor device. in some embodiments, the semiconductor device includes a first drain/source structure extending in a first direction, a second drain/source structure extending the first direction and spaced from the first drain/source structure in a second direction perpendicular to the first direction, a third drain/source structure extending in the first direction and spaced from the second drain/source structure in the second direction, a first bit line disposed over the first drain/source structure in the first direction, a common select line that includes a portion disposed over the second drain/source structure in the first direction, a second bit line disposed over the third drain/source structure in the first direction, and a charge storage layer coupled to at least a first sidewall of each of the first drain/source structure, the second drain/source structure, and the third drain/source structure.
Inventor(s): Wei-Liang Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Lei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Anhao Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Liang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ru-Shang Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/94, H01L29/66
CPC Code(s): H01L29/94
Abstract: a semiconductor structure includes a substrate and a capacitor over the substrate. the capacitor includes a silicide layer over the substrate. the capacitor includes a first dielectric layer over the silicide layer. the capacitor includes a metal gate structure over the first dielectric layer, where a top portion of the metal gate structure is over the substrate and a bottom portion of the metal gate structure extends into the substrate. the capacitor includes a second dielectric layer over the metal gate structure. the capacitor further includes a conductive structure over the second dielectric layer.
Inventor(s): Chih-Hao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Hao CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Yi PENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source/drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer; forming a dielectric layer on the source/drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; forming a liner layer on exposed surfaces of the source/drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surface, sidewalls and a bottom surface of the source/drain region.
Inventor(s): Chia-Hao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Ting PAN of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Jia-Chuan YOU of Taoyuan (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/06, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/42392
Abstract: various embodiments of the present disclosure provide a semiconductor device structure. in one embodiment, the semiconductor device structure includes a dielectric wall disposed over a substrate, first and second metal gate structure portions respectively disposed at either side of the dielectric wall. each first and second metal gate structure portion includes a plurality of semiconductor layers vertically stacked and separated from each other, a high-k (hk) dielectric layer disposed to surround at least three surfaces of each of the semiconductor layers, and a gate electrode layer disposed between two neighboring semiconductor layers. the semiconductor device structure also includes a metal layer disposed on two opposing sidewalls of the dielectric wall.
Inventor(s): Yu-Sheng CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Pang-Hsuan LIU of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Hui WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ju-Li HUANG of Nantou County (TW) for taiwan semiconductor manufacturing co., ltd., Jeng-Ya YEH of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a method for forming a semiconductor structure is provided. the method includes forming a first nanostructure and a second nanostructure over a substrate, forming a first interfacial layer on the first nanostructure and a second interfacial layer on the second nanostructure, forming a first gate dielectric layer on the first interfacial layer and a second gate dielectric layer on the second interfacial layer, forming a patterned mask layer on the second gate dielectric layer while exposing the first gate dielectric layer, and driving nitrogen into the first interfacial layer, thereby forming a nitrogen-doped interfacial layer.
Inventor(s): Ming-Shuan LI of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Lung CHENG of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L29/66, H01L29/78
CPC Code(s): H01L29/0673
Abstract: a semiconductor device structure includes first nanostructures formed over a substrate. the structure also includes a first gate structure wrapping around the first nanostructures. the structure also includes a first source/drain epitaxial structure formed beside the first nanostructures. the structure also includes a first inner spacer between the first gate structure and the first source/drain epitaxial structure. the structure also includes second nanostructures formed over the first nanostructure. the structure also includes a second gate structure wrapping around the second nanostructures. the structure also includes a second source/drain epitaxial structure formed beside the second nanostructures. the structure also includes a second inner spacer between the second gate structure and the second source/drain epitaxial structure. a sidewall of the second inner spacer is spaced apart from a sidewall of the first inner spacer when viewed from above.
Inventor(s): Kuei-Yu Kao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Yao Lin of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Chiung-Yu Cho of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Po-Yuan Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Min-Chiao Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Ping Chen of Yilan (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Ching Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L29/06, H01L29/423
CPC Code(s): H01L29/66545
Abstract: a semiconductor fabrication method includes: forming an epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a plurality of fins in the epitaxial stack; performing tuning operations to prevent a width of the sacrificial epitaxial layer expanding beyond a width of the channel epitaxial layer during operations to form isolation features; forming the isolation features between the plurality of fins, wherein the width of the sacrificial epitaxial layer does not expand beyond the width of the channel epitaxial layer; forming a sacrificial gate stack; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layer and the channel epitaxial layer; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layer; and forming a replacement metal gate, wherein the metal gate is shielded from the source/drain features.
Inventor(s): Chun Hsiung TSAI of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Clement Hsingjen WANN of Carmel NY (US) for taiwan semiconductor manufacturing co., ltd., Kuo-Feng YU of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Hsi YEH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/28, H01L21/8234, H01L29/51
CPC Code(s): H01L29/6656
Abstract: the present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. the semiconductor device also includes a multi-spacer structure. the multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. the second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. the second portion of the second spacer has a thickness in a first direction that gradually decreases. the third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. the semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.
20250040219. SEMICONDUCTOR DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Po-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wan-Hua HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jing-Ying CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/40, H01L29/06, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/402
Abstract: a semiconductor device includes an isolation structure in a substrate. the semiconductor device further includes a gate structure over a first region of the substrate, wherein the isolation structure surrounds the first region, the gate structure comprising a first section and a second section. the semiconductor device further includes a conductive field plate over the substrate, the conductive field plate extending between the first section and the second section and overlapping an edge of the first region, wherein the conductive field plate comprises a dielectric layer having a variable thickness. the semiconductor device further includes a first well in the substrate, wherein the first well overlaps the edge of the first region, and the first well extends underneath the isolation structure, and the conductive field plate extends beyond an outer-most edge of the first well.
Inventor(s): Shih-Wei PENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Min HSIAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jiann-Tyng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/311, H01L21/768, H01L23/522, H01L23/528, H01L29/40
CPC Code(s): H01L29/4175
Abstract: a method of fabricating an integrated circuit includes fabricating a set of transistors and a dummy via in a front-side of a substrate, performing thinning on a back-side of the substrate opposite from the front-side, fabricating a first set of vias and a first set of conductors on the back-side of a thinned substrate on a first level, the first set of conductors being electrically coupled to the set of transistors by the first set of vias, fabricating a second set of vias on the back-side of the thinned substrate, and depositing a conductive material on the back-side of the thinned substrate on a second level thereby forming a second set of conductors, the second set of conductors being electrically coupled to the first set of conductors by the second set of vias.
Inventor(s): Guan-Lin Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Chien Cheng of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Shi Ning Ju of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/088, H01L21/8234
CPC Code(s): H01L27/088
Abstract: a method for manufacturing an integrated circuit device is provided. the method includes depositing an epitaxial stack comprising alternative first and second semiconductor layers over a semiconductor substrate; patterning the epitaxial stack to form first and second semiconductor fins; removing the first semiconductor layers in the first and second semiconductor fins, while leaving a first set of the second semiconductor layers in the first semiconductor fin and a second set of the second semiconductor layers in the second semiconductor fin; forming a gate dielectric layer around the first and second sets of the second semiconductor layers; depositing a gate metal layer over the gate dielectric layer; etching a recess in the gate metal layer and between the first and second sets of the second semiconductor layers, wherein the gate metal layer has a first portion below the recess; and forming a dielectric feature in the recess.
Inventor(s): Yu-Wei Lu of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Kenichi Sano of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tze-Chung Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Fang-Wei Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Chien Kuang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Chen Lo of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Fo-Ju Lin of Keelung City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Te Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Pinyen Lin of Rochester NY (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/417, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L27/092
Abstract: in an embodiment, a device includes: lower semiconductor nanostructures including a first semiconductor material; a lower epitaxial source/drain region adjacent the lower semiconductor nanostructures, the lower epitaxial source/drain region having a first conductivity type; upper semiconductor nanostructures including a second semiconductor material, the second semiconductor material different from the first semiconductor material; and an upper epitaxial source/drain region adjacent the upper semiconductor nanostructures, the upper epitaxial source/drain region having a second conductivity type, the second conductivity type being opposite the first conductivity type.
20250040254. PACKAGE STRUCTURES_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Wen Shih of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/06, H01L21/768, H01L21/78, H01L23/538
CPC Code(s): H01L27/0688
Abstract: a package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. the first die and a second die are bonded to a first side of the bottom die. the encapsulant laterally encapsulates the first die and the second die. the first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.
Inventor(s): Chien-Min Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shy-Jay Lin of Jhudong Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N52/80, H01F10/32, H01F41/30, H10N50/01, H10N50/10, H10N50/80, H10N50/85, H10N52/00, H10N52/01
CPC Code(s): H10N52/80
Abstract: a magnetic memory device includes a spin-orbit torque (sot) induction spin hall electrode and a free layer of a magnetic tunnel junction (mtj) stack disposed on the spin hall electrode which is a synthetic anti-ferromagnetic structure. the free layer has a magnetic moment which is askew of the long axis of the mtj stack and askew the direction of current flow through the spin hall electrode. the mtj stack internally generates a magnetic field to switch the state of the free layer. the free layer includes a first layer separated from a second layer by a spacer layer, where the first layer and the second layer may have the same or different crystalline structures.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on January 30th, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- B08B3/02
- A46B17/06
- CPC B08B3/02
- Taiwan semiconductor manufacturing co., ltd.
- B32B43/00
- B24B37/34
- B32B7/12
- B32B37/12
- CPC B32B43/006
- C01B11/04
- CPC C01B11/04
- G01N33/543
- G01N27/414
- CPC G01N33/54373
- G03F1/24
- CPC G03F1/24
- G06F30/392
- H01L21/04
- H01L27/02
- CPC G06F30/392
- G11C11/4076
- G11C11/408
- G11C11/4093
- CPC G11C11/4076
- H01L21/28
- H01L29/06
- H01L29/423
- H01L29/49
- H01L29/66
- H01L29/775
- CPC H01L21/28088
- H01L21/321
- C09G1/02
- H01L21/768
- CPC H01L21/3212
- H01L23/522
- CPC H01L21/76844
- H01L23/48
- H01L21/8238
- H01L27/092
- H01L29/08
- H01L29/417
- H01L29/78
- CPC H01L23/481
- H01L23/367
- H01L23/00
- H01L23/528
- H01L27/146
- H01L23/498
- H01L21/48
- H01L21/56
- H01L21/683
- H01L23/31
- H01L25/00
- H01L25/065
- CPC H01L23/49822
- H01L23/58
- CPC H01L23/528
- H01L23/552
- H01L29/786
- CPC H01L23/552
- H10B80/00
- CPC H01L25/0652
- H02H9/04
- CPC H02H9/045
- H03K19/0185
- H03K3/037
- H03K3/356
- H03K19/00
- CPC H03K19/018521
- H10B51/20
- H10B51/30
- CPC H10B51/20
- H01L29/94
- CPC H01L29/94
- CPC H01L29/41733
- H01L21/8234
- H01L27/088
- CPC H01L29/42392
- CPC H01L29/0673
- CPC H01L29/66545
- H01L29/51
- CPC H01L29/6656
- H01L29/40
- CPC H01L29/402
- H01L21/311
- CPC H01L29/4175
- CPC H01L27/088
- CPC H01L27/092
- H01L27/06
- H01L21/78
- H01L23/538
- CPC H01L27/0688
- H10N52/80
- H01F10/32
- H01F41/30
- H10N50/01
- H10N50/10
- H10N50/80
- H10N50/85
- H10N52/00
- H10N52/01
- CPC H10N52/80