Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on December 26th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on December 26th, 2024
Taiwan Semiconductor Manufacturing Co., Ltd.: 34 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L29/66 (16), H01L29/06 (13), H01L29/775 (12), H01L29/423 (12), H01L29/786 (8) H01L29/0673 (3), H01L29/775 (2), H01L29/66439 (2), G02B6/122 (1), H01L27/14636 (1)
With keywords such as: layer, structure, semiconductor, device, dielectric, third, substrate, region, portion, and channel in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Chia-Ning Weng of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming Chou of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shih Wei Liang of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Nien-Fang Wu of Chiayi City (TW) for taiwan semiconductor manufacturing co., ltd., Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/122, G02B6/136
CPC Code(s): G02B6/122
Abstract: optical devices and methods of manufacture are presented herein. in an embodiment, an optical device is provided that includes a first substrate, the first substrate including an optical device layer, and a semiconductor die, a first waveguide structure over the first substrate, the first waveguide structure including a first optical component surrounded by cladding material, wherein the first waveguide structure has a top surface, the top surface including a first portion at a first distance from the first substrate, a second portion at a second distance from the first substrate, and a transition portion between the first portion to the second portion, wherein the second distance is greater than the first distance, and a first reflective structure over the first portion and the transition portion, wherein a portion of the first reflective structure over the transition portion is a curved surface.
20240427489. SEMICONDUCTOR DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Sheng-Po HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Hsiang HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0604
Abstract: a semiconductor device includes a memory array. the memory array is configured to calculate first data and second data, and includes a first memory cell and a second memory cell. the first memory cell is configured to generate a first current signal at a first node, in response to the first data. the second memory cell is configured to generate a second current signal at the first node when the first memory cell generating the first current signal, in response to the second data. when the first data has a first data value and the second data has a second data value, the second memory cell is further configured cancel the first current signal with the second current signal. the second data value is a negative value of the first data value.
Inventor(s): Cheng-Hsien Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Jer Tzeng of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Xinyu BAO of Fremont CA (US) for taiwan semiconductor manufacturing co., ltd., Hengyuan Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C13/00, G11C11/16
CPC Code(s): G11C13/003
Abstract: operating method, memory system, and control circuit are provided. the operating method is for operating a memory device comprising a selector and a memory element serially coupled to the selector. the operating method comprises presetting the memory device by providing a preset signal to the memory device, wherein the preset signal is clamped at a first current; and accessing the memory device by providing an access signal to the memory device, wherein a second current greater than the first current flows through the memory device when the access signal is provided to the memory device.
Inventor(s): Chia-Hsi Wang of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Yu Chen of Taichung (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01J37/34, C23C14/34, C23C14/54
CPC Code(s): H01J37/3479
Abstract: a physical vapor deposition (pvd) system includes: a chamber body; a substrate support disposed within the chamber body and capable of supporting a substrate; a pvd target; and a target profile monitoring subsystem. the pvd target includes: a target plate comprising a target material; and a backing plate attached to the target plate and comprising: a central section; and a peripheral section circumferentially surrounding the central section in a horizontal plane. the peripheral section has a first thickness in a vertical direction, the central section has a second thickness in the vertical direction, and the first thickness is larger than the second thickness. the target profile monitoring subsystem is configured to monitor usage of the target plate.
Inventor(s): Hui-Chun LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Tung-Hung FENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Peng-Ting LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/027, G03F7/16, G03F7/38, H01L21/033, H01L21/308
CPC Code(s): H01L21/0274
Abstract: a method of manufacturing a semiconductor device includes the following steps. a photoresist layer is formed over a material layer on a substrate. the photoresist layer is exposed. an organic treatment is performed to the photoresist layer by a hydrophobic organic compound. after performing the organic treatment, the photoresist layer is developed. the material layer is etched using the photoresist layer as a mask.
Inventor(s): Chao-Hsuan CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., I-Wei YANG of Yilan (TW) for taiwan semiconductor manufacturing co., ltd., Chang-Han TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Uei JANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Yuan KU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yih-Ann LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ryan Chia-Jen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/3213, H01L21/02, H01L21/033, H01L21/28, H01L29/66
CPC Code(s): H01L21/32136
Abstract: methods for etching metal, such as for processing a metal gate, are provided. a method includes forming a hard mask over the metal, wherein the hard mask includes a sidewall defining an opening; and performing a plasma etching process including cycles of depositing a carbon nitride film on the sidewall and etching the metal.
Inventor(s): Yi-Chang CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yao Hwan Kao of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/67
CPC Code(s): H01L21/67017
Abstract: the present disclosure describes a processing system that includes a stage configured to hold a substrate thereon and an exhaust system. the exhaust system can include a perforated plate with a exhaust holes and an exhaust port. the perforated plate can be positioned between the substrate and the exhaust port. each of the exhaust holes includes a shutter.
Inventor(s): Yao-Jhen Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jiann-Horng Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chung Ta Han of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsiang-Ku Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L21/311, H01L21/3213, H01L23/522, H01L23/528, H01L23/532
CPC Code(s): H01L21/76814
Abstract: a method includes providing a workpiece. the workpiece includes a substrate, a first dielectric layer over the substrate, a lower contact feature vertically extending through the first dielectric layer, a second dielectric layer over the lower contact feature and the first dielectric layer, a third dielectric layer over the second dielectric layer, a metal-insulator-metal (mim) structure over the third dielectric layer, and a fourth dielectric layer over the mim structure. the method further includes performing a first etch process to form an opening through the fourth dielectric layer to expose the mim structure; performing a second etch process to extend the opening through the mim structure to expose the third dielectric layer; performing a third etch process to further extend the opening into the third dielectric layer; and performing a fourth etch process to further extend the opening through the second dielectric layer to expose the lower contact feature.
Inventor(s): Jen-Chun Liao of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Wei Lin of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chih Chiou of Zhunan Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/78, H01L21/66
CPC Code(s): H01L21/78
Abstract: a method includes forming a database, finding a plurality of dicing marks on a wafer, wherein patterns of the plurality of dicing marks match a pattern in the database, measuring a die pitch of the wafer according to a patch of adjacent two of the plurality of dicing marks, and determining kerf centers of the wafer based on the plurality of dicing marks. the measuring the die pitch and the determining the kerf centers are performed on a same wafer-holding platform. the wafer is diced into a plurality of dies, and the dicing is performed aligning to the kerf centers.
Inventor(s): Wei-Yip LOH of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Hsu Chen of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Chien Chi of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Harry Chien of Chandler AZ (US) for taiwan semiconductor manufacturing co., ltd., Chih-Wei Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/45, H01L29/66, H01L29/775
CPC Code(s): H01L21/823475
Abstract: a method includes forming a bottom-tier transistor and a top-tier transistor over the bottom-tier transistor, the top-tier transistor comprising a first channel layer, a first gate structure around the first channel layer, and a plurality of first source/drain regions on opposite sides of the first channel layer; forming a first dielectric layer over the first source/drain regions of the top-tier transistor; etching the first dielectric layer to form a first opening exposing one of the first source/drain regions of the top-tier transistor; selectively forming a first metal silicide on the one of the first source/drain regions; selectively forming a first metal cap on the first metal silicide and not on the first dielectric layer; forming a front-side contact on the first metal cap.
Inventor(s): Min-Feng KAO of Chiayi City (TW) for taiwan semiconductor manufacturing co., ltd., Shyh-Fann TING of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hsien LIN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Dun-Nian YAUNG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/768, H01L23/498, H01L23/522, H01L23/528, H01L25/065
CPC Code(s): H01L23/481
Abstract: some implementations herein provide a semiconductor device and methods for forming the semiconductor device. a multi-layer structure of the semiconductor device includes a metal ring structure and a dielectric sidewall structure along interior sidewalls of the metal ring structure. an interconnect structure (e.g., a through silicon via interconnect structure) is along a central interior axis of the metal ring structure. a protective layer is between the interconnect structure and the dielectric sidewall structure. during a deposition operation that fills a cavity with a conductive material to form the interconnect structure, the protective layer may protect the dielectric sidewall structure from damage to improve a quality and/or a reliability of the semiconductor device.
Inventor(s): Ming-Hung Tseng of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Sung Huang of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Hsien Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., An-Jhih Su of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Jin Hu of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Hua-Wei Tseng of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Hsien Hsieh of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Cheng Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Der-Chyang Yeh of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/498, H01L21/60, H01L23/00
CPC Code(s): H01L23/49811
Abstract: a semiconductor device includes first ic dies disposed side-by-side, a second ic die overlapping and electrically coupled to the first ic dies, and first conductive features. each first ic die includes first and second die connectors. a first pitch of the first die connectors is less than a second pitch of the second die connectors and is substantially equal to a third pitch of the third die connectors of the second ic die. the first conductive features are interposed between and electrically coupled to the first and third die connectors. each first conductive feature includes at least a first conductive bump and at least a first conductive joint.
Inventor(s): Chia-Yueh Chou of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Hsiang-Ku Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Chung Yu of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Ling Chang of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Chiu Huang of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Hao Hou of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Hung Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Alvin Universe Tang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kun-Yu Lee of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Hsiu Chiang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
CPC Code(s): H01L23/5223
Abstract: a device includes a first dielectric layer. a second dielectric layer is disposed over the first dielectric layer. the second dielectric layer and the first dielectric layer have different material compositions. a metal-insulator-metal (mim) structure is embedded in the second dielectric layer. a third dielectric layer is disposed over the second dielectric layer. the third dielectric layer and the second dielectric layer have different material compositions. the first dielectric layer or the third dielectric layer may contain silicon nitride (sin), the second dielectric layer may contain silicon oxide (sio).
Inventor(s): Yi-Yi CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Chun TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jiann-Tyng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Yu LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L21/8238, H01L23/522, H01L27/092, H01L29/417
CPC Code(s): H01L23/5286
Abstract: an integrated circuit includes a first-type active-region structure and a second-type active-region structure extending in a first direction and a first terminal-conductor and a second terminal-conductor extending in a second direction. the integrated circuit also includes a first power stub and a second power stub in a first metal layer and a first power line and a second power line in a second metal layer. the integrated circuit further includes a first via connector directly connected between the first power stub and the first terminal-conductor, a second via connector directly connected between the second power stub and the second terminal-conductor, a third via connector directly connected between the first power stub and the first power line, and a fourth via connector directly connected between the second power stub and the second power line.
Inventor(s): Yi-Hsuan Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Hao Chuang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Keng-Yu Chou of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Hau Wu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Chieh Chiang of Yuanlin Township (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Kung Chang of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14627
Abstract: an image sensing device includes a germanium sensor within a semiconductor body and a metalens formed in the back side of the semiconductor body. the metalens is structured to focus infrared light on the germanium sensor and may have a lower profile than an equivalent microlens. optionally, the metalens is combined with a microlens to achieve a desired focal length. the metalens, or the metalens in combination with a microlens, overcomes a manufacturing process limitation on the focal length of the microlens, which in turn eliminates the need for, or reduces the thickness of, a spacer between the microlens and the germanium sensor. eliminating the spacer or reducing its thickness improves the angular response of the image sensing device.
Inventor(s): Cheng-Ying Ho of Minxiong Township (TW) for taiwan semiconductor manufacturing co., ltd., Wen-De Wang of Minsyong Township (TW) for taiwan semiconductor manufacturing co., ltd., Kai-Chun Hsu of Yonghe City (TW) for taiwan semiconductor manufacturing co., ltd., Yuh Ruey Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Lung Cheng of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1463
Abstract: a process used to form a first deep trench isolation (dti) structure in a pixel region of a semiconductor substrate is also used to form a second dti structure in a guard ring area that isolates the pixel region from a peripheral region. the guard ring area may have a pnp guard ring structure. the second dti structure may include trenches in each of an inner ring, a middle, and an outer ring of the pnp guard ring structure. the first and second dti structures may have conductive cores. the conductive cores of the inner and outer ring may be biased to a first voltage while the conductive cores of the middle ring may be biased to an opposite polarity second voltage. when the second dti structure have conductive cores with these biases, the second dti structure may be used as the guard ring without the pnp structure.
Inventor(s): Chuan-Cheng Tsou of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Sung-Hsin Yang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Chi Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Chieh Chiang of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Ru-Shang Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ling-Sung Wang of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146, H01L25/065
CPC Code(s): H01L27/14636
Abstract: embodiments of the present disclosure relate to methods for forming a film stack during fabrication or bonding process. the film stack according to present disclosure may reduce wet dip attacking to semiconductor substrate during bonding, such as bonding between an image sensor substrate and a logic device substrate. the film stack according to the present disclosure may be used to modulate stress and wafer warpage to improve bonding adhesion and device performance during various packaging schemes, such as cowos, soic, or the like. the film stack according to the present disclosure may be used to improve bonding process and device performance in both wafer-to-wafer bonding and die-to-die bonding.
Inventor(s): Kuan-Ting PAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a semiconductor device includes a semiconductor substrate, a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a dielectric wall, and a first isolation feature. the first semiconductor structure, the second semiconductor structure and the third semiconductor structure are disposed on the semiconductor substrate. the first semiconductor structure is disposed between the second semiconductor structure and the third semiconductor structure. the dielectric wall is disposed on the semiconductor substrate and is connected between the first semiconductor structure and the second semiconductor structure. the first isolation feature is disposed between the first semiconductor structure and the third semiconductor structure, and extends into the semiconductor substrate.
Inventor(s): Meng-Yu LIN of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Fu CHENG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a semiconductor device includes a substrate, a semiconductor nanostructure over the substrate, a gate dielectric layer wrapping around the semiconductor nanostructure and a gate electrode over the gate dielectric layer. the semiconductor nanostructure includes a plurality of first strips extending along a first direction and a plurality of second strips along a second direction, and wherein the second direction crosses the first direction.
Inventor(s): Yu-Sheng Chen of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ju-Li Huang of Nantou County (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Hui Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jeng-Ya Yeh of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a method of manufacturing a semiconductor device includes forming a first stack of nanostructures suspended in a first region, a second stack of nanostructures suspended in a second region, and a third stack of nanostructures suspended in a third region, depositing a first work function (wf) layer wrapping around the nanostructures in the first, second, and third regions, removing the first wf layer from the first and second regions, depositing a second wf layer wrapping around the nanostructures in the first and second regions and over the first wf layer in the third region, removing the second wf layer from the first region, depositing a third wf layer wrapping around the nanostructures in the first region and over the second wf layer in the second and third regions, and forming a capping layer over the third wf layer in the first, second, and third regions.
Inventor(s): Che-Chun LU of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsing CHU of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Yi TSENG of Tainan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/10, H01L29/66, H01L29/78
CPC Code(s): H01L29/1037
Abstract: the present disclosure describes forming a semiconductor structure having an isolation layer surrounding a sloped portion of a channel structure. the semiconductor structure includes a channel structure having first, second, and third portions on a substrate. the first portion has a first width. the second portion has a second width less than the first width. the third portion has a third width less than the second width. the semiconductor structure further includes a first isolation layer on the substrate and surrounding the first portion, a second isolation layer on the first isolation layer and surrounding the second portion of the channel structure, and a gate structure on the second isolation layer and surrounding the third portion of the channel structure.
Inventor(s): Chun-Yuan CHEN of HsinChu (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Chieh SU of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/285, H01L21/8234, H01L27/088, H01L29/06, H01L29/08, H01L29/423, H01L29/45, H01L29/66, H01L29/775
CPC Code(s): H01L29/41733
Abstract: the present disclosure describes a semiconductor device having a contact structure isolated from a source/drain structure. the semiconductor structure includes a gate structure on a substrate, first and second source/drain (s/d) structures on opposite sides of the gate structure, an isolation layer on the second s/d structure, a third s/d structure adjacent to and separate from the second s/d structure, and a s/d contact structure on the isolation layer and the third s/d structure. the isolation layer separates the s/d contact structure from the second s/d structure.
Inventor(s): Cheng-Ting CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Bo LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jin CAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a semiconductor structure includes a substrate, a first device unit and a second device unit. the substrate includes a first region and a second region. the first device unit is disposed on the first region, and includes a plurality of first channel portions and two first source/drain portions. the second device unit is disposed on the second region, and includes a lower device and an upper device. the lower device is disposed on the second region, and includes at least one lower channel portion and two lower source/drain portions. the upper device is disposed above and spaced apart from the lower device, and includes at least one upper channel portion and two upper source/drain portions. a number of the first channel portions is greater than a number of the at least one lower channel portion and greater than a number of the at least one upper channel portion.
Inventor(s): Che-Chun Lu of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Guan-Lun Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsing Chu of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Yi Tseng of Tainan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/306, H01L29/06, H01L29/10, H01L29/423, H01L29/775
CPC Code(s): H01L29/66439
Abstract: a dummy gate structure is formed over a plurality of active regions. the dummy gate structure extends in a first horizontal direction in a planar top view. the active regions each extend in a second horizontal direction in the planar top view. the second horizontal direction is different from the first horizontal direction. a plurality of source/drain components is formed over the active regions. a dielectric structure is formed over the source/drain components. the dummy gate structure is then removed. a removal of the dummy gate structure exposes a first segment of each of the active regions. a thickness of the first segment of each of the active regions is reduced in the first horizontal direction.
Inventor(s): Chia-Min YU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chii-Horng LI of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Hsueh-Chang SUNG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/306, H01L21/308, H01L29/06, H01L29/423, H01L29/775
CPC Code(s): H01L29/66439
Abstract: methods of forming and a semiconductor devices where the channel region includes a germanium-comprising layer; and a crystalline silicon layer on the germanium-comprising layer. a gate structure over a first surface and a second surface, the second surface opposing the first surface. in some implementations, the crystalline silicon layer can mitigate damage during processing.
Inventor(s): Wei-Chih KAO of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Che Chiang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Lin Chiang of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Wei Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/66795
Abstract: a method for forming a semiconductor structure is provided. the method includes forming a first active region and a second active region, forming a first n-type work function layer and a first p-type work function layer along the first active region and the second active region, respectively, forming a semiconductor material along the first n-type work function layer and the first p-type work function layer, removing a first portion of the semiconductor material along the first p-type work function layer, thereby leaving a second portion of the semiconductor material as a first protection layer over the first n-type work function layer, and diffusing a dopant into the first p-type work function layer to form a doped p-type work function layer while the first protection layer blocks the dopant from diffusing into the first n-type work function layer.
Inventor(s): Sheng-Fu HSU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Fan CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Yi LEE of Keelung City (TW) for taiwan semiconductor manufacturing co., ltd., Pin-Chen CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/735, H01L27/02, H01L29/06, H01L29/40, H01L29/66, H03K17/081
CPC Code(s): H01L29/735
Abstract: a semiconductor device may include a electrostatic discharge (esd) protection circuit and a high voltage esd triggering circuit that is configured to trigger esd protection for high voltage circuits of the semiconductor device. the high voltage esd triggering circuit may be implemented by one or more of the example implementations of high voltage esd triggering circuits described herein. the example implementations of high voltage esd triggering circuits described herein are capable of handle high voltages of the high voltage circuits included in the semiconductor device. this reduces the likelihood of and/or prevents premature triggering of esd protection during normal operation for these high voltage circuits, and enables the high voltage circuits to be protected from high voltage esd events.
Inventor(s): Kang Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Deng-Ming Juo of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Wan-Chun Pan of Hsinch (TW) for taiwan semiconductor manufacturing co., ltd., Shich-Chang Suen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/775, H01L21/02, H01L21/3105, H01L29/06, H01L29/423, H01L29/66
CPC Code(s): H01L29/775
Abstract: provided are semiconductor devices and methods for fabricating such devices. an exemplary method includes forming fin structures separated by an isolation material; depositing a high-k material over the fin structures and isolation material, wherein the high-k material includes lower portions located between fin structures and an upper portion located above the fin structures; depositing a topography-improving capping layer over the high-k material; performing a chemical mechanical planarization (cmp) process to remove the capping layer and the upper portion of the high-k material and to define high-k insulation segments.
Inventor(s): Yu-Cheng Shiau of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Ting Ko of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Ting-Hsiang Chang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shu Ling Liao of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Sung-En Lin of Xionglin Township (TW) for taiwan semiconductor manufacturing co., ltd., Tai-Chun Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/775, H01L21/02, H01L21/306, H01L27/088, H01L29/06, H01L29/417, H01L29/423, H01L29/786
CPC Code(s): H01L29/775
Abstract: a method includes etching a semiconductor region aside of a gate stack to form a recess, forming a dielectric layer at a bottom of the recess, selectively forming a first semiconductor layer at the bottom of the recess, and epitaxially growing a second semiconductor layer on the first semiconductor layer. a bottom surface of the first semiconductor layer forms an interface with a top surface of the dielectric layer, with the interface extending to opposing sides of the recess. the selectively forming the first semiconductor layer comprises a first deposition process performed under first process conditions. the second semiconductor layer is formed using a second deposition process under second process conditions. the second process conditions are different from the first process conditions.
Inventor(s): Hsiao Po-Kai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Ting Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Pei Tsang Ho of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yang Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L29/66
CPC Code(s): H01L29/7851
Abstract: a semiconductor device includes a semiconductor fin. the semiconductor device includes a first silicon oxide layer contacting the semiconductor fin at a first interface and including nitrogen at a first concentration. the semiconductor device includes a second silicon oxide layer contacting the first silicon oxide layer at a second interface and including nitrogen at a second concentration that is greater than the first concentration. and the semiconductor device further includes a gate electrode over the second silicon oxide layer
Inventor(s): Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Guan-Lin Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Shi Ning Ju of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Chien Cheng of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/786, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/78642
Abstract: a vertically protruding structure is formed. the vertically protruding structure includes a substrate, a first semiconductor layer disposed over the substrate, a channel layer disposed over the first semiconductor layer, and a second semiconductor layer disposed over the channel layer. the first semiconductor layer and the second semiconductor layer each contain a first type of semiconductive material. the channel layer contains a second type of semiconductive material different from the first type. first recesses are formed in the first semiconductor layer and the second semiconductor layer. each of the first recesses protrudes laterally inward. the first recesses are filled with dielectric spacers. the channel layer and the substrate are laterally trimmed. the remaining portions of the channel layer and the dielectric spacers define second recesses that protrude laterally inward. gate structures are formed in the second recesses.
Inventor(s): Hidehiro Fujiwara of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu Jung Li of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yueh Chiang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Chang Zhao of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsin Nien of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kinshuk Khare of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K3/037
CPC Code(s): H03K3/037
Abstract: a circuit includes a first dual interlocked storage cell (dice) component, a second dice component, a third dice component, and a fourth dice component operatively coupled to one another as a loop. the first and second dice components form a first sub-latch configured to receive an input signal, the third and fourth dice components form a second sub-latch configured to receive the same input signal, the first sub-latch is configured to provide, at a first node, an intermediate signal based on the input signal, and the second sub-latch is configured to provide, at a second node, the same intermediate signal based on the input signal. the circuit includes a first inverter configured to logically invert the intermediate signal and provide, at a third node, an output signal. the circuit includes a second inverter configured to logically invert the intermediate signal and provide, at the third node, the output signal.
20240431089. MEMORY DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: a memory device includes a static random access memory (sram) cell including a first inverter and a second inverter. the first inverter has a first pull-down transistor and a first pull-up transistor. the second inverter has a second pull-down transistor and a second pull-up transistor. the first inverter and the second inverter are cross-coupled to each other. each of the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, and the second pull-up transistor includes active channel layers vertically stacked. a number of the active channel layers of the first pull-up transistor is less than a number of the active channel layers of the first pull-down transistor or the second pull-down transistor.
20240431116. FEFET DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Kuo-Chang Chiang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Ting Lin of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Chuan Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B51/30, H01L29/51, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H10B51/30
Abstract: the present disclosure relates a ferroelectric field-effect transistor (fefet) device. the fefet device includes a ferroelectric structure having a first side and a second side. a gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. the oxide semiconductor has a first semiconductor type. a source region and a drain region are disposed on the oxide semiconductor. the gate structure is laterally between the source region and the drain region. a polarization enhancement structure is arranged on the oxide semiconductor between the source region and the drain region. the polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type that is different than the first semiconductor type.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on December 26th, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- G02B6/122
- G02B6/136
- CPC G02B6/122
- Taiwan semiconductor manufacturing co., ltd.
- G06F3/06
- CPC G06F3/0604
- G11C13/00
- G11C11/16
- CPC G11C13/003
- H01J37/34
- C23C14/34
- C23C14/54
- CPC H01J37/3479
- H01L21/027
- G03F7/16
- G03F7/38
- H01L21/033
- H01L21/308
- CPC H01L21/0274
- H01L21/3213
- H01L21/02
- H01L21/28
- H01L29/66
- CPC H01L21/32136
- H01L21/67
- CPC H01L21/67017
- H01L21/768
- H01L21/311
- H01L23/522
- H01L23/528
- H01L23/532
- CPC H01L21/76814
- H01L21/78
- H01L21/66
- CPC H01L21/78
- H01L21/8234
- H01L27/088
- H01L29/06
- H01L29/423
- H01L29/45
- H01L29/775
- CPC H01L21/823475
- H01L23/48
- H01L23/498
- H01L25/065
- CPC H01L23/481
- H01L21/60
- H01L23/00
- CPC H01L23/49811
- CPC H01L23/5223
- H01L21/8238
- H01L27/092
- H01L29/417
- CPC H01L23/5286
- H01L27/146
- CPC H01L27/14627
- CPC H01L27/1463
- CPC H01L27/14636
- H01L29/786
- CPC H01L29/0673
- H01L29/10
- H01L29/78
- CPC H01L29/1037
- H01L21/285
- H01L29/08
- CPC H01L29/41733
- CPC H01L29/42392
- H01L21/306
- CPC H01L29/66439
- CPC H01L29/66795
- H01L29/735
- H01L27/02
- H01L29/40
- H03K17/081
- CPC H01L29/735
- H01L21/3105
- CPC H01L29/775
- CPC H01L29/7851
- CPC H01L29/78642
- H03K3/037
- CPC H03K3/037
- H10B10/00
- CPC H10B10/125
- H10B51/30
- H01L29/51
- CPC H10B51/30