Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on December 19th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on December 19th, 2024
Taiwan Semiconductor Manufacturing Co., Ltd.: 30 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L29/66 (8), H01L29/423 (7), H01L29/06 (6), H01L23/00 (6), H01L29/417 (4) H01L29/42392 (2), H01L23/5223 (2), H01L29/0673 (2), G03F7/0042 (1), H01L29/0665 (1)
With keywords such as: structure, layer, semiconductor, substrate, device, gate, direction, forming, portion, and metal in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): An-Ren ZI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Yu KUO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chin-Hsiang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/004, G03F7/075, G03F7/16, G03F7/20, G03F7/32, G03F7/38
CPC Code(s): G03F7/0042
Abstract: a method for forming a semiconductor device is provided. the method includes forming a photoresist layer comprising an organometallic compound over a substrate. the organometallic compound includes a metal core, at least one hydrolyzable ligand bonded to the metal core, and at least one photoacid generator ligand bonded to the metal core. the method further includes selectively exposing the photoresist layer to radiation and developing the photoresist layer to form a pattern in the photoresist layer.
Inventor(s): Ming-Hsin CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Zi-Wen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi YANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yao-Tang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jian-Yuan SU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/20, H01L21/027
CPC Code(s): G03F7/70033
Abstract: a method includes: protecting a mask of a mask assembly by a frame thereon during translating the mask assembly to a position associated with a region of a substrate, the frame having height less than a focal plane associated with a selected particle size; directing extreme ultraviolet (euv) radiation toward the mask; reflecting radiation carrying a pattern of the mask toward the mask layer; forming a feature of a semiconductor device in a layer underlying the mask layer according to the pattern.
Inventor(s): Kea Tiong TANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Pei LEE of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06N3/049, G06N3/048
CPC Code(s): G06N3/049
Abstract: a method is provided and includes operations as below: receiving an input in an input layer of a spiking neural network during time steps, wherein the input includes multiple spikes; generating, based on multiple activation values corresponding to the spikes, location information including count numbers each corresponding to non-zero values, in the activation values, in one of multiple rows of the input; performing, based on the location information, a matrix multiplication with the non-zero values in a first number of rows in the rows with a first group of filters of weight values to generate multiple first membrane potentials for outputting a first output spike; and performing, based on the location information, the matrix multiplication with the non-zero values in a second number of rows in the rows with the first group of filters of weight values to generate multiple second membrane potentials for outputting a second output spike.
20240420760. MEMORY DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Shih-Lien Linus LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/419, G11C5/14, G11C11/418
CPC Code(s): G11C11/419
Abstract: a memory device is provided. the memory device includes a cell array having a plurality of cells, each of the plurality of cells operative to store a bit value. the memory device further includes a reset circuit connected to the cell array. the reset circuit is operative to reset, in parallel, the bit value stored in each of the plurality of cells to a predetermined bit value.
Inventor(s): Jeng-Chi LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi-hsiang SHEN of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Te-Chien HOU of Kaohsiung (TW) for taiwan semiconductor manufacturing co., ltd., Tang-Kuei CHANG of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Jen LIU of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Chi HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kei-Wei CHEN of Tainan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/673, H01L21/306, H01L21/321, H01L21/67
CPC Code(s): H01L21/67369
Abstract: provided is a chemical-mechanical polishing apparatus, a retaining ring for a chemical-mechanical polishing apparatus, and a chemical-mechanical polishing method. a chemical-mechanical polishing apparatus includes a polishing pad; a polishing head configured to receive a wafer and to hold the wafer against the polishing pad; and a retaining ring configured to engage with the polishing head, wherein the retaining ring is formed with channels configured for flowing a slurry in a flow direction from outside the retaining ring to inside the retaining ring, wherein the channels have a cross-sectional flow area that decreases in the flow direction.
Inventor(s): Li-Ling SU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Hsien LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Ping CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shao-Kuan LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chin LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ju WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Yen HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsi-Wen TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Wei LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Chen LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/522
CPC Code(s): H01L21/76828
Abstract: a semiconductor device includes a substrate, a heat dissipation dielectric layer, a conductive interconnect structure, and a blocking dielectric layer. the heat dissipation dielectric layer is disposed on the substrate and has a thermal conductivity greater than 10 w/mk. the conductive interconnect structure is disposed in the heat dissipation dielectric layer. the blocking dielectric layer is disposed in the heat dissipation dielectric layer to isolate the conductive interconnect structure from the heat dissipation dielectric layer.
Inventor(s): Wei-Hao Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ying Tsung Chen of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8238, H01L27/092
CPC Code(s): H01L21/823878
Abstract: in an embodiment, a method includes: forming a plurality of fins over a substrate, the plurality of fins comprising: a first semiconductor fin adjacent to an isolation region; and a dielectric fin embedded in the isolation region; depositing a silicon layer over a first surface of the first semiconductor fin, a second surface of the dielectric fin, and a third surface of the isolation region; forming an oxide layer over the silicon layer; removing a portion of the oxide layer and the silicon layer to expose the second surface of the dielectric fin; forming a dummy gate over a remaining portion of the oxide layer and between the plurality of fins; forming a first epitaxial region in the first semiconductor fin; and replacing the dummy gate with a gate structure.
Inventor(s): Yun-Feng KAO of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Katherine H. CHIANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, G11C13/00, H01L23/528, H10B12/00, H10B20/25, H10B63/00, H10B80/00
CPC Code(s): H01L23/481
Abstract: a semiconductor device may include a non-volatile memory structure that may be formed in a back end of line (beol) region of a semiconductor device. the non-volatile memory structure may include a dielectric-based one-time programmable (otp) anti-fuse memory structure or a dielectric-based resistive random access memory (reram), among other examples. the non-volatile memory structure may be selectively programmed based on modifying an electrical resistance of the non-volatile memory structure, and may retain data stored in the non-volatile memory structure even when electrical power is removed from the semiconductor device.
Inventor(s): Tsung-Chieh Hsiao of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Yun Wan of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Liang-Wei Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/50, H01L23/00, H01L25/00, H01L25/18, H10B80/00
CPC Code(s): H01L23/50
Abstract: one aspect of the present disclosure pertains to a method. the method includes receiving a first circuit structure having semiconductor devices, an interconnect structure, first feedthrough vias, top metal lines, redistribution vias, and bond pads. the method includes dicing the first circuit structure to form a top die having a top semiconductor device. the method includes forming a stacked integrated circuit (ic) structure by bonding the top die to a second circuit structure, the second circuit structure having second semiconductor devices, a second interconnect structure, second redistribution vias, and second bond pads. the method includes forming ic top metal lines over the first feedthrough vias, forming an ic passivation layer over the ic top metal lines, forming metal-insulator-metal (mim) capacitor structures in the ic passivation layer, and forming ic redistribution vias penetrating through the mim capacitor structures and the ic passivation layer to land on the ic top metal lines.
Inventor(s): Chia-Yueh CHOU of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Tzu CHEN of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Ling CHANG of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Hsiang-Ku SHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Alvin Universe TANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Hsiu CHIANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Hung TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kun-Yu LEE of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Hao HOU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Dian-Hau CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Chung YU of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01G4/08, H01L23/00
CPC Code(s): H01L23/5223
Abstract: a method and semiconductor device including a substrate having one or more semiconductor devices. in some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices, and a metal-insulator-metal (mim) capacitor structure formed over the first passivation layer. in some embodiments, the mim capacitor structure includes a first conductor plate layer, an insulator layer on the first conductor plate layer, and a second conductor plate layer on the insulator layer. in some examples, the insulator layer includes a metal oxide sandwich structure.
Inventor(s): Chung-Liang CHENG of Changhua City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chau CHEN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/532
CPC Code(s): H01L23/5223
Abstract: forming a barrier layer and removing the barrier layer from an upper portion of a recess in which a metal-insulator-metal (mim) structure will be formed allows for forming the mim structure with fewer voids, which improves capacitance of the mim structure. for example, a bottom layer anti-reflective coating may be deposited and etched back in order to allow for removal of the barrier layer from the upper portion of the recess but not from a bottom portion of the recess. additionally, the barrier layer may be formed using physical vapor deposition, which reduces carbon impurities in the barrier layer as compared with using atomic layer deposition, which improves resistance for the mim structure.
Inventor(s): Hung-Pin Chang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Cheng Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Der-Chyang Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L21/768, H01L23/00, H01L23/58, H01L25/065
CPC Code(s): H01L23/528
Abstract: a package device for 3d stacking of integrated circuits includes a semiconductor substrate, and an interconnect structure on the semiconductor substrate. the interconnect structure is organized into a plurality of device regions, and the device has a first seal ring extending vertically through the interconnect structure in a first device region, and a second seal ring extending vertically through the interconnect structure in a second device region. the interconnect structure also includes a conductive line electrically connecting a metallization pattern within the first seal ring to a second metallization pattern within the second seal ring, wherein the first horizontally extending conductive line extends through the first seal ring and the second seal ring.
Inventor(s): Chih-Hung Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Ching Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsiu Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/528, H01L25/00, H01L25/18, H10B80/00
CPC Code(s): H01L23/5386
Abstract: a semiconductor device includes a bridge carrier, a first die, a second die, a first encapsulant, a cap carrier, a third die, and a second encapsulant. the bridge carrier includes a carrier substrate and a bridge redistribution structure disposed on the carrier substrate. the first die and the second die are disposed side by side on the bridge carrier. the bridge redistribution structure electrically connects the first die and the second die. the first encapsulant laterally encapsulates the first die and the second die. the cap carrier is disposed over the first die and the second die. the third die is located between the first die and the cap carrier. the second encapsulant laterally encapsulates the third die.
Inventor(s): Hung-Pin Chang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Cheng Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Der-Chyang Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/08
Abstract: a package device includes a top die having a top interconnect structure on a first surface of a transistor layer and a bottom interconnect structure on a second surface of the transistor layer. one of the top interconnect structure or the bottom interconnect structure is direct bonded onto a bottom die. the bottom interconnect structure includes a power rail which directly contacts transistor contacts that are directly contacting a transistor structure in the transistor layer.
Inventor(s): Feng-Chien Hsieh of Pingtung County (TW) for taiwan semiconductor manufacturing co., ltd., Yun-Wei Cheng of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Li Hu of Tainan city (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng Lee of Tainan city (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Ming Wu of Tainan city (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14636
Abstract: an image sensor device and methods of forming the same are described. in some embodiments, the device includes a substrate, a contact pad structure extending from a contact pad region to a black level correction region, a dielectric layer disposed over the substrate in the black level correction region, and a light blocking structure disposed on and through the dielectric layer in the black level correction region. a first portion of the contact pad structure disposed in the black level correction region is in contact with the light blocking structure, and the light blocking structure is in contact with the substrate.
Inventor(s): Shuang-Ji Tsai of Guiren Township (TW) for taiwan semiconductor manufacturing co., ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-De Wang of Minsyong Township (TW) for taiwan semiconductor manufacturing co., ltd., Hsiao-Hui Tseng of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146, H01L23/00, H01L23/48, H01L23/525
CPC Code(s): H01L27/14687
Abstract: provided is a method of fabricating an image sensor device. an exemplary includes forming a plurality of radiation-sensing regions in a substrate. the substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. the exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.
Inventor(s): Kuan-Ting PAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shi-Ning JU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Ruei JHAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ming CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/0665
Abstract: a device includes a substrate, a first semiconductor fin over the substrate extending in a first lateral direction, a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction, and an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction. a first gate structure surrounds and covers the first semiconductor fin, and extends in a second lateral direction substantially perpendicular to the first lateral direction. a second gate structure surrounds and covers the first vertical stack, and extends in the second lateral direction.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Hsun Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a semiconductor device and a manufacturing method thereof are provided. the semiconductor device includes semiconductor nanosheets vertically stacked upon one another and disposed above a semiconductor substrate, a gate structure surrounding each of the semiconductor nanosheets, and source/drain regions disposed over the semiconductor substrate and laterally abutting the semiconductor nanosheets. the semiconductor nanosheets serve as channel regions, and a topmost semiconductor nanosheet most distanced from the semiconductor substrate is thinner than an underlying semiconductor nanosheet between the topmost semiconductor nanosheet and the semiconductor substrate.
Inventor(s): Yi Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Yu LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L23/48, H01L27/088, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a semiconductor device (having a vfet architecture) includes: first and second active regions (ars); first and second metal-to-gate (mg) contacts proximal to channel regions of the first and second ars; metal-to-source/drain (md) contacts and buried md (bmd) contacts correspondingly coupled to first and second s/d regions correspondingly of the first and second ars; and a metal-to-gate (mp) contact at a same level as the mg contacts, and extending between and coupling together the first and second mg contacts; and relative to a first direction, the first and second ars being substantially aligned; and at least a portion of the mp contact extending substantially beyond each of the first and second ars relative to a perpendicular second direction.
Inventor(s): Yi-An LAI of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Pan Chieh Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hua WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chan-Hong CHERN of Palo Alto CA (US) for taiwan semiconductor manufacturing co., ltd., Cheng-Hsiang HSIEH of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/20, H01L29/40, H01L29/66, H01L29/778
CPC Code(s): H01L29/2003
Abstract: the present disclosure describes a semiconductor device having artificial field plates. the semiconductor device includes a first gallium nitride (gan) layer on a substrate, an aluminum gallium nitride (algan) layer on the first gan layer, and a second gan layer on the algan layer. the first and second gan layers includes different types of dopants. the semiconductor device further includes a gate contact structure in contact with the second gan layer, first and second source/drain (s/d) contact structures in contact with the algan layer, one or more artificial field plates between the gate contact structure and the first s/d contact structure. the first and second s/d contact structures are disposed at opposite sides of the gate contact structure. the one or more artificial field plates are separated from the first and second s/d contact structures and above the algan layer.
Inventor(s): Ta-Chun Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L27/088, H01L29/423
CPC Code(s): H01L29/41725
Abstract: semiconductor structures and methods of forming the same are provided. in an embodiment, an exemplary semiconductor structure includes a source/drain feature over a substrate; a metal gate structure extending lengthwise along a first direction and adjacent to the source/drain feature; a gate isolation structure extending lengthwise along a second direction substantially perpendicular to the first direction, and a source/drain contact electrically coupled to the source/drain feature and including a first portion directly above the source/drain feature and a second portion extending from the first portion along the first direction. in embodiments, the gate isolation structure divides the metal gate structure into two isolated portions. in embodiments, the first portion has a first width along the second direction and the second portion has a second width along the second direction, the first width being greater than the second width.
Inventor(s): Chia-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., I-Wen Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Ming Lee of Taoyuan County (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Cheng Syu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L27/088, H01L29/06, H01L29/423
CPC Code(s): H01L29/41766
Abstract: one aspect of the present disclosure pertains to a semiconductor structure. the semiconductor structure includes first and second active regions extending lengthwise along a first direction and metal gate structures extending lengthwise along a second direction over channels of the first and second active regions. the semiconductor structure includes an insulating structure cutting through the metal gate structures. the insulating structure is disposed between the first and the second active regions along the second direction. the semiconductor structure includes source/drain (s/d) contacts over the insulating structure and over s/d features of the first and second active regions. the s/d contacts extend lengthwise along the second direction. and the semiconductor structure includes a feedthrough via contacting a bottom surface of the s/d contacts and penetrating through a portion of the insulating structure. the insulating structure surrounds the feedthrough via and isolates the feedthrough via from the metal gate structures.
Inventor(s): Hung-Ju Chou of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Chung Chang of Nantou County (TW) for taiwan semiconductor manufacturing co., ltd., Yao-Hsuan Lai of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L29/06, H01L29/66, H01L29/775
CPC Code(s): H01L29/42392
Abstract: a method of forming a semiconductor structure includes depositing a dummy material stack over a fin, patterning a top portion of the dummy material stack in a first etching process, patterning a middle portion of the dummy material stack in a second etching process, patterning a bottom portion of the dummy material stack in a third etching process to form a dummy gate stack, and replacing the dummy gate stack with a metal gate stack. the second etching process is weaker than the first etching process, and the third etching process is weaker than the second etching process.
Inventor(s): Ta-Chun Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/306, H01L29/06, H01L29/417, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a method for fabricating a semiconductor device is disclosed. the method includes forming, over a substrate, a stack extending along a first lateral direction, wherein the stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately arranged on top of one another; overlaying a first portion of the stack with a first gate structure, wherein the first gate structure extends along a second lateral direction perpendicular to the first lateral direction; removing a second portion of the stack through a first etching process, wherein the second portion was disposed next to the first portion along the first lateral direction; and removing a third portion of the stack through a second etching process, wherein the third portion was disposed next to a lower part of the second portion.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Uei Jang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ya-Yi Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Yuan Ku of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088
CPC Code(s): H01L29/66545
Abstract: a method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. a planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. the dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. the method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.
20240421228. NOISE TRANSISTOR_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Che-Chun Lu of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsing Chu of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Yi Tseng of Tainan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L29/10, H01L29/165, H01L29/66
CPC Code(s): H01L29/7848
Abstract: noise semiconductor devices and methods of forming the same are provided. a semiconductor device according to the present disclosure includes a substrate, a fin structure over the substrate and extending lengthwise along a direction, the fin structure including a middle section sandwiched between a first end section and a second section along the direction, a gate structure wrapping over a channel region of the middle section, and a first source/drain feature and a second source/drain feature sandwiching the channel region of the middle section along the direction, the middle section includes a first semiconductor material and the first end section and the second end section include a second semiconductor material different from the first semiconductor material.
Inventor(s): MARTIN KINYUA of Cedar Park TX (US) for taiwan semiconductor manufacturing co., ltd., ERIC SOENEN of Austin TX (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03F3/217, H03F1/02, H03F3/185, H03M3/00
CPC Code(s): H03F3/2175
Abstract: an amplifier includes an input circuit configured to receive an analog input signal and a feedback signal, and output an analog error signal based on the analog input signal and the feedback signal. an adc is configured to convert the analog error signal into a digital signal in a phase domain. a digital control circuit is configured to generate a digital control signal based on the digital signal in the phase domain. an output circuit is configured to generate an amplified output signal based on the digital control signal, and a feedback circuit is configured generate the feedback signal based on the amplified output signal.
Inventor(s): Chien-Hsing Lu of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Chiang Tu of Tauyen (TW) for taiwan semiconductor manufacturing co., ltd., Fei-Gwo Tsai of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Wei Wen of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Fu Tseng of Zhubei (TW) for taiwan semiconductor manufacturing co., ltd., Tzu Jeng Hsu of Taoyuan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H05G2/00, G03F7/00
CPC Code(s): H05G2/008
Abstract: a laser produced plasma (lpp)-extreme ultraviolet (euv) light source includes a vacuum chamber, a rotatable crucible disposed in the vacuum chamber with an annular inner surface for carrying a liquid metal, and a laser arranged to apply laser light to the liquid metal carried on the annular inner surface of the rotatable crucible to cause the liquid metal to emit euv light. the lpp-euv light source further includes a stationary component disposed in the vacuum chamber and positioned proximate to the annular inner surface of the rotatable crucible or surrounding the rotatable crucible, a coolant fluid delivery inlet or nozzle, and a cooling element secured with the stationary component and including a feature configured to operatively couple with coolant fluid delivered by the coolant fluid delivery inlet or nozzle.
Inventor(s): Sheng-Chen Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Han-Jong Chia of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B51/20, H10B43/27, H10B51/30
CPC Code(s): H10B51/20
Abstract: a memory device includes a substrate, a first stacking structure, a second stacking structure, struts, an isolation structure, memory films, channel layers, and conductive pillars. the first stacking structure includes first gate layers and is located on the substrate. the second stacking structure includes second gate layers and is located on the substrate, where the second stacking structure is separated from the first stacking structure through a trench. the struts stand on the substrate and are located in the trench, where the struts each have two opposite surfaces respectively in contact with the first stacking structure and the second stacking structure. the isolation structure stands on the substrate and is located in the trench, where cell regions are located in the trenches, and at least two of the cell regions are separated from one another through a respective one strut and the isolation structure connected therewith. the memory films are respectively located in the cell regions, and the memory films each cover a sidewall of a respective one of the cell regions. the channel layers respectively cover an inner surface of a respective one of the memory films, where the memory films are sandwiched between the first gate layers and the channel layers. the conductive pillars stand on the substrate within the cell regions and are covered by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars are laterally separated from one another.
Inventor(s): Hsin-Yuan CHIU of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Ang CHAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Gregory Michael PITNER of Sunnyvale CA (US) for taiwan semiconductor manufacturing co., ltd., Matthias PASSLACK of Hayward CA (US) for taiwan semiconductor manufacturing co., ltd., Chao-Hsin CHIEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Han WANG of San Jose CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10K10/84, H10K10/46
CPC Code(s): H10K10/84
Abstract: a device includes a carbon nanotube having a channel region and dopant-free source/drain regions at opposite sides of the channel region, a first metal oxide layer interfacing a first one of the dopant-free source/drain regions of the carbon nanotube, a second metal oxide layer interfacing a second one of the dopant-free source/drain regions of the carbon nanotube and a gate structure over the channel region of the carbon nanotube, and laterally between the first metal oxide layer and the second metal oxide layer.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on December 19th, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- G03F7/004
- G03F7/075
- G03F7/16
- G03F7/20
- G03F7/32
- G03F7/38
- CPC G03F7/0042
- Taiwan semiconductor manufacturing co., ltd.
- H01L21/027
- CPC G03F7/70033
- G06N3/049
- G06N3/048
- CPC G06N3/049
- G11C11/419
- G11C5/14
- G11C11/418
- CPC G11C11/419
- H01L21/673
- H01L21/306
- H01L21/321
- H01L21/67
- CPC H01L21/67369
- H01L21/768
- H01L23/522
- CPC H01L21/76828
- H01L21/8238
- H01L27/092
- CPC H01L21/823878
- H01L23/48
- G11C13/00
- H01L23/528
- H10B12/00
- H10B20/25
- H10B63/00
- H10B80/00
- CPC H01L23/481
- H01L23/50
- H01L23/00
- H01L25/00
- H01L25/18
- CPC H01L23/50
- H01G4/08
- CPC H01L23/5223
- H01L23/532
- H01L23/58
- H01L25/065
- CPC H01L23/528
- H01L23/538
- H01L21/48
- CPC H01L23/5386
- CPC H01L24/08
- H01L27/146
- CPC H01L27/14636
- H01L23/525
- CPC H01L27/14687
- H01L29/06
- H01L21/8234
- H01L29/423
- H01L29/66
- H01L29/786
- CPC H01L29/0665
- H01L29/08
- H01L29/775
- CPC H01L29/0673
- H01L27/088
- H01L29/417
- H01L29/20
- H01L29/40
- H01L29/778
- CPC H01L29/2003
- CPC H01L29/41725
- CPC H01L29/41766
- CPC H01L29/42392
- CPC H01L29/66545
- H01L29/78
- H01L29/10
- H01L29/165
- CPC H01L29/7848
- H03F3/217
- H03F1/02
- H03F3/185
- H03M3/00
- CPC H03F3/2175
- H05G2/00
- G03F7/00
- CPC H05G2/008
- H10B51/20
- H10B43/27
- H10B51/30
- CPC H10B51/20
- H10K10/84
- H10K10/46
- CPC H10K10/84