Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on April 3rd, 2025
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on April 3rd, 2025
Taiwan Semiconductor Manufacturing Co., Ltd.: 53 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L29/66 (20), H01L29/423 (17), H01L29/06 (15), H01L29/775 (13), H01L29/786 (11) H10D30/6735 (2), H10D1/042 (2), H10D64/017 (2), H10D62/121 (2), H10D30/031 (1)
With keywords such as: layer, structure, semiconductor, gate, forming, disposed, source, drain, dielectric, and substrate in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Chih-Ming TSAO of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Tzu-Sou CHUANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chwen YU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B08B15/00, B01D46/44, G05B15/02, G06V10/75, G06V20/00, H01J49/00, H01J49/40, H01L21/67, H01L21/677
CPC Code(s): B08B15/00
Abstract: a method includes: generating a contaminant distribution map by sampling an environment of a cleanroom; selecting a first fabrication tool of the cleanroom by comparing the contaminant distribution map with at least one diffusion image in a first database; comparing parameters of the first fabrication tool against process utility information in a second database; and when the parameters are consistent with the process utility information, taking at least one action. the one action may include moving a cleaning tool to a location associated with a contaminant concentration of the contaminant distribution map; turning on a fan of the cleaning tool; stopping pod transit to the first fabrication tool; or halting production by the first fabrication tool.
Inventor(s): Jin-Hao JHANG of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., James June Fan HSU of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Wei-Yen WOON of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B24B37/013, H01L21/306, H01L21/66
CPC Code(s): B24B37/013
Abstract: a method includes providing a wafer including a layer; performing a surface treatment to the layer; polishing the layer using a polishing pad; determining whether a surface roughness or a thickness of the layer reaches a pre-determined condition; and stopping polishing the layer when the surface roughness or the thickness of the layer reaches the pre-determined condition.
Inventor(s): Chia-Wei WU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hao YANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsiao-Chieh CHOU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chun-Hung CHAO of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jao Sheng HUANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Neng-Jye YANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuo-Bin HUANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): F24F9/00, H01L21/67, H01L21/687
CPC Code(s): F24F9/00
Abstract: the present disclosure is at least directed to utilizing air curtain devices to form air curtains to separate and isolate areas in which respective workpieces are stored from a transfer compartment within a workpiece processing apparatus. the transfer compartment of the workpiece processing apparatus includes a robot configured to transfer or transport ones of the workpieces to and from these respective storage areas through the transfer compartment and to and from a tool compartment. a tool is present in the tool compartment for processing and refining the respective workpieces. clean dry air (cda) may be circulated through the respective storage areas. the air curtains formed by the air curtain devices and the circulation of cda through the respective storage areas reduces the likelihood of the generation of defects, damages, and degradation of the workpieces when present within the workpiece processing apparatus.
20250110079. BioFET SYSTEM_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Yu-Jie Huang of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Jui-Cheng Huang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01N27/414, H03K19/185
CPC Code(s): G01N27/4145
Abstract: a bio-field effect transistor (biofet) system includes a biofet configured to receive to a first voltage signal and output a current signal, where the current signal varies exponentially with respect to the first voltage signal. a logarithmic current-to-time converter is connected to the biofet and is configured to receive the current signal and convert the current signal to a time domain signal. the time domain signal varies logarithmically with respect to the current signal, such that the time domain signal varies linearly with respect to the first voltage signal.
Inventor(s): Ming Da Yang of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Chun-Hsuan Lin of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Yi-Chen Li of Taichung City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01R29/12
CPC Code(s): G01R29/12
Abstract: an electrostatic field strength measuring apparatus includes an electrostatic field detection device and a processor. the electrostatic field detection device includes a ring light source configured to emit a light signal to a target object, and a reflection detector disposed within and surrounded by the ring light source and configured to receive a reflection signal, of the light signal, reflected by a surface of the target object and generate an electrical signal based upon the reflection signal. the processor is configured to determine, based upon the electrical signal, measures of electrostatic field strength at the surface of the target object.
Inventor(s): Ying-Chih Hsu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Jui-Cheng Huang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Mu Wei Lee of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Wei-Tao Shaw of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01R31/28
CPC Code(s): G01R31/2853
Abstract: a semiconductor package includes an array of through-substrate-via (tsv) structures comprising a number (o) of tsv structures, wherein the array comprises a number (m) of active tsv structures; a number (n) of contact structures, the contact structures comprising a plurality of pairs configured to receive an input test signal and provide an output test signal, respectively; and a plurality of binary-tree branches, each of the plurality of binary-tree branches electrically coupling a first one of the active tsv structures to a second one of the active tsv structures and a third one of the active tsv structures.
Inventor(s): Tai-Chun HUANG of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Stefan RUSU of Sunnyvale CA US for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/122, G02B6/13
CPC Code(s): G02B6/1228
Abstract: a semiconductor photonics device includes a multiple-layer coupler structure. the multiple-layer coupler structure includes a plurality of optical coupler layers, which enables the properties of the optical coupler layers to be configured to achieve efficient optical coupling for a broad spectrum of optical wavelengths. this enables the multiple-layer coupler structure to handle wide bandwidth optical signals, which enables the semiconductor photonics device to support high-bandwidth optical communication applications. moreover, the optical coupler layers of the multiple-layer coupler device enable the performance of the multiple-layer coupler structure to be increased using less complex and less costly semiconductor manufacturing processes and techniques. additionally, the optical coupler layers of the multiple-layer coupler structure enable the multiple-layer coupler structure to handle bidirectional transmission of optical signals, thereby enabling transmission of optical signals between various layers of the semiconductor photonics device.
Inventor(s): Sui-Ying HSU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yuehying LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chien-Ying WU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chen-Hao HUANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chien-Chang LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chia-Ping LAI of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/34, G02B6/30, G02B6/42
CPC Code(s): G02B6/34
Abstract: a coupling system includes a chip configured to receive an optical signal, wherein an angle between a propagation direction of the optical signal and a top surface of the chip ranges from about 92-degrees to about 88-degrees. the chip includes a grating configured to receive the optical signal; and a waveguide, wherein the grating is configured to receive the optical signal and redirect the optical signal along the waveguide, and the grating is on a light incident side of the waveguide.
Inventor(s): Chung-Ming Weng of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Yu-Hao Chen of HsinChu City TW for taiwan semiconductor manufacturing co., ltd., Hao-Yi Tsai of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., An-Jhih Su of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd., Tzuan-Horng Liu of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd., Po-Yuan Teng of Hsinchu city TW for taiwan semiconductor manufacturing co., ltd., Tsung-Yuan Yu of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Che-Hsiang Hsu of Taichung City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/42, H01L23/00, H01L23/48, H01L25/16, H01L25/18
CPC Code(s): G02B6/4206
Abstract: provided are a package structure and a method of forming the same. the package structure includes a bottom package having a first sidewall and a second sidewall opposite to each other; a hybrid path layer disposed on the bottom package, wherein the hybrid path layer comprises an optical path layer and an electrical path layer, and at least one optical path of the optical path layer extends from the first sidewall of the bottom package beyond a center of the bottom package; and a plurality of dies bonded onto the hybrid path layer.
Inventor(s): Stefan RUSU of Sunnyvale CA US for taiwan semiconductor manufacturing co., ltd., Wei-wei SONG of Sunnyvale CA US for taiwan semiconductor manufacturing co., ltd., Mohammed Rabiul ISLAM of Austin TX US for taiwan semiconductor manufacturing co., ltd., Chih-Tsung SHIH of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/43, G02B6/13, G02B6/42, H01L33/60, H01L33/64
CPC Code(s): G02B6/43
Abstract: disclosed are apparatus and methods for optical interconnections that include the integration of a photonics die (pdie) and an electronic die (edie) with a socket layer, waveguides and fiber connectors to enable high bandwidth communications. in one embodiment, an exemplary optical interconnect device includes an electronic die coupled to a photonics die and integrated with a substrate, a socket, a board, a pair of micro-lenses and a mirror coupled to a waveguide, which can be embedded in the board. in another embodiment, the waveguide is embedded in a socket layer and coupled to a fiber connector. in these embodiments, the exemplary optical interface device can be coupled one more other optical interconnect devices via a waveguide array and/or a fiber array.
Inventor(s): Che-Chang HSU of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Sheng-Kang YU of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Shang-Chieh CHIEN of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Li-Jui CHEN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Heng-Hsin LIU of New Taipei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/00, G03F1/62, G03F1/82
CPC Code(s): G03F7/70925
Abstract: some implementations described herein provide a reticle cleaning device and a method of use. the reticle cleaning device includes a support member configured for extension toward a reticle within an extreme ultraviolet lithography tool. the reticle cleaning device also includes a contact surface disposed at an end of the support member and configured to bond to particles contacted by the contact surface. the reticle cleaning device further includes a stress sensor configured to measure an amount of stress applied to the support member at the contact surface. during a cleaning operation in which the contact surface is moving toward the reticle, the stress sensor may provide an indication that the amount of stress applied to the support member satisfies a threshold. based on satisfying the threshold, movement of the contact surface and/or the support member toward the reticle ceases to avoid damaging the reticle.
Inventor(s): Cheng-Tse CHOU of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., King-Ho TAM of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/3312, G06F30/392, G06F113/18, G06F119/12
CPC Code(s): G06F30/3312
Abstract: a method includes accessing a layout of a first die, wherein the first die is of a three-dimensional integrated circuit (3dic) structure; generating a virtual design based on the layout of the first die, a first resistance and capacitance (rc) technology file (techfile) of the first die, and a second rc techfile of a second die, wherein the second die is of the 3dic structure; performing a virtual coupling capacitance extraction on the virtual design to form a virtual coupling capacitance netlist; performing an static timing analysis on the first die with the virtual coupling capacitance netlist.
Inventor(s): Hung-Chih Ou of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Yu-Sheng Lu of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Wen-Hao Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/398
CPC Code(s): G06F30/398
Abstract: a method for checking standard cell spacing in a design includes providing a first standard cell. a cell environment of the first standard cell is determined and a first feasible distance between a first boundary of the standard cell and a boundary of a first adjacent cell based on the cell environment is determined. a second feasible distance between a second boundary of the standard cell and a boundary of a second adjacent cell based on the cell environment is determined. a feasible spacing between the first standard cell and a second standard cell is provided, and the feasible spacing is evaluated based on the first feasible distance, the second feasible distance and a cell pitch of the first standard cell. an integrated circuit is fabricated that includes the first standard cell in response on the evaluating.
Inventor(s): Tung-Cheng Chang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yu-Fan Lin of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Ku-Feng Lin of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Perng-Fei Yuh of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yih Wang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/16
CPC Code(s): G11C11/1659
Abstract: a memory circuit includes a memory array comprising a plurality of non-volatile memory cells, wherein the non-volatile memory cells are arranged along a plurality of access lines that extend along a lateral direction. the memory circuit includes a first access circuit physically disposed on a first side of the memory array in the lateral direction. the memory circuit includes a second access circuit physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side. when each of the non-volatile memory cells is configured to be programmed by at least a first current and a second current, the first current and second current flow through a first path and a second path, respectively. the first path at least comprises a portion on the first side and the second path at least comprises a portion on the second side.
Inventor(s): Tsung-Jen YANG of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Yi-Zhen CHEN of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Chih-Pin WANG of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Chao-Li SHIH of Jhudong Township TW for taiwan semiconductor manufacturing co., ltd., Ching-Hou SU of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Cheng-Yi HUANG of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01J37/34, C23C14/35
CPC Code(s): H01J37/3408
Abstract: in an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.
Inventor(s): Chia-Cheng CHAO of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Hsin-Chieh HUANG of Taoyuan TW for taiwan semiconductor manufacturing co., ltd., Yu-Wen WANG of New Taipei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/306, H01L21/3105, H01L21/311, H01L29/06, H01L29/423
CPC Code(s): H01L21/30604
Abstract: implementations described herein provide a method of forming a semiconductor device. the method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. the method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. the method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. the method further includes removing a top portion of the cladding structure. the method further includes removing the second hard mask layer after removing the top portion of the cladding structure.
Inventor(s): Jin-Hao JHANG of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Wei-Yen WOON of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd., Szuya LIAO of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/306, C09G1/02, H01L21/02, H01L21/304, H01L21/321
CPC Code(s): H01L21/30625
Abstract: a method includes providing a wafer including a layer; projecting a beam for a surface treatment on the layer to form a material-modified portion at a top of the layer, wherein the material-modified portion is spaced apart from a bottom surface of the layer; and polishing, by using a polishing pad, the material-modified portion of the layer.
Inventor(s): Chien-Fa LEE of Hinchu City TW for taiwan semiconductor manufacturing co., ltd., Chin-Lin CHOU of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Shang-Ying TSAI of Pingzhen City TW for taiwan semiconductor manufacturing co., ltd., Shou-Wen KUO of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Kuei-Sung CHANG of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Jiun-Rong PAI of Jhubei City TW for taiwan semiconductor manufacturing co., ltd., Hsu-Shui LIU of Pingjhen City TW for taiwan semiconductor manufacturing co., ltd., Chun-wen CHENG of Zhubei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/683, B25B11/00
CPC Code(s): H01L21/6838
Abstract: disclosed is a vacuum chuck and a method for securing a warped semiconductor substrate during a semiconductor manufacturing process so as to improve its flatness during a semiconductor manufacturing process. for example, a semiconductor manufacturing system includes: a vacuum chuck configured to hold a substrate, wherein the vacuum chuck comprises, a plurality of vacuum grooves located on a top surface of the vacuum chuck, wherein the top surface is configured to face the substrate; and a plurality of flexible seal rings disposed on the vacuum chuck and extending outwardly from the top surface, wherein the plurality of flexible seal rings are configured to directly contact a bottom surface of the substrate and in adjacent to the plurality of vacuum grooves so as to form a vacuum seal between the substrate and the vacuum chuck, and wherein each of the plurality of flexible seal rings has a zigzag cross section.
Inventor(s): Hwei-Jay CHU of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Hsi-Wen TIEN of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Wei-Hao LIAO of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Yu-Teng DAI of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Hsin-Chieh YAO of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Tzu-Hui WEI of Zhubei City TW for taiwan semiconductor manufacturing co., ltd., Chih Wei LU of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chan-Yu LIAO of Yunlin County TW for taiwan semiconductor manufacturing co., ltd., Li-Ling SU of Taichung County TW for taiwan semiconductor manufacturing co., ltd., Chia-Wei SU of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd., Yung-Hsu WU of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Hsin-Ping CHEN of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/528
CPC Code(s): H01L21/76802
Abstract: a method for fabricating an integrated circuit device is provided. the method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.
Inventor(s): Cheng-Chin LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yen Ju WU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shao-Kuan LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuang-Wei YANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsin-Yen HUANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jing Ting SU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kai-Fang CHENG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsiao-Kang CHANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wei-Chen CHU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shu-Yun KU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chia-Tien WU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ming-Han LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsin-Ping CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L21/76832
Abstract: a semiconductor structure is provided. the semiconductor structure includes a first low dielectric constant (low-k) layer, a first metal layer, a metal cap layer, a dielectric on dielectric (dod) layer, an etch stop layer (esl), a second low-k layer, a metal via and a second metal layer. the dielectric constant of the first low-k layer is less than 4. the first metal layer is embodied in the first low-k layer. the first low-k layer exposes the first metal layer. the metal cap layer is disposed on the first metal layer. the dod layer is disposed on the first low-k layer. the etch stop layer is disposed on the metal cap layer and the dod layer. the second low-k layer is disposed above the etch stop layer. the metal via is embodied in the second low-k layer and connected to the first metal layer.
Inventor(s): Shu-Wei Li of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shin-Yi Yang of New Taipei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/532
CPC Code(s): H01L21/76843
Abstract: a structure including a conductive region, a dielectric region, and a capping layer is provided. the conductive region is disposed on or embedded in the dielectric region. the capping layer is disposed on the conductive region. a material of the capping layer includes a 2d material.
Inventor(s): Su-Jen Sung of Zhubei City TW for taiwan semiconductor manufacturing co., ltd., Jr-Hung Li of Chupei City TW for taiwan semiconductor manufacturing co., ltd., Tze-Liang Lee of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/29, H01L23/538, H01L25/10
CPC Code(s): H01L23/3185
Abstract: a method includes bonding a first wafer to a second wafer, performing a trimming process on the first wafer, and depositing a sidewall protection layer contacting a sidewall of the first wafer. the depositing the sidewall protection layer includes depositing a high-density material in contact with the sidewall of the first wafer. the sidewall protection layer has a density higher than a density of silicon oxide. the method further includes removing a horizontal portion of the sidewall protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. the interconnect structure is electrically connected to integrated circuit devices in the first wafer.
Inventor(s): Shih-Wei Liu of Chiayi TW for taiwan semiconductor manufacturing co., ltd., Po-Yao Lin of Zhudong Township TW for taiwan semiconductor manufacturing co., ltd., Sing-Da Jiang of Taichung TW for taiwan semiconductor manufacturing co., ltd., Tsunyen Wu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kathy Wei Yan of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/373, H01L25/065
CPC Code(s): H01L23/49822
Abstract: a method of manufacturing a device includes bonding a first die and a second die to a first side of a substrate, forming a stress buffer structure over the first die and the second die, where the stress buffer structure includes a first portion of a first via extending through a first insulating layer, a second portion of the first via extending through a second insulating layer, and a third portion of the first via extending through a third insulating layer, where the second portion of the first via is disposed between the first portion of the first via and the third portion of the first via, and where a diameter of the second portion of the first via is smaller than diameters of the first portion of the first via and the third portion of the first via, and depositing a metal layer over the stress buffer structure.
Inventor(s): Chi-Han Yang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/70, H01L21/768, H01L27/01
CPC Code(s): H01L23/5226
Abstract: a semiconductor device includes a capacitor and a resistor. the capacitor includes a first plate, a capacitor dielectric layer disposed over the first plate, and a second plate disposed over the capacitor dielectric layer. the resistor includes a thin film. the thin film of the resistor and the first plate of the capacitor, formed of a same conductive material, are defined in a single patterning process.
Inventor(s): Hsin-Cheng LIN of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Kuan-Ying CHIU of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd., Chee-Wee LIU of Taipei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L23/5286
Abstract: a device includes a first transistor, a second transistor, an interlayer dielectric (ild) layer, and a backside gate rail. the first and second transistors are arranged along a first direction in a top view. the first transistor includes a first channel layer, a gate structure surrounding the first channel layer, a first source/drain epitaxial structure and a second source/drain epitaxial structure connected to the first channel layer. the second transistor includes a second channel layer, the gate structure surrounding the second channel layer, a third source/drain epitaxial structure and a fourth source/drain epitaxial structure connected to the second channel layer. a portion of the ild layer is sandwiched between the first and third source/drain epitaxial structures. the backside gate rail is under the ild layer and is electrically connected to the gate structure. the portion of the ild layer is directly above the backside gate rail.
Inventor(s): Chern-Yow HSU of Hsin-Chu county TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/66
CPC Code(s): H01L24/05
Abstract: a highly selective wet etch technique is used to etch a barrier layer under a metal layer from which the test pads of a semiconductor die are formed in a periphery region of the semiconductor die. the wet etch technique involves the use of a wet etchant that has a high etch rate for the barrier layer and a very low etch rate for a top dielectric layer on which the barrier layer is formed. sidewall spacers may be formed on the sidewalls of the test pads to protect the test pads from being etched by the wet etchant. the low etch rate of the top dielectric layer reduces and/or minimizes over etching into the top dielectric layer, which reduces and/or minimizes the step height between the top dielectric layer and the test pads.
Inventor(s): Po-Yao Lin of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Shu-Shen Yeh of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd., Chin-Hua Wang of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Yu-Sheng Lin of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Shin-Puu Jeng of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/18, H01L23/31, H01L23/48, H01L23/498, H01L25/00
CPC Code(s): H01L25/18
Abstract: provided are a package structure and a method of forming the same. the package structure includes a first tier, a second tier, and a third tier. the first tier includes an interposer. the second tier is disposed on the first tier and includes a bottom die. the third tier is disposed on the second tier and includes a plurality of first dies and at least one second die. the at least one second die is disposed between the plurality of first dies. the plurality of first dies are electrically connected to the bottom die by a plurality of first connectors to form a signal path, the plurality of first dies are electrically connected to the interposer by a plurality of second connectors to form a power path, and the plurality of first connectors are closer to the at least one second die than the plurality of second connectors.
Inventor(s): Shih-Lien Linus LU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Cheng-En LEE of Hinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H04L9/32, G06F21/75, G11C11/419, H03K3/03
CPC Code(s): H04L9/3278
Abstract: disclosed is a physical unclonable function generator circuit and method. in one embodiment, physical unclonable function (puf) generator includes: a puf cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two access transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state; a puf control circuit coupled to the puf cell array, wherein the puf control circuit is configured to access the plurality of bit cells to determine second logical states by turning on the at least one enable transistor and turning off the at least two access transistors of each of the plurality of bit cells, and based on the second logical states of the plurality of bit cells, to generate a puf output; and a noise injector coupled to the puf control circuit and the puf cell array, wherein the noise injector is configured to create stressed operation conditions to evaluate stability of the plurality of bit cells.
Inventor(s): Ping-Wei Wang of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Jui-Lin Chen of Taipei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: a semiconductor device according to the present disclosure includes a memory array having a plurality of memory cells arranged in a row, and an interconnect structure disposed over the memory cells and having a bit line coupled to each of the memory cells arranged in the row. the bit line has a first segment coupled to a first portion of the memory cells and a second segment coupled to a second portion of the memory cells. the first segment has a first width and the second segment has a second width that is smaller than the first width.
Inventor(s): Ting-Chen Hsu of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Hsin-Li Cheng of Hsin Chu TW for taiwan semiconductor manufacturing co., ltd., Jyun-Ying Lin of Wujie Township TW for taiwan semiconductor manufacturing co., ltd., Yingkit Felix Tsui of Cupertino CA US for taiwan semiconductor manufacturing co., ltd., Shu-Hui Su of Tucheng City TW for taiwan semiconductor manufacturing co., ltd., Shi-Min Wu of Changhua County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L29/94, H10B12/00
CPC Code(s): H10D1/042
Abstract: various embodiments of the present application are directed towards an integrated chip (ic). the ic comprises a trench capacitor overlying a substrate. the trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. the plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. the plurality of capacitor electrode structures comprise a metal component and a nitrogen component. the plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.
Inventor(s): Yuan-Sheng Huang of Taichung TW for taiwan semiconductor manufacturing co., ltd., Yi-Chen Chen of Jhubei TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L29/94
CPC Code(s): H10D1/042
Abstract: various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. the trench capacitor is on a substrate and comprises a plurality of capacitor segments. the capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. the plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. the edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. the greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.
20250113499. SEMICONDUCTOR DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Yun-Chi Chiang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Meng-Pei Lu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Shin-Yi Yang of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Cian-Yu Chen of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Chien-Hsin Ho of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Ming-Han Lee of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Shau-Lin Shue of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01F17/00, H01F27/28, H01L23/522
CPC Code(s): H10D1/20
Abstract: a semiconductor device including a substrate, a magnetic core and a conductor coil is provided. the magnetic core is disposed on the substrate, and formed by sub-layers of different materials stacked alternatively on one another. the conductor coil is disposed on the substrate, wherein the magnetic core partially extends to a level between an upper surface of the conductor coil and a bottom surface of the conductor coil.
Inventor(s): Wei Kai SHIH of Nantou County TW for taiwan semiconductor manufacturing co., ltd., Kuo-Liang WANG of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522
CPC Code(s): H10D1/682
Abstract: semiconductor devices and methods are disclosed herein. in one example, a disclosed semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. the insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.
Inventor(s): Chun-Wing YEUNG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Wen-Chiang HONG of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Yu-Jen CHANG of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Wei-Chen CHANG of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Feng-Ming CHANG of Taitung City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L23/528, H01L29/06, H01L29/40, H01L29/417, H01L29/423, H01L29/775
CPC Code(s): H10D30/014
Abstract: a method for forming a semiconductor structure is provided. the method includes forming a fin structure over a substrate, forming an isolation structure surrounding a lower portion of the fin structure, forming a protection layer over the isolation structure, etching the fin structure, the protection layer and the isolation structure to form a first recess in the fin structure and a second recess in the isolation structure, forming a source/drain feature to fill the first recess, and forming an interlayer dielectric layer over the source/drain feature and filling the second recess.
Inventor(s): Shao-An WANG of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Ding-Kang SHIH of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chia-Ling PAI of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Pinyen LIN of Rochester NY US for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/3065, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D30/024
Abstract: a method of forming source/drain regions of semiconductor devices is disclosed. the method includes forming a fin structure on a substrate, forming a polysilicon structure on the fin structure, removing a portion of the fin structure adjacent to the polysilicon structure to form an opening, and forming a s/d region in the opening. the forming the s/d region includes exposing the fin structure in the opening to a first flow rate of a precursor gas during a first phase of a gas flow cycle, a second flow rate of the precursor gas during a second phase of the gas flow cycle. the exposing the fin structure in the opening to the precursor gas, the etching gas, and the plasma is performed in an in-situ process.
Inventor(s): Kung-Pin CHANG of Caotun Township TW for taiwan semiconductor manufacturing co., ltd., Yi-Ting LIN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Wen-Chiang HONG of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Yao-Kwang WU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jyh-Huei CHEN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/311, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D30/031
Abstract: a method for forming a semiconductor device structure is provided. the method includes providing a substrate and a nanostructure stack. the method includes forming an isolation layer over the base and surrounding the fin. the method includes forming a first protection layer over the nanostructure stack and the isolation layer. the method includes forming a second protection layer over the first protection layer. the method includes forming a mask layer over the second protection layer. the top portion of the second protection layer protrudes from the mask layer. the method includes thinning the top portion of the second protection layer. the method includes removing the mask layer. the method includes removing the first protection layer and the second protection layer over the nanostructure stack. the method includes forming a gate stack wrapped around the nanostructure stack.
Inventor(s): Yi-Hong WANG of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Yi-Chen LI of Taichung City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L29/66
CPC Code(s): H10D30/603
Abstract: asymmetry may be used to tune electrical properties of tunnel field effect transistors (tfets). an exemplary tfet includes a gate stack disposed over a semiconductor layer, a source disposed in the semiconductor layer, and a drain disposed in the semiconductor layer. the gate stack includes a gate electrode disposed over a gate dielectric. the gate stack is disposed between the source and the drain. the source has a first conductivity type, and the drain has a second conductivity type different than the first conductivity type. the gate stack is asymmetric. for example, the gate stack has an asymmetric gate dielectric, an asymmetric gate electrode, asymmetric gate footing, asymmetric sidewalls, or combinations thereof. in some embodiments, the source and the drain have asymmetric profiles. in some embodiments, the semiconductor layer is a semiconductor fin, and the gate stack wraps the semiconductor fin.
Inventor(s): YI CHEN LIN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wei-Tse HSU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ya-Ching TSENG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/321, H01L29/06, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D30/6735
Abstract: a semiconductor device includes a substrate, a first active structure, a second active structure, an epitaxy and a conductive via. the first active structure is formed on the substrate and including a plurality of first sheets and a plurality of first spacers. the second active structure is disposed formed on the substrate and adjacent to the first active structure, wherein the second active structure includes a plurality of second sheets and a plurality of second spacers, the second sheets and the second spacers are stacked to each other, and there is trench between the first active structure and the second active structure. the epitaxy is formed within the trench. the conductive via is connected with the epitaxy. the semiconductor device further has a planarized surface including the first active structure, the second active structure and the conductive via, and the planarized surface has a flatness less than 10 nm.
Inventor(s): Chun Yi CHOU of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Guan-Lin CHEN of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Shi Ning JU of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/06, H01L29/08, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D30/6735
Abstract: a method includes forming semiconductive sheets over a substrate and arranged in a vertical direction; forming source/drain regions on either side of each of the semiconductive sheets; forming first air gap inner spacers interleaving with the semiconductive sheets; forming a gate around each of the semiconductive sheets, wherein the first air gap inner spacers are laterally between the gate and a first one of the source/drain regions.
Inventor(s): Chia-Cheng CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Sih-Jie LIU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Liang-Yin CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chi On CHUI of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/265, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H10D30/796
Abstract: a method includes: forming a stack of nanostructures over a substrate; forming a source/drain opening adjacent the stack of nanostructures; forming a semiconductor layer in the source/drain opening; forming an amorphous semiconductor layer by performing an ion implantation on the semiconductor layer; and forming a recrystallized source/drain by annealing the amorphous semiconductor layer.
Inventor(s): Jhon-Jhy LIAW of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L27/088, H01L29/08, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H10D62/118
Abstract: a semiconductor device includes a first circuit cell having first transistors, and a second circuit cell having second transistors and arranged with the first circuit cell in an x-direction. each of the first transistors includes first nanostructures vertically stacked from each other. each of the second transistors includes second nanostructures vertically stacked from each other. a cell pitch of the first circuit cell and a cell pitch of the second circuit cell in a y-direction are the same. a first pitch of the first nanostructures in the z-direction and a second pitch of the second nanostructures in the z-direction are the same. a first thickness of the first nanostructures in the z-direction is greater than a second thickness of the second nanostructures in the z-direction. a first width of the first nanostructures in the y-direction is greater than a second width of the second nanostructures in the y-direction.
Inventor(s): Lo-Heng CHANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Huan-Chieh SU of Changhua TW for taiwan semiconductor manufacturing co., ltd., Chun-Yuan CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Sheng-Tsung WANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L27/088, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/121
Abstract: embodiments of the present disclosure provide a semiconductor device with backside source/drain contacts formed using a buried source/drain feature and a semiconductor cap layer formed between the buried source/drain feature and a source/drain region. the buried source/drain feature and the semiconductor cap layer enable self-aligned backside source/drain contact and backside isolation. the semiconductor cap layer functions as an etch stop layer during backside contact formation while enabling source/drain region growth without fabrication penalty, such as voids in the source/drain regions.
Inventor(s): Yu-Ting Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Tai-Jung Kuo of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Mu-Chieh Chang of Zhubei City TW for taiwan semiconductor manufacturing co., ltd., Zhen-Cheng Wu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Sung-En Lin of Xionglin Township TW for taiwan semiconductor manufacturing co., ltd., Tze-Liang Lee of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/121
Abstract: various embodiments include protection layers for a transistor and methods of forming the same. in an embodiment, a method includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing a deposition selectivity between a top surface of the semiconductor nanostructure and a top surface of the isolation region relative a selective deposition process; depositing a protection layer on the top surface of the isolation region by performing the selective deposition process; removing the dummy nanostructure by selectively etching a dummy material of the dummy nanostructure at a faster rate than a protection material of the protection layer; and forming a gate structure around the semiconductor nanostructure.
Inventor(s): Ming-Che CHEN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yen-Cheng LAI of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Pin-Jung CHEN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Ming-Heng TSAI of Taipei TW for taiwan semiconductor manufacturing co., ltd., Feng-Ming CHANG of Taitung City TW for taiwan semiconductor manufacturing co., ltd., Chun-Jun LIN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/08, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D64/017
Abstract: a method of forming a semiconductor structure, includes forming a fin structure over a substrate in a z-direction; forming a dummy gate structure extending in a y-direction and over the fin structure; and forming gate spacers on sidewalls of the dummy gate structure. the fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. the method further includes removing a portion of the dummy gate structure to form a first trench that exposes upper portions of the gate spacers; forming an insulating material in the first trench; partially removing the insulating material to form insulating layers on sidewalls of the upper portions of the gate spacers; removing a remaining portion of the dummy gate structure to expose lower portions of the gate spacers; and partially etching the lower portions of the gate spacers.
Inventor(s): Ta-Chun LIN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Tzu-Hung LIU of Yunlin County TW for taiwan semiconductor manufacturing co., ltd., Chi-Hsin CHANG of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chun-Sheng LIANG of Changhua County TW for taiwan semiconductor manufacturing co., ltd., Chih-Hao CHANG of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/08, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D64/017
Abstract: semiconductor structures and methods for forming the same are provided. the semiconductor structure includes a plurality of nanostructures formed over a substrate, and a gate structure formed on the nanostructures. the semiconductor structure includes a source/drain (s/d) structure formed adjacent to the gate structure, and a fin spacer layer adjacent to the s/d structure. the bottom surface of the fin spacer layer is lower than a bottom surface of the s/d structure.
Inventor(s): Kuei-Yu KAO of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shih-Yao LIN of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chih-Chung CHIU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chen-Chin LIAO of Yilan TW for taiwan semiconductor manufacturing co., ltd., Chun-Yu LIN of Yilan TW for taiwan semiconductor manufacturing co., ltd., Min-Chiao LIN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yung-Chi CHANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Li-Jung KUO of Zhubei TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D64/021
Abstract: embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. the structure includes a source/drain region disposed over a substrate, a gate electrode layer disposed over the substrate, a first gate spacer disposed between the gate electrode layer and the source/drain region, and a dielectric spacer disposed between the gate electrode layer and the source/drain region. a first portion of the dielectric spacer is in contact with a first portion of the first gate spacer. the structure further includes a sacrificial layer disposed between a second portion of the first gate spacer and a second portion of the dielectric spacer.
Inventor(s): Chia-Hsi WANG of Changhua TW for taiwan semiconductor manufacturing co., ltd., Yen-Yu CHEN of Taichung City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/51, H01L29/40, H01L29/417, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H10D64/685
Abstract: a semiconductor device and a method of fabricating the semiconductor device are disclosed. the semiconductor device includes a substrate, a fin structure disposed on the substrate, and a gate structure. the gate structure includes a high-k gate oxide layer disposed on the fin structure, a diffusion barrier layer disposed on the high-k gate oxide layer, and a metal layer disposed on the diffusion barrier layer. the semiconductor device further includes a gate spacer disposed on the diffusion barrier layer and a source/drain (s/d) region disposed on the fin structure. a sidewall of the s/d region is in contact with a sidewall of the high-k gate oxide layer.
Inventor(s): Yu-Chi Pan of Zhubei City TW for taiwan semiconductor manufacturing co., ltd., Kuo-Bin Huang of Zhubei City TW for taiwan semiconductor manufacturing co., ltd., Ming-Hsi Yeh of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Ying-Liang Chuang of Zhubei City TW for taiwan semiconductor manufacturing co., ltd., Yu-Te Su of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuan-Wei Lin of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L29/49
CPC Code(s): H10D84/014
Abstract: a method includes depositing a first work function layer over a first and second gate trench. the method includes depositing a second work function layer over the first work function layer. the method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. the method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.
Inventor(s): Jui-Chien Huang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Cheng-Yin Wang of Taipei TW for taiwan semiconductor manufacturing co., ltd., Wei-Cheng Lin of Taichung TW for taiwan semiconductor manufacturing co., ltd., Kao-Cheng Lin of Taipei TW for taiwan semiconductor manufacturing co., ltd., Szuya Liao of Zhubei TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/088, H01L29/08, H01L29/417, H01L29/66
CPC Code(s): H10D84/834
Abstract: embodiments include mixed complementary field effect and unipolar transistors and methods of forming the same. in an embodiment, a structure includes: a first semiconductor nanostructure; a second semiconductor nanostructure; a first isolation structure interposed between the first semiconductor nanostructure and the second semiconductor nanostructure; a first source/drain region extending laterally from an end of the first semiconductor nanostructure, the first source/drain region having a first conductivity type; a second source/drain region extending laterally from an end of the second semiconductor nanostructure, the second source/drain region having the first conductivity type, the second source/drain region aligned vertically with the first source/drain region; and a first gate structure surrounding the first semiconductor nanostructure and the second semiconductor nanostructure.
Inventor(s): Yi-Ruei JHAN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuan-Lun CHENG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuan-Ting PAN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/02, H01L21/311, H01L21/762, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H10D84/85
Abstract: a device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate laterally offset from the first semiconductor channel. a first gate structure and a second gate structure are over and laterally surround the first and second semiconductor channels, respectively. a first inactive fin is between the first gate structure and the second gate structure. a dielectric feature over the inactive fin includes multiple layers of dielectric material formed through alternating deposition and etching steps.
Inventor(s): Kenichi SANO of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chia-Yun CHENG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yu-Wei LU of Taipei City TW for taiwan semiconductor manufacturing co., ltd., I-Ming CHANG of ShinChu TW for taiwan semiconductor manufacturing co., ltd., Pinyen LIN of Rochester NY US for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/28, H01L21/822, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H10D84/856
Abstract: semiconductor structures and methods for manufacturing the same are provided. the method includes forming first channel structures, second channel structures, and third channel structures. the method also includes forming gate dielectric layers surrounding the first channel structures, the second channel structures, and the third channel structures and forming dipole layers over the gate dielectric layers. the method also includes forming a dummy material in a first space between the first and the second channel structures and in a second space between the second and the third channel structures and removing first portions of the dummy material. the method also includes implanting first dopants in the dummy material in the first space and removing second portions of the dummy material in the first space and the second space. the method also includes removing the dipole layers in the top device region and completely removing the dummy material.
Inventor(s): Yu-Ching CHOU of Taipei TW for taiwan semiconductor manufacturing co., ltd., Ya-Chun TENG of Tainan TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/8057
Abstract: a pixel array may include a metal shielding structure on a grid structure between pixel sensors in the pixel array. the metal shielding structure laterally extends outward from the grid structure to reflect photons of incident light that might otherwise travel between the grid structure and the isolation structure of the pixel sensors in the pixel array. the lateral extensions of the metal shielding reflect these photons to reduce crosstalk between adjacent pixel sensors, thereby increasing the performance of the pixel array.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on April 3rd, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- B08B15/00
- B01D46/44
- G05B15/02
- G06V10/75
- G06V20/00
- H01J49/00
- H01J49/40
- H01L21/67
- H01L21/677
- CPC B08B15/00
- Taiwan semiconductor manufacturing co., ltd.
- B24B37/013
- H01L21/306
- H01L21/66
- CPC B24B37/013
- F24F9/00
- H01L21/687
- CPC F24F9/00
- G01N27/414
- H03K19/185
- CPC G01N27/4145
- G01R29/12
- CPC G01R29/12
- G01R31/28
- CPC G01R31/2853
- G02B6/122
- G02B6/13
- CPC G02B6/1228
- G02B6/34
- G02B6/30
- G02B6/42
- CPC G02B6/34
- H01L23/00
- H01L23/48
- H01L25/16
- H01L25/18
- CPC G02B6/4206
- G02B6/43
- H01L33/60
- H01L33/64
- CPC G02B6/43
- G03F7/00
- G03F1/62
- G03F1/82
- CPC G03F7/70925
- G06F30/3312
- G06F30/392
- G06F113/18
- G06F119/12
- CPC G06F30/3312
- G06F30/398
- CPC G06F30/398
- G11C11/16
- CPC G11C11/1659
- H01J37/34
- C23C14/35
- CPC H01J37/3408
- H01L21/3105
- H01L21/311
- H01L29/06
- H01L29/423
- CPC H01L21/30604
- C09G1/02
- H01L21/02
- H01L21/304
- H01L21/321
- CPC H01L21/30625
- H01L21/683
- B25B11/00
- CPC H01L21/6838
- H01L21/768
- H01L23/522
- H01L23/528
- CPC H01L21/76802
- H01L23/532
- CPC H01L21/76832
- CPC H01L21/76843
- H01L23/31
- H01L21/56
- H01L23/29
- H01L23/538
- H01L25/10
- CPC H01L23/3185
- H01L23/498
- H01L21/48
- H01L23/373
- H01L25/065
- CPC H01L23/49822
- H01L21/70
- H01L27/01
- CPC H01L23/5226
- H01L21/8238
- H01L27/092
- H01L29/08
- H01L29/66
- H01L29/775
- CPC H01L23/5286
- CPC H01L24/05
- H01L25/00
- CPC H01L25/18
- H04L9/32
- G06F21/75
- G11C11/419
- H03K3/03
- CPC H04L9/3278
- H10B10/00
- CPC H10B10/125
- H01L29/94
- H10B12/00
- CPC H10D1/042
- H01F17/00
- H01F27/28
- CPC H10D1/20
- CPC H10D1/682
- H01L29/40
- H01L29/417
- CPC H10D30/014
- H01L21/3065
- H01L29/786
- CPC H10D30/024
- CPC H10D30/031
- H01L29/78
- CPC H10D30/603
- CPC H10D30/6735
- H01L21/8234
- H01L27/088
- H01L21/265
- CPC H10D30/796
- CPC H10D62/118
- CPC H10D62/121
- CPC H10D64/017
- CPC H10D64/021
- H01L29/51
- CPC H10D64/685
- H01L29/49
- CPC H10D84/014
- CPC H10D84/834
- H01L21/762
- CPC H10D84/85
- H01L21/28
- H01L21/822
- CPC H10D84/856
- H01L27/146
- CPC H10F39/8057