Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on April 10th, 2025
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on April 10th, 2025
Taiwan Semiconductor Manufacturing Co., Ltd.: 81 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L23/00 (15), H01L23/522 (12), H01L23/528 (11), H01L21/768 (11), H01L29/66 (9) H01L23/562 (2), H10D84/834 (2), H01L23/544 (2), H01L25/0657 (2), H10D84/038 (2)
With keywords such as: layer, structure, semiconductor, dielectric, conductive, substrate, gate, memory, die, and forming in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Cheng-Lung WU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yang-Ann CHU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsu-Shui LIU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jiun-Rong PAI of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B05B1/00, B05B13/02
CPC Code(s): B05B1/002
Abstract: a plurality of purge nozzles of a purge load port include a nozzle gasket and a nozzle structure to inject a purging fluid into and through an internal chamber of a container (e.g., a foup) that is configured to, in operation, transport wafers or workpieces between various locations within a fab. the nozzle gasket includes a deformable structure that abuts against a surface of a nozzle structure and a sealing structure opposite to the deformable structure that forms a seal between the container and the nozzle gasket. a nozzle hole of a nozzle of the nozzle structure includes a threaded region or portion that is configured to receive a threaded stopper structure to seal off the nozzle hole.
Inventor(s): Shih-Chung Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wei-Kang Tu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ching-Wen Cheng of Zhubei TW for taiwan semiconductor manufacturing co., ltd., Chun Yan Chen of Zhubei TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B24B41/00, B24B29/00, B24B49/18
CPC Code(s): B24B41/005
Abstract: a system and method for chemical mechanical polishing (“cmp”) pad replacement on a cmp processing tool. a platen carrier having two or more platens is positioned within a platen cleaning process module. each platen includes a cmp pad affixed thereto, and is capable of being independently rotated during operations. when a pad requires replacement, the platen carrier rotates towards a pad tearer tool, which extends and pivots to remove the used pad from the platen as the carrier rotates. a pad tape replacement module is positioned above the cmp tool with pad tape extending from a supply roll to a recycle roll. as the pad tape transits through the module, a backing of the tape is separated and recycled. a pad disposed in the pad tape is then applied to a platen via a pressure roller.
Inventor(s): Ming-Hsuan CHANG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yuan-Li LIN of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Sheng-Ming YANG of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Kuo-Ming LU of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01R31/28
CPC Code(s): G01R31/2877
Abstract: a semiconductor testing apparatus is provided, and includes a base, a conductive socket, a pusher, and a thermal interface material structure. the conductive socket is disposed in the base for containing a semiconductor structure. the pusher is over the conductive socket and movable in a vertical direction. the thermal interface material structure is connected to the pusher, and includes a resilient material and a metal film around the resilient material. the metal film and the resilient material are in contact with the pusher.
Inventor(s): Ming-Hui Weng of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Wei-Han Lai of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Ching-Yu Chang of Yilang County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/039, G03F7/038
CPC Code(s): G03F7/039
Abstract: a photoresist composition includes a solvent and a polymer. the polymer comprises a polymer backbone, an acid labile group monomer, a photo acid generator monomer and a quencher monomer. the acid labile group monomer is bonded to the polymer backbone. the acid labile group monomer is acid cleavable. the photo acid generator monomer is bonded to the polymer backbone. the quencher monomer is bonded to the polymer backbone.
Inventor(s): Li-Po YANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wei-Han LAI of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuan-Hsin LO of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/039, C08F212/14, C08F220/18, C08F220/38, G03F7/038
CPC Code(s): G03F7/039
Abstract: a method for manufacturing a semiconductor device includes forming a photoresist layer from a photoresist composition over a substrate. the photoresist layer is selectively exposed to actinic radiation to form a latent pattern and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a patterned photoresist. the photoresist composition includes a photoactive compound, a thiol-containing polymer comprising an aryl group and an acid labile group. the thiol group can crosslink the polymer via oxidative disulfide formation and/or thiol-ene/yne “click” reaction.
20250116937. LITHOGRAPHY PROCESS_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Ming-Hui WENG of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Wei-Han LAI of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Hsien-Chung HUANG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Yilang County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/40, G03F7/00, H01L21/027, H01L29/66
CPC Code(s): G03F7/40
Abstract: a lithography method includes the steps which are mentioned below. a photoresist layer is formed over a substrate. the photoresist layer is exposed. the photoresist layer is developed. a vacuum treatment is performed to the photoresist layer. the substrate is etched by using the photoresist layer as an etch mask.
Inventor(s): Chi YANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Po-Yuan YEH of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Che-Hsin LIN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jen Chieh YU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chung Wen LUO of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/00, G03F7/20
CPC Code(s): G03F7/70033
Abstract: a method includes: forming a mask layer on a semiconductor wafer; forming a tin droplet, including: supplying tin to a high-pressure reservoir from a low-pressure reservoir; monitoring a level of tin in the high-pressure reservoir by at least two electrodes attached to the high-pressure reservoir; in response to the level of the tin exceeding a threshold value, supplying the tin to a droplet generator from the high-pressure reservoir; forming the tin droplet by the droplet generator using the tin supplied from the high-pressure reservoir; generating light by the tin droplet; and patterning the mask layer by the light.
Inventor(s): Yen-An Chang of Miaoli County TW for taiwan semiconductor manufacturing co., ltd., Yi-Chun Shih of Taipei TW for taiwan semiconductor manufacturing co., ltd., Chieh-Pu Lo of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G05F1/575, G05F1/565, G05F1/59
CPC Code(s): G05F1/575
Abstract: a reference voltage generator includes an input terminal configured to receive an enable signal and an output terminal configured to provide an output signal. a voltage generator circuit is arranged to generate a first output voltage signal, and a pre-settling circuit is arranged to generate a second output voltage. the pre-settling circuit is configured to provide the second output voltage signal at the output terminal in response to the enable signal received at the input terminal, and following a first time period provide the first output voltage at the output terminal.
Inventor(s): Win-San Khwa of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Yi-Lun Lu of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Jen-Chieh Liu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jui-Jen Wu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Meng-Fan Chang of Taichung City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F7/544
CPC Code(s): G06F7/5443
Abstract: a computing circuit is configured to perform a bit-serial multiplication of an input signal and a weight signal. a multiplier circuit is configured to receive the input signal and the weight signal and to provide a product sum. an adder circuit is configured to receive the product sum and to provide a partial sum. a partial sum register is configured to: clock-gate a second part of the partial sum register; receive the partial sum; provide, based on the partial sum, a first output of the bit-serial multiplication through a first part of the partial sum register; determine whether not to clock-gate the second part of the partial sum register or not based on a first feature bit of the partial sum; and provide, based on the first feature bit of the partial sum, a second output of the bit-serial multiplication through the second part of the partial sum register.
Inventor(s): Jack Liu of Taipei TW for taiwan semiconductor manufacturing co., ltd., Kuo-Nan Yang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/392, G06F30/3953, G06F119/06, H01L23/522, H10D62/10
CPC Code(s): G06F30/392
Abstract: one aspect of this description relates to an integrated circuit (ic) structure including a first layer and a second layer. the first layer includes a first metal structure coupled to a first power supply having a first voltage level and a second metal structure coupled to a second power supply having a second voltage level different from the first voltage level. the second layer is formed over the first layer. the second layer includes a first nano-sheet device coupled to the first metal structure and a second nano-sheet device adjacent to the first nano-sheet device. the second nano-sheet device is coupled to the second metal structure. a distance between the first nano-sheet device and the second nano-sheet device is less than a minimum n-well to n-well spacing.
Inventor(s): Hiranmay BISWAS of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chung-Hsing WANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chin-Shen LIN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuo-Nan YANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/392, G06F30/337, G06F30/394, G06F30/3947, G06F30/3953, G06F30/398, H01L23/522, H01L23/528, H01L23/532
CPC Code(s): G06F30/392
Abstract: a method of forming an integrated circuit device includes forming first segments extending in a first direction in a first conductive layer; forming second segments extending in the first direction in the first conductive layer, the forming the first and second segments including: interspersing the first and second segments relative to a second direction perpendicular to the first direction such that: the first segments are symmetrically spaced apart relative to each other, the second segments are symmetrically spaced apart relative to each other, and ones of the second segments are substantially asymmetrically spaced between corresponding adjacent ones of the first segments.
Inventor(s): Shao-Lun CHIEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Pin-Dai SUE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Li-Chun TIEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ting-Wei CHIANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ting Yu CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10D84/90
CPC Code(s): G06F30/398
Abstract: a method of manufacturing a transmission gate includes overlying a substrate with first through fourth adjacent metal segments in a same metal layer. each of the first and second metal segments, second and third metal segments, and third and fourth metal segments are offset from each other by an offset distance in a first direction, the first metal segment overlies a first active area in the substrate including first and second pmos transistors, and the fourth metal segment overlies a second active area in the substrate including first and second nmos transistors. the method includes configuring the first and second pmos transistors and the first and second nmos transistors as a transmission gate by forming first through third conductive paths, the first conductive path including a fifth metal segment overlying at least three of the first through fourth metal segments along a second direction perpendicular to the first direction.
Inventor(s): Win-San KHWA of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Yu-Der CHIH of Hsin-Chu City TW for taiwan semiconductor manufacturing co., ltd., Yi-Chun SHIH of Taipei TW for taiwan semiconductor manufacturing co., ltd., Chien-Yin LIU of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06N3/063, G06N3/08, G11C7/10, G11C11/54, G11C29/04
CPC Code(s): G06N3/063
Abstract: disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. in one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.
Inventor(s): Win-San KHWA of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Ping-Chun WU of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Tung Ying LEE of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Meng-Fan CHANG of Taichung City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C13/00
CPC Code(s): G11C7/1096
Abstract: memory systems and operating method of a memory system are provided. the memory system utilized for performing a computing-in-memory (cim) operation comprises a memory array and a processing circuit. the memory array comprises a plurality of memory cells. the processing circuit is coupled to the memory array and comprises a programming circuit and a control circuit. the programming circuit is coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells. the control circuit is coupled to the programming circuit and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values.
Inventor(s): Xiu-Li YANG of Shanghai City CN for taiwan semiconductor manufacturing co., ltd., He-Zhou WAN of Shanghai City CN for taiwan semiconductor manufacturing co., ltd., Mu-Yang YE of Nanjing City CN for taiwan semiconductor manufacturing co., ltd., Lu-Ping KONG of Nanjing City CN for taiwan semiconductor manufacturing co., ltd., Ming-Hung CHANG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C7/22, G11C7/10, G11C7/12, G11C8/08, G11C8/10
CPC Code(s): G11C7/12
Abstract: a device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. the first modulation circuit is coupled to the first memory subarray. the second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. the second modulation circuit is coupled to the second memory subarray. the control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.
Inventor(s): Chun-Ying Lee of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chieh Lee of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Tung-Cheng Chang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yen-Hsiang Huang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chia-En Huang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/419, G11C5/06, G11C8/08, H01L23/522, H01L23/528, H10B10/00
CPC Code(s): G11C11/419
Abstract: a memory device comprises a memory array, a plurality of access word lines, and a first tracking word line. the memory array may include a plurality of bit cells arranged over a plurality of rows and a plurality of columns. the plurality of access word lines may extend along a lateral direction. the plurality of rows may operatively correspond to the plurality of access word lines, respectively. the first tracking word line may also extend along the lateral direction and have a first portion extending from an edge of the memory array to a middle of the memory array and a second portion extending from the middle of the memory array to the edge of the memory array. the first combination can be different from the second combination.
Inventor(s): Hiroki Noguchi of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yu-Der Chih of Hsin-Chu City TW for taiwan semiconductor manufacturing co., ltd., Yih Wang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C13/00, G11C11/16, G11C11/22
CPC Code(s): G11C13/0069
Abstract: a memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.
Inventor(s): Meng-Sheng Chang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C17/16, G11C17/18, H10B20/25
CPC Code(s): G11C17/16
Abstract: a semiconductor device includes a memory cell including a first transistor, a second transistor, and a resistor. each of the first transistor and the second transistor is operatively coupled to the resistor in series. the second transistor is formed below the resistor such that the second transistor provides heat to the resistor when the memory cell is being programmed.
Inventor(s): Kai-Fang Cheng of Taoyuan District TW for taiwan semiconductor manufacturing co., ltd., Hsiao-Kang Chang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/02, H01L29/778
CPC Code(s): H01L21/02178
Abstract: semiconductor devices and methods of forming the same are provided. a method of the present disclosure includes depositing an aluminum nitride layer over a substrate, treating the aluminum nitride layer to convert a top portion of the aluminum nitride layer to an aluminum oxynitride layer, depositing a iii-v semiconductor layer on the aluminum oxynitride layer, and forming a gate structure over the iii-v semiconductor layer.
Inventor(s): Jen-Hong Chang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yuan-Ching Peng of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jiun-Ming Kuo of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuo-Yi Chao of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chih-Chung Chang of Nantou County TW for taiwan semiconductor manufacturing co., ltd., You-Ting Lin of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yen-Po Lin of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chen-Hsuan Liao of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/033, H01L21/8234, H01L29/423, H01L29/66
CPC Code(s): H01L21/0337
Abstract: a method includes forming a semiconductor substrate, forming hard mask layers (hms) over the semiconductor substrate, forming first mandrels over the hms, forming second mandrels along sidewalls of the first mandrels, forming a protective layer over the first mandrels and the second mandrels, removing a portion of the protective layer to expose portions of the first and the second mandrels, removing the exposed portions of the second mandrels with respect to the exposed portions of the first mandrels, removing remaining portions of the protective layer to expose remaining portions of the first and second mandrels, where the exposed portions of the first mandrels and the remaining portions of the first and second mandrels form a mandrel structure, patterning the hms using the mandrel structure as an etching mask, and patterning the semiconductor substrate to form a fin structure using the patterned hms as an etching mask.
Inventor(s): Chih-Cheng LIU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wei-Zhong CHEN of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chi-Ming YANG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Jr-Hung LI of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Yung-Cheng LU of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/311, C23C16/26, C23C16/505, C23C16/56, H01J37/32, H01L21/308
CPC Code(s): H01L21/31144
Abstract: a method includes following steps. a target layer is formed over a substrate. a first hard mask layer is formed over the target layer by a plasma generated using a first radio frequency generator and a second radio frequency generator. the first radio frequency generator and the second radio frequency generator have different powers. a second hard mask layer is formed over the first hard mask layer by a plasma generated using the first radio frequency generator without using the second radio frequency generator. a photoresist layer is formed over the second hard mask layer. the photoresist layer is exposed. the photoresist layer is developed. the first hard mask layer and the second hard mask layer are patterned using the photoresist layer as an etch mask. the target layer is patterned using the first hard mask layer and the second hard mask layer as an etch mask.
Inventor(s): Hsien-Wei Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ming-Fa Chen of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Ying-Ju Chen of Tuku Township TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/18, H01L21/66, H01L23/00, H10B80/00
CPC Code(s): H01L21/563
Abstract: a method of forming an integrated circuit package includes attaching a first die to an interposer. the interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. the first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. the method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.
Inventor(s): Lung-Yin Tang of Keelung TW for taiwan semiconductor manufacturing co., ltd., Tsung-Min Lin of Zhubei TW for taiwan semiconductor manufacturing co., ltd., Hsin-Sheng Liang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/683, H01J37/317
CPC Code(s): H01L21/683
Abstract: a horizontally oriented calibration jig for a wafer gripper arm of an ion implanter is disclosed. the calibration jig is mounted within the process chamber of the ion implanter. the calibration jig includes a mounting plate that spans a diameter of the wafer gripper arm, a support stand passing through the mounting plate, and a calibration plate at a bottom end of the support stand. the perimeter of the calibration plate includes a plurality of notches. the calibration plate is rotated. if any finger of the wafer gripper arm falls into a notch, the rotating calibration plate stops. the finger is then adjusted until it does not fall into a notch.
Inventor(s): Xin-Hua Huang of Xihu Township TW for taiwan semiconductor manufacturing co., ltd., Ping-Yin Liu of Yonghe City TW for taiwan semiconductor manufacturing co., ltd., Chang-Chen Tsao of Tainan City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10D88/00
CPC Code(s): H01L21/6833
Abstract: in some embodiments, the present disclosure relates to a method that includes aligned a first wafer with a second wafer. the second wafer is spaced apart from the first wafer. the first wafer is arranged on a first electrostatic chuck (esc). the first esc has electrostatic contacts that are configured to attract the first wafer to the first esc. further, the second wafer is brought toward the first wafer to directly contact the first wafer at an inter-wafer interface. the inter-wafer interface is localized to a center of the first wafer. the second wafer is deformed to gradually expand the inter-wafer interface from the center of the first wafer toward an edge of the first wafer. the electrostatic contacts of the first esc are turned off such that the first and second wafers are bonded to one another by the inter-wafer interface.
Inventor(s): Chia-Wei SU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsin-Ping CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yung-Hsu WU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Li-Ling SU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chan-Yu LIAO of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shao-Kuan LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ting-Ya LO of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsin-Yen HUANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsiao-Kang CHANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/528, H01L23/532
CPC Code(s): H01L21/76816
Abstract: the semiconductor structure and a manufacturing method thereof are provided. the semiconductor structure includes a first dielectric layer, a first metal layer, a second metal layer, a first etching stop layer, a second etching stop layer, a second dielectric layer, a first via and a second via. the first metal layer and the second metal are embedded in the first dielectric layer. the first etching stop layer is disposed on the first dielectric layer. the second etching stop layer is disposed on the first etching stop layer. the second dielectric layer is disposed on the second etching stop layer. the first via and the second via are embedded in the second dielectric layer. a width of the second etching stop layer is smaller a width of the first etching stop layer.
Inventor(s): Shao-Kuan Lee of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Ting-Ya Lo of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsin-Yen Huang of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chia Chen Lee of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Hsiao-Kang Chang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L21/7682
Abstract: semiconductor structures and methods of forming the same are provided. an exemplary method incudes forming a first dielectric layer over a first conductive feature, forming a conductive via extending through the first dielectric layer and coupled to the first conductive feature, forming a hard mask layer over the conductive via, patterning the hard mask layer to form a first opening exposing the first dielectric layer; forming a sacrificial layer to partially fill the first opening, forming a porous dielectric layer on the sacrificial layer, after the forming of the porous dielectric layer, selectively removing the sacrificial layer to form an air gap, forming a second dielectric layer over the porous dielectric layer, and replacing a portion of the patterned hard mask layer disposed directly over the conductive via with a second conductive feature.
Inventor(s): Yung-Chih Tsai of Jhudong Township TW for taiwan semiconductor manufacturing co., ltd., Wei-Che Hsu of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Yu-Chung Yang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Alexander Kalnitsky of San Francisco CA US for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/528, H01L23/532, H01L23/535
CPC Code(s): H01L21/7682
Abstract: a semiconductor structure includes a substrate and a dielectric material disposed over the substrate. a void is disposed within the dielectric material. a dielectric liner is disposed along inner sidewalls of the dielectric material proximate to the void. an inner surface of the dielectric liner defines an outer extent of the void, and the dielectric liner includes an inner liner layer and an outer liner layer.
Inventor(s): Cheng-Chin LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ting-Ya LO of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chi-Lin TENG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shao-Kuan LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuang-Wei YANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Gary HSU WEI LIU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yen-Ju WU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Jing-Ting SU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsin-Yen HUANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsiao-Kang CHANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Wei-Chen CHU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shu-Yun KU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chia-Tien WU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Ming-Han LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsin-Ping CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/528
CPC Code(s): H01L21/76843
Abstract: an interconnection structure and a manufacturing method thereof are provided. the interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. the first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.
Inventor(s): Chun Yu Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yen Lian Lai of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/58
CPC Code(s): H01L23/10
Abstract: a semiconductor structure according to the present disclosure includes a circuit region disposed over a substrate and a seal ring region disposed over the substrate and completely surrounding the circuit region. the circuit region includes first fins, second fins, n-type epitaxial structures over the first fins, and p-type epitaxial structures over the second fins. the seal ring region includes fin rings extending completely around the circuit region, epitaxial rings disposed over and extending parallel to the fin rings. all of the epitaxial rings over all of the fin rings in the seal ring region are p-type epitaxial rings.
Inventor(s): Wensen Hung of Zhubei City TW for taiwan semiconductor manufacturing co., ltd., Yen-Fu Su of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Tsung-Yu Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/18, H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L23/18
Abstract: a semiconductor package and the method of forming the same are provided. the semiconductor package may include a substrate, an integrated circuit package component having a semiconductor die bonded to the substrate, and a ring structure on the substrate, wherein the ring structure may encircle the integrated circuit package component in a top-down view. the ring structure may comprise a first attached segment, a second attached segment attached to the substrate by an adhesive, and a first suspended segment between the first attached segment and the second attached segment. the first suspended segment may be suspended over the substrate. the first attached segment and the second attached segment may be spaced apart from the package component by a first distance and a second distance, respectively. the first suspended segment may be spaced apart from the package component by a third distance different from the first distance and the second distance.
Inventor(s): Hsin Chang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Po-Han Wang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang Hu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/31, H01L23/00, H01L23/498, H01L23/522, H01L25/00, H01L25/065
CPC Code(s): H01L23/3128
Abstract: a method of forming a semiconductor package includes: surrounding a die with a molding material; and forming a redistribution structure (rds) over the molding material and electrically coupled to the die, which includes: depositing a first dielectric layer over the molding material; patterning the first dielectric layer to form first openings in the first dielectric layer; performing a first descum process to clean the first openings; after performing the first descum process, forming a first redistribution layer (rdl) on the first dielectric layer; depositing a second dielectric layer over the molding material; patterning the second dielectric layer to form second openings in the second dielectric layer; performing a second descum process to clean the second openings, where the first and second descum processes are performed under different process conditions; and after performing the second descum process, forming a second rdl on the second dielectric layer.
Inventor(s): Chen Chen of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Yu-Hung Lin of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Chih-Hao Yu of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Wei-Ming Wang of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Chia-Hui Lin of Taichung County TW for taiwan semiconductor manufacturing co., ltd., Shih-Peng Tai of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/31, G02B6/42, H01L23/00, H01L25/16, H01L25/18
CPC Code(s): H01L23/3178
Abstract: a semiconductor package includes a photonic integrated circuit (pic) die having a photonic layer, and an electronic integrated circuit (eic) die bonded to the pic die. the eic die includes an optical region that allows the transmission of optical signals through the optical region towards the photonic layer, and a peripheral region outside of the optical region. the optical region includes optical concave/convex structures, a protection film and optically transparent material layers. the optical concave/convex structures are formed in the semiconductor structure. the protection film is conformally disposed over the optical concave/convex structures. the optically transparent material layers are disposed over the protection film and filling up the optical region. the peripheral region includes first bonding pads bonded to the photonic integrated circuit die, and via structures connected to the first bonding pads, wherein the protection film is laterally surrounding sidewalls of the via structures.
Inventor(s): Yung-Ta Chen of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Kuan-Kan Hu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chun-Yu Liu of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Che Chi Shih of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd., Ku-Feng Yang of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Szuya Liao of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L21/48, H01L23/00, H01L23/373
CPC Code(s): H01L23/3677
Abstract: a method includes forming a bonding structure that contains thermal conductive vias (also termed as thermal vias, thermal conductive pillars, or thermal pillars) on a semiconductor structure. the thermal vias, with material thermal conductivity greater than about 10 w/m�k, are embedded in the bonding structure that provides a quick dissipation path of heat from thermal hotspot regions into a substrate.
Inventor(s): Yi-Hsin Nien of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chih-Yu Lin of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Hidehiro Fujiwara of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yen-Huei Chen of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H10B10/00
CPC Code(s): H01L23/481
Abstract: a memory device may comprise a substrate, a plurality of memory cells, and a header device. the substrate may have a first side and a second side opposite to each other. the plurality of memory cells may be formed on the first side of the substrate. the header device may be formed on the first side of the substrate. the header device can be configured to selectively couple a supply voltage through a first combination of power delivery paths or a second combination of power delivery paths to the plurality of memory cells based on a control signal.
Inventor(s): Chen-Hsuan Tsai of Taitung City TW for taiwan semiconductor manufacturing co., ltd., Chin-Chuan Chang of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/498, G02B6/12, G02B6/42, H01L21/56, H01L21/683, H01L23/00, H01L25/065
CPC Code(s): H01L23/49816
Abstract: a method of forming a semiconductor package includes the following operations. at least one integrated circuit structure is provided and bonded to an interposer structure. a photonic structure is provided and bonded to the interposer structure, wherein the photonic structure has a recessed feature covered by a mask and facing a light source. an encapsulation layer is formed around the at least one integrated circuit structure and the photonic structure. at least a portion of the mask layer is removed from the photonic structure.
Inventor(s): Ying-Ju Wu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Tzu-Ting Liu of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd., Hsiang-Ku Shen of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chen-Chiu Huang of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Dian-Hau Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/768
CPC Code(s): H01L23/5223
Abstract: a passivation layer is formed over an interconnect structure. an opening is etched at least partially through the passivation layer. a first conductive layer is deposited over the passivation layer. the first conductive layer partially fills the opening. an insulator layer is deposited over the first conductive layer. the insulator layer partially fills the opening. a second conductive layer is deposited over the insulator layer. the second conductive layer completely fills the opening. a first conductive structure is formed that is electrically coupled to the first conductive layer. a second conductive structure is formed that is electrically coupled to the second conductive layer.
Inventor(s): Yun-Sheng Li of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chih Hsin Yang of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Chih-Chieh Chang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Mao-Nan Wang of Kaohsiung TW for taiwan semiconductor manufacturing co., ltd., Kuan-Hsun Wang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yang-Hsin Shih of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L23/528, H01L27/02, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H01L23/5226
Abstract: a semiconductor structure according to the present disclosure includes a substrate; a through substrate via (tsv) cell over the substrate; and a tsv extending through the tsv cell and the substrate. the tsv cell includes a guard ring structure extending around a perimeter of the tsv cell, and a buffer zone surrounded by the guard ring. the buffer zone includes first dummy transistors, and second dummy transistors. each of the first dummy transistors includes two first type epitaxial features, a first plurality of nanostructures extending between the two first type epitaxial features, and a first isolation gate structure wrapping over the first plurality of nanostructures. each of the second dummy transistors includes two second type epitaxial feature, a second plurality of nanostructures extending between the two first type epitaxial features, and a second isolation gate structure wrapping over the second plurality of nanostructures.
Inventor(s): Wei-Xiang You of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Jui-Chien Huang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chun-Yen Lin of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Szuya Liao of Zhubei TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/8238, H01L23/528, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L23/5226
Abstract: a method includes forming a first complementary field-effect transistor (cfet) and a second cfet. the first cfet includes a first lower transistor, and a first upper transistor overlapping the first lower transistor. the second cfet includes a second lower transistor, and a second upper transistor overlapping the second lower transistor. the method further includes performing a first etching process to form a first opening, wherein the first etching process includes etching a first gate stack between the first upper transistor and the second upper transistor, and etching a second gate stack between the first lower transistor and the second lower transistor. the first opening is filled with a dielectric material to form a dielectric region. the method further includes performing a second etching process to etch a middle portion of the dielectric region and to form a second opening, and filling the second opening with a conductive material to form a through-via.
20250118658. SEMICONDUCTOR DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Cheng-Hsien Lai of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shih-Ming Chen of Miaoli County TW for taiwan semiconductor manufacturing co., ltd., Han-Chang Hsieh of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H10D1/20
CPC Code(s): H01L23/5227
Abstract: a semiconductor device includes a semiconductor substrate, an interconnection layer and an inductor pattern. the interconnection layer is disposed on the semiconductor substrate. the inductor pattern is electrically connected to the interconnection layer. the inductor pattern includes a first conductive line joined with a first terminal, a second conductive line joined with a second terminal, and a plurality of conductive coils. the conductive coils are joining the first conductive line to the second conductive line, and includes an outer coil joined with the first conductive line, an inner coil joined with the second conductive line and the outer coil. the second conductive line is spaced apart from a first side of the inner coil in a first direction by distance y, the second terminal is spaced apart from a second side of the inner coil in a second direction by distance x wherein x>1.25y.
Inventor(s): Yung-Shih CHENG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L23/522, H01L23/58, H01L25/00, H01L25/065
CPC Code(s): H01L23/5283
Abstract: provided are a semiconductor device and a method of forming the same. the semiconductor device includes a device layer having a frontside and a backside; a first interconnect structure disposed on the frontside of the device layer, and having a first seal ring structure; a second interconnect structure disposed on the backside of the device layer; and a diode and a transistor embedded in the device layer, wherein a gate of the transistor is electrically connected to the first seal ring structure by the diode.
Inventor(s): Wan-Yu LO of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd., Chin-Shen LIN of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chi-Yu LU of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Kuo-Nan YANG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chih-Liang CHEN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chung-Hsing WANG of Baoshan Township TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L21/768
CPC Code(s): H01L23/5286
Abstract: semiconductor devices are provided. a semiconductor device includes a power switch, a first power mesh and a second power mesh. the power switch has a first terminal and a second terminal. the first power mesh is directly connected to the first terminal of the power switch. the second power mesh is directly connected to the second terminal of the power switch. the first power mesh includes a first power rail over the power switch and extending in a first direction. the second power mesh includes a second power rail under the power switch and extending in the first direction. the first and second power rails are separated from each other.
Inventor(s): Ni-Wan Fan of Miao-Li County TW for taiwan semiconductor manufacturing co., ltd., Ting-Wei Chiang of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Cheng-I Huang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Jung-Chan Yang of Longtan Township TW for taiwan semiconductor manufacturing co., ltd., Hsiang-Jen Tseng of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Lipen Yuan of Jhubei City TW for taiwan semiconductor manufacturing co., ltd., Chi-Yu Lu of New Taipei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L21/768, H01L23/485, H01L23/535, H10D64/01, H10D84/01, H10D84/03, H10D84/83, H10D84/90, H10D89/10
CPC Code(s): H01L23/5286
Abstract: the present disclosure, in some embodiments, relates to an integrated circuit. the integrated circuit includes first and second source/drain regions arranged on or within a substrate. a first gate is arranged over the substrate between the first source/drain region and the second source/drain region. a first middle-end-of-the-line (meol) structure is arranged over the second source/drain region and a second meol structure is arranged over a third source/drain region. a conductive structure contacts the first meol structure and the second meol structure. a second gate is separated from the first gate by the second source/drain region. the conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. a plurality of conductive contacts are configured to electrically couple an interconnect wire and the first meol structure along one or more conductive paths extending through the conductive structure.
Inventor(s): Yung-Chi Chu of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Jhih-Yu Wang of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang Hu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/58, H01L21/48, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L23/5389
Abstract: a package includes a die and a redistribution structure. the die has an active surface and is wrapped around by an encapsulant. the redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.
Inventor(s): Chih-Hsiung PENG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shih-Chi FU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuei-Shun CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yu-Lun LIU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/544, H01L21/308, H01L21/3105, H01L21/8234
CPC Code(s): H01L23/544
Abstract: a method includes: forming a first mask over a substrate; forming first openings and a second opening in the first mask; forming first wells in first regions of the substrate exposed by the first openings and an alignment implant in a second region of the substrate exposed by the second opening; forming an alignment mark by recessing the alignment implant; and patterning a multi-layer semiconductor lattice under alignment of the alignment mark.
20250118682. PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Jhih-Yu Wang of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang Hu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Sih-Hao Liao of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Yung-Chi Chu of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/31, H01L23/498, H01L25/00, H01L25/07
CPC Code(s): H01L23/544
Abstract: a package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. the insulating encapsulant is encapsulating the plurality of semiconductor dies. the redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.
Inventor(s): Wen-Ling CHANG of Miaoli County TW for taiwan semiconductor manufacturing co., ltd., Wen-Chiung TU of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chen-Chiu HUANG of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Hsiu-Wen HSUEH of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Hsiang-Ku SHEN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Dian-Hau CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Po-Hsiang HUANG of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Ke-Rong HU of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd., Cheng-Nan LIN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/053, H01L23/29, H01L25/065
CPC Code(s): H01L23/562
Abstract: the present disclosure provides an integrated circuit (ic) structure that includes a substrate having a circuit region and a chip corner region; ic devices formed on the substrate within the circuit region; a passivation layer formed over the ic devices; and a polyimide layer formed over the passivation layer, wherein the passivation layer and the polyimide layer include a stress-release pattern formed in the chip corner region.
Inventor(s): Chun-Liang LU of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Chun-Wei CHIA of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Chun-Hao CHOU of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng LEE of Tainan City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/58, H01L23/00
CPC Code(s): H01L23/562
Abstract: a semiconductor device includes a first wafer comprising a first portion of a seal ring structure within a body of the first wafer. the semiconductor device includes a second wafer comprising a second portion of the seal ring structure within a body of the second wafer. the second wafer is affixed to the first wafer such that the second portion of the seal ring structure is on the first portion of the seal ring structure. the semiconductor device includes a trench structure comprising a first trench in the first wafer and a second trench in the second wafer, where the first trench and the second trench are on a same side of the seal ring structure.
Inventor(s): Wen-Yi Lin of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Kan-Ju Yang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kai-Cheng Chen of Taoyuan TW for taiwan semiconductor manufacturing co., ltd., Chien-Li Kuo of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chien-Chen Li of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/29, H01L23/31
CPC Code(s): H01L24/05
Abstract: a semiconductor package includes: a die having a conductive pad at a first side of the die; and a redistribution structure over the first side of the die and electrically coupled to the die. the redistribution structure includes: a first dielectric layer including a first dielectric material; a first via in the first dielectric layer, where the first via is electrically coupled to the conductive pad of the die; and a first dielectric structure embedded in the first dielectric layer, where the first dielectric structure includes a second dielectric material different from the first dielectric material, where the first dielectric structure laterally surrounds the first via and contacts sidewalls of the first via.
Inventor(s): Shenggao Li of Cupertino CA US for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L21/48
CPC Code(s): H01L24/17
Abstract: a method includes forming a first package component, and forming a first plurality of electrical connectors at a first surface of the first package component. the first plurality of electrical connectors are laid out as having a honeycomb pattern. a second package component is bonded to the first package component, wherein a second plurality of electrical connectors at a second surface of the second package component are bonded to the first plurality of electrical connectors.
Inventor(s): Po-Cheng Chen of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chao-Wen Shih of Zhubei City TW for taiwan semiconductor manufacturing co., ltd., Min-Chien Hsiao of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Kuo-Chiang Ting of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yen-Ming Chen of Chu-Pei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/31, H01L23/498
CPC Code(s): H01L25/0652
Abstract: an integrated circuit package and the method of forming the same are provided. the integrated circuit package may include a first die, a first gap-fill layer along sidewalls of the first die, a first bonding layer on the first die and the first gap-fill layer, and a first die connector in the first bonding layer. the first die connector may be directly over an interface between the first die and the first gap-fill layer.
Inventor(s): Kuo-Ming WU of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Ru-Liang LEE of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Sheng-Chau CHEN of Tainan City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/552, H01L25/00
CPC Code(s): H01L25/0657
Abstract: a semiconductor device is formed by bonding a first semiconductor die and a second semiconductor die at bonding pads in the first semiconductor die with bonding vias in the second semiconductor die, and by bonding dielectric layers in the first semiconductor die and in the second semiconductor die. omitting bonding pads from the second semiconductor device, and instead using the bonding vias to bond the first and second semiconductor dies, provides a greater amount of spacing between the bonding vias of the second semiconductor die in that the bonding vias have lesser widths than bonding pads. this enables a greater amount of dielectric material of the dielectric layers of the second semiconductor device to be placed between the bonding vias without (or with minimally) increasing the lateral size of the second semiconductor die.
Inventor(s): Hsien-Wei Chen of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Ching-Jung Yang of Taoyuan City TW for taiwan semiconductor manufacturing co., ltd., Ming-Fa Chen of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Sung-Feng Yeh of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Ying-Ju Chen of Yunlin County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/768, H01L23/00, H01L25/00
CPC Code(s): H01L25/0657
Abstract: a package structure includes first and second dies, an insulation structure, a through via, a dielectric layer and a redistribution layer. the second die is electrically bonded to the first die and includes a through substrate via. the insulation structure is disposed on the first die and laterally surrounds the second die. the through via penetrates through the insulation structure to electrically connect to the first die. the redistribution layer is embedded in the dielectric layer and electrically connected to the through via, and the redistribution layer includes a barrier layer and a conductive layer. the conductive layer of the redistribution layer continuously extends between opposite surfaces of the dielectric layer, and a conductive post of the through via extends from the surface of the dielectric layer towards the first die, and the conductive layer of the redistribution layer is separated from the through substrate via by the barrier layer.
Inventor(s): Wei-Yu Chen of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Cheng-Shiuan Wong of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chia-Shen Cheng of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Hsuan-Ting Kuo of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Hao-Jan Pei of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hsiu-Jen Lin of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/16, H01L21/56, H01L23/00, H01L23/31, H10B80/00
CPC Code(s): H01L25/167
Abstract: a semiconductor package includes a semiconductor element, at least one electronic die, at least one optical die, an encapsulant, and a substrate. the semiconductor element has a first side and a second side opposing to the first side. the at least one electronic die is disposed over the first side. the at least one optical die is disposed over the first side and next to the at least one electronic die. the encapsulant is disposed on the first side and covers the at least one electronic die, where a sidewall of the at least one optical die is distant from the encapsulant, and a sidewall of the encapsulant is aligned with a sidewall of the semiconductor element. the substrate is disposed over the second side, where the at least one electronic die is electrically coupled to the substrate and the at least one optical die through the semiconductor element.
Inventor(s): Cheng Han Lu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chia-Fu Lee of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Yen-An Chang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H02M3/07, G11C11/413
CPC Code(s): H02M3/07
Abstract: a circuit is disclosed. the circuit includes a first pump circuit configured to receive a first reference voltage and provide an output voltage at a first level based on the first reference voltage. the circuit includes a second pump circuit configured to receive a second reference voltage and provide the output voltage at a second level based on the second reference voltage. the first reference voltage is lower than the second reference voltage, and the first level is lower than the second level.
Inventor(s): Jack LIU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K19/094, G06F30/392, H03K3/037, H03K19/21
CPC Code(s): H03K19/094
Abstract: an ic device includes a first interconnect structure configured to distribute a power supply voltage, a second interconnect structure configured to distribute a reference voltage, a third interconnect structure configured to distribute a first power gating signal, and a plurality of logic circuits. each logic circuit of the plurality of logic circuits includes a power switch coupled in series with a logic gate between the first and second interconnect structures, and the power switch includes a control terminal coupled to the third interconnect structure.
Inventor(s): John S. WERNER of Fishkill NY US for taiwan semiconductor manufacturing co., ltd., Arkadiy O. TSFASMAN of Wappingers Falls NY US for taiwan semiconductor manufacturing co., ltd., Sagarika MUKESH of Albany NY US for taiwan semiconductor manufacturing co., ltd., Dong Hyun KIM of Stoneham MA US for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H04L65/80, H04L43/0811, H04L65/1089, H04L65/613
CPC Code(s): H04L65/80
Abstract: some implementations described herein provide apparatuses and techniques for correcting a network disruption during a virtual meeting. in response to detecting audio and/or video input to a first device, audio and/or video data is recorded and stored in a temporary buffer of the first device. after the network disruption, and using time stamps, a network disruption server may request the audio and/or video data from the first device and transmit the audio and/or video data to a second device at an accelerated rate.
Inventor(s): Meng-Sheng Chang of Chubei City TW for taiwan semiconductor manufacturing co., ltd., Chia-En Huang of Xinfeng Township TW for taiwan semiconductor manufacturing co., ltd., Yi-Hsun Chiu of Zhubei City TW for taiwan semiconductor manufacturing co., ltd., Yih Wang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/12
Abstract: a memory cell is disclosed. the memory cell includes a first transistor. the first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. the memory cell includes a second transistor electrically coupled to the first transistor in series. the second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. at least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.
Inventor(s): Feng-Ming Chang of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Jui-Lin Chen of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Ping-Wei Wang of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Jui-Wen Chang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Lien-Jung Hung of Taipei TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: a semiconductor structure according to the present disclosure includes a first memory array in a first cache and a second memory array in a second cache. the first memory array includes a plurality of first memory cells arranged in m rows and n columns. the second memory array includes a plurality of second memory cells arranged in m rows and n columns. the semiconductor structure also includes a first bit line coupled to a number of n first memory cells in one of the m rows, and a second bit line coupled to a number of n second memory cells in one of the m rows. n is smaller than n and a width of the first bit line is smaller than a width of the second bit line.
Inventor(s): Meng-Sheng Chang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chia-En Huang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yih Wang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B20/00, G11C17/18, H10B20/25
CPC Code(s): H10B20/60
Abstract: a memory device including a substrate, a sense amplifier that includes first gate-all-around transistors that have first drain/source regions that extend into the substrate, and bit cells that include fuse memory elements and second gate-all-around transistors. each of the bit cells includes a fuse memory element having a first terminal connected to an input of the sense amplifier and a second terminal connected to a second gate-all-around transistor that includes second drain/source regions and a bottom dielectric isolation layer under the second drain/source regions.
Inventor(s): Kuo-Chang Chiang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Hung-Chang Sun of Kaohsiung TW for taiwan semiconductor manufacturing co., ltd., Sheng-Chih Lai of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., TsuChing Yang of Taipei TW for taiwan semiconductor manufacturing co., ltd., Yu-Wei Jiang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B51/20, H10B51/10, H10D30/67
CPC Code(s): H10B51/20
Abstract: a memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (os) layer contacting a source line and a bit line, wherein the memory film is disposed between the os layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the os layer, and wherein the first conductive material has a work function less than 4.6. the memory cell further includes a dielectric material separating the source line and the bit line.
Inventor(s): Katherine H. Chiang of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chung-Te Lin of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Mauricio Manfrini of Zhubei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B61/00, G11C11/16, H10N50/01, H10N50/80
CPC Code(s): H10B61/10
Abstract: in some embodiments, the present disclosure relates to an integrated chip. the integrated chip includes a memory device disposed within an inter-level dielectric (ild) structure over a substrate. the memory device has a data storage structure between a first electrode and a second electrode. a first unidirectional current controller and a second unidirectional current controller are disposed within the ild structure. a conductor arranged between the first unidirectional current controller and the data storage structure along a first conductive path and further arranged between the second unidirectional current controller and the data storage structure along a second conductive path. a part of the first conductive path overlaps a part, but not all, of the second conductive path.
Inventor(s): Liang-Hsiang Chen of Taichung TW for taiwan semiconductor manufacturing co., ltd., Chinyu Su of Taichung TW for taiwan semiconductor manufacturing co., ltd., Che-Chih Hsu of Taichung TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10D1/47
CPC Code(s): H10D1/47
Abstract: a method of forming a semiconductor device is disclosed. the method includes forming a plurality of isolation regions on a semiconductor substrate, forming a protective layer in a resistor region of the semiconductor substrate, after forming the protective layer, etching a gate dielectric layer to form first and second gate dielectric layers of a transistor in a transistor region of the semiconductor substrate, removing the protective layer, forming first and second dummy gate stacks over the first and second gate dielectric layers, respectively, forming a resistor in the resistor region, forming third and fourth dummy gate stacks over the resistor, and replacing each of the first, second, third, and fourth dummy gate stacks with a conductive material.
Inventor(s): Ching-Feng Fu of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Guan-Ren Wang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yun-Min Chang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yu-Lien Huang of Jhubei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/768, H01L21/8234, H01L29/06, H01L29/66
CPC Code(s): H10D30/62
Abstract: a semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. in embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. in other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.
Inventor(s): Shi Ning Ju of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng Chiang of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Guan-Lin Chen of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10D30/67, H10D30/00, H10D62/10, H10D84/83
CPC Code(s): H10D30/6217
Abstract: a semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.
Inventor(s): Chen-Ming Lee of Taoyuan County TW for taiwan semiconductor manufacturing co., ltd., Shih-Chieh Wu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Po-Yu Huang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., I-Wen Wu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Fu-Kai Yang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Mei-Yun Wang of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D30/6729
Abstract: one aspect of the present disclosure pertains to a semiconductor device. the semiconductor device includes a semiconductor substrate and a transistor formed over the semiconductor substrate. the transistor includes a first source/drain (s/d) feature, a second s/d feature, a channel region interposed between the first and second s/d features, and a gate stack engaging the channel region. the semiconductor device includes a first s/d contact landing on a top surface of the first s/d feature, a second s/d contact landing on a top surface of the second s/d feature, and a dielectric plug penetrating through the semiconductor substrate and landing on a bottom surface of the first s/d feature. the dielectric plug spans a width equal to or smaller than a width of the first s/d feature.
Inventor(s): Chun-Fu LU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Lung-Kun CHU of New Taipei TW for taiwan semiconductor manufacturing co., ltd., Jia-Ni YU of New Taipei TW for taiwan semiconductor manufacturing co., ltd., Chung-Wei HSU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shih-Hao LAI of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/06, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D30/6735
Abstract: a semiconductor device structure and methods of forming the same are described. the structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer, wherein the first gate spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface of the first gate spacer.
20250120138. SEMICONDUCTOR DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Yu-Lin YANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chao-Ching CHENG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Tzu-Chiang CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., I-Sheng CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10D62/10, H10D30/00, H10D62/13
CPC Code(s): H10D62/116
Abstract: in a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. a sacrificial gate structure is formed over the fin structure. the first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. a dielectric layer is formed over the etched upper portion of the fin structure. a source/drain epitaxial layer is formed. the source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.
Inventor(s): Chun-Fai CHENG of Tin Shui Wa HK for taiwan semiconductor manufacturing co., ltd., Liang-Yi CHEN of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chi-An WANG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Kuan-Chung CHEN of Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chih-Wei LEE of New Taipei City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10D64/66, H10D30/00, H10D84/83
CPC Code(s): H10D62/118
Abstract: a semiconductor device structure includes nanostructures formed over a substrate. the structure also includes a fin isolation structure formed beside the nanostructures. the structure also includes a work function layer surrounding the nanostructures and covering a sidewall of the fin isolation structure. the structure also includes a gate electrode layer covering the work function layer. the gate electrode layer has an extending portion surrounded by the work function layer.
Inventor(s): Bau-Ming Wang of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Che-Fu Chiu of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chun-Feng Nieh of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Huicheng Chang of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Yee-Chia Yeo of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10D84/01, H01L21/265, H01L21/266, H10D62/00, H10D62/17, H10D84/85
CPC Code(s): H10D62/371
Abstract: a method of forming a semiconductor device includes implanting dopants of a first conductivity type into a semiconductor substrate to form a first well, epitaxially growing a channel layer over the semiconductor substrate, forming a fin from the second semiconductor material, and forming a gate structure over a channel region of the fin. the semiconductor substrate includes a first semiconductor material. implanting the dopants may be performed at a temperature in a range of 150� c. to 500� c. the channel layer may include a second semiconductor material. the channel layer may be doped with dopants of the first conductivity type.
Inventor(s): KUEI-YU KAO of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Shih-Yao LIN of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chen-Ping Chen of Toucheng Township TW for taiwan semiconductor manufacturing co., ltd., Chih-Han Lin of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., MING-CHING CHANG of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., CHAO-CHENG CHEN of Hsin-Chu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10D64/01, H10D30/01, H10D30/67, H10D62/10
CPC Code(s): H10D64/01
Abstract: a method of fabricating a semiconductor structure includes forming a recess in an active channel structure by removing a portion thereof, filling the recess with a dielectric material, forming a cladding layer adjacent the active channel structure but not adjacent the dielectric material, and forming a gate structure comprising a first gate structure and a second gate structure around the active channel structure. a width of the dielectric material in the recess is greater than a width of the first gate structure and a width of the second gate structure.
Inventor(s): Kong-Beng Thei of Pao-Shan Village TW for taiwan semiconductor manufacturing co., ltd., Chien-Chih Chou of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Hsiao-Chin Tuan of Taowan TW for taiwan semiconductor manufacturing co., ltd., Yi-Huan Chen of Hsin Chu City TW for taiwan semiconductor manufacturing co., ltd., Alexander Kalnitsky of San Francisco CA US for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10D62/10, H10D64/60
CPC Code(s): H10D64/021
Abstract: in some embodiments, an integrated chip is provided. the integrated chip includes a source region and a drain region disposed in a substrate. a gate is disposed over the substrate and between the source region and the drain region. a silicide structure is disposed over the drain region. a first silicide blocking segment and a second silicide blocking segment are disposed directly over the drain region. the silicide structure continuously extends over the drain region from a first sidewall contacting the first silicide blocking segment to a second sidewall contacting the second silicide blocking segment, in a cross-sectional view.
Inventor(s): Kuan-Jung CHEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chun-Ming LIN of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Tsung-Lin LEE of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Shiuan-Jeng LIN of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Hung-Lin CHEN of Pingtung City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10D10/40, H10D10/01, H10D62/10, H10D62/13, H10D62/17
CPC Code(s): H10D64/231
Abstract: bipolar junction transistor (bjt) structures are provided. a bjt structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a plurality of base regions formed over the collector region, a plurality of emitter regions formed over the collector region, a ring-shaped shallow trench isolation (sti) region formed in the collector region, a plurality of base conductive layers formed over the collector region and on opposite sides of the base regions, a plurality of sidewall dielectric layers formed on top surfaces of the base conductive layers and disposed vertically between the base conductive layers and upper portions of the emitter regions, and a plurality of base contacts formed on the base conductive layers. the base contacts are divided into a first group of base contacts disposed between the base regions and a second group of base contacts disposed between the base regions and the sti region.
Inventor(s): Chung-Wei Hsu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng Chiang of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsin-Chu TW for taiwan semiconductor manufacturing co., ltd., Hou-Yu Chen of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Ching-Wei Tsai of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Lung-Kun Chu of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Mao-Lin Huang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Jia-Ni Yu of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/28, H01L21/311, H01L27/092, H01L29/06, H01L29/423, H01L29/49, H01L29/51, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H10D84/038
Abstract: semiconductor device and the manufacturing method thereof are disclosed. an exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.
Inventor(s): Kuei-Yu Kao of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chao-Cheng Chen of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chih-Han Lin of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Chen-Ping Chen of Toucheng Township TW for taiwan semiconductor manufacturing co., ltd., Ming-Ching Chang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Shih-Yao Lin of New Taipei City TW for taiwan semiconductor manufacturing co., ltd., Chih-Chung Chiu of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H10D84/038
Abstract: a semiconductor device includes a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface, and an etch stop layer extends between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer.
Inventor(s): Chun Hsiung Tsai of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd., Ziwei Fang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Tsan-Chun Wang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Kei-Wei Chen of Tainan City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10D84/83, H01L21/306, H01L21/311, H01L21/762, H10D30/01, H10D30/62, H10D30/69, H10D62/10, H10D62/13, H10D64/01, H10D84/01, H10D84/03
CPC Code(s): H10D84/834
Abstract: a fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. the substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. the at least one gate stack is disposed over the insulators and over the channel portions of the fins. the epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. the epitaxy material portions disposed on the flank portions of the fins are separate from one another.
Inventor(s): Jia-Chuan YOU of Taoyuan TW for taiwan semiconductor manufacturing co., ltd., Shi-Ning JU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/528
CPC Code(s): H10D84/834
Abstract: a semiconductor device structure, along with methods of forming such, are described. the structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. the dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.
Inventor(s): Ta-Pen GUO of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Lee-Chung LU of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Li-Chun TIEN of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/02
CPC Code(s): H10D84/907
Abstract: a semiconductor device includes a plurality of standard cells. the plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. the first group of standard cells and the second group of standard cells are arranged in a column direction. a cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.
Inventor(s): Yu-Lung Tung of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Xiaodong Wang of Hsinchu City TW for taiwan semiconductor manufacturing co., ltd., Jhon Jhy Liaw of Hsinchu County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/02, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10D89/10
Abstract: a semiconductor structure includes first standard cells having first active regions formed over first alternating n-type and p-type wells, the first active regions and the first alternating n-type and p-type wells each extends lengthwise along a first direction, each of the first standard cells includes a first n-type well and a first p-type well; and second standard cells adjacent to the first standard cells, the second standard cells having second active regions formed over second alternating n-type and p-type wells, the second active regions and the second alternating n-type and p-type wells each extends lengthwise along the first direction, each of the second standard cells includes a second n-type well and a second p-type well. the first standard cells have a first cell height, the second standard cells have a second cell height, and the second cell height is greater than the first cell height.
Inventor(s): Ming-Hsien YANG of Taichung City TW for taiwan semiconductor manufacturing co., ltd., Kun-Hui LIN of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Chun-Hao CHOU of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng LEE of Tainan City TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146, G01S7/481, G01S17/894
CPC Code(s): H10F39/8027
Abstract: a pixel sensor array may include a plurality of pixel sensors configured to generate color information associated with incident light, and a time of flight (tof) sensor circuit configured to generate distance information associated with the incident light. the color information and the distance information may be used to generate a three-dimensional (3d) tof color image. the tof sensor circuit may be included under a dti structure surrounding the plurality of pixel sensors in a top view of the pixel sensor array.
Inventor(s): Shu-Ting Tsai of Kaohsiung City TW for taiwan semiconductor manufacturing co., ltd., Tzu-Jui Wang of Fengshan City TW for taiwan semiconductor manufacturing co., ltd., U-Ting Chen of Wanluan Township TW for taiwan semiconductor manufacturing co., ltd., Shyh-Fann Ting of Tainan City TW for taiwan semiconductor manufacturing co., ltd., Szu-Ying Chen of Miaoli County TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/807
Abstract: the problem of forming a deep trench isolation structure suitable for photodetectors with small pitch is solved by a process in which a grid of trenches is etched from the front side using high energy plasma followed by annealing. the trenches are filled with an oxide followed by etching to recess the oxide. the trench recesses are filled with semiconductor to form a grid-shaped semiconductor structure. after feol processing, beol processing, attachment to a second substrate, and thinning from the back side, an etch removes the oxide from the back side. the etch stops on the grid-shaped semiconductor structure. the trenches are then lined and filled from the back side. the front side etch allows the trenches to be made narrow and with highly vertical sidewalls. lining and filling the trenches from the back side provides good optical and electrical isolation.
Inventor(s): Nien-Yu Tai of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Kuo-Feng Huang of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yi-Jen HUANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., Yu-Jen WANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd., HARRY-HAKLAY CHUANG of Hsinchu TW for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N50/80, G11C11/16, H10B61/00, H10N50/01, H10N50/10
CPC Code(s): H10N50/80
Abstract: a semiconductor device includes a plurality of interlayer dielectric layers, a memory cell, and a first capping layer. the memory cell is embedded in the interlayer dielectric layers, the first capping layer covers the memory cell and surrounds the sidewalls of the memory cell, the first capping layer includes a hydrogen absorbing material, and the hydrogen absorbing material prevents hydrogen gas from entering the memory cell.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on April 10th, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- B05B1/00
- B05B13/02
- CPC B05B1/002
- Taiwan semiconductor manufacturing co., ltd.
- B24B41/00
- B24B29/00
- B24B49/18
- CPC B24B41/005
- G01R31/28
- CPC G01R31/2877
- G03F7/039
- G03F7/038
- CPC G03F7/039
- C08F212/14
- C08F220/18
- C08F220/38
- G03F7/40
- G03F7/00
- H01L21/027
- H01L29/66
- CPC G03F7/40
- G03F7/20
- CPC G03F7/70033
- G05F1/575
- G05F1/565
- G05F1/59
- CPC G05F1/575
- G06F7/544
- CPC G06F7/5443
- G06F30/392
- G06F30/3953
- G06F119/06
- H01L23/522
- H10D62/10
- CPC G06F30/392
- G06F30/337
- G06F30/394
- G06F30/3947
- G06F30/398
- H01L23/528
- H01L23/532
- H10D84/90
- CPC G06F30/398
- G06N3/063
- G06N3/08
- G11C7/10
- G11C11/54
- G11C29/04
- CPC G06N3/063
- G11C13/00
- CPC G11C7/1096
- G11C7/22
- G11C7/12
- G11C8/08
- G11C8/10
- CPC G11C7/12
- G11C11/419
- G11C5/06
- H10B10/00
- CPC G11C11/419
- G11C11/16
- G11C11/22
- CPC G11C13/0069
- G11C17/16
- G11C17/18
- H10B20/25
- CPC G11C17/16
- H01L21/02
- H01L29/778
- CPC H01L21/02178
- H01L21/033
- H01L21/8234
- H01L29/423
- CPC H01L21/0337
- H01L21/311
- C23C16/26
- C23C16/505
- C23C16/56
- H01J37/32
- H01L21/308
- CPC H01L21/31144
- H01L25/18
- H01L21/66
- H01L23/00
- H10B80/00
- CPC H01L21/563
- H01L21/683
- H01J37/317
- CPC H01L21/683
- H10D88/00
- CPC H01L21/6833
- H01L21/768
- CPC H01L21/76816
- CPC H01L21/7682
- H01L23/535
- CPC H01L21/76843
- H01L23/58
- CPC H01L23/10
- H01L23/18
- H01L21/56
- H01L23/31
- CPC H01L23/18
- H01L23/498
- H01L25/00
- H01L25/065
- CPC H01L23/3128
- G02B6/42
- H01L25/16
- CPC H01L23/3178
- H01L23/367
- H01L21/48
- H01L23/373
- CPC H01L23/3677
- H01L23/48
- CPC H01L23/481
- G02B6/12
- CPC H01L23/49816
- CPC H01L23/5223
- H01L27/02
- H01L29/417
- H01L29/78
- CPC H01L23/5226
- H01L21/8238
- H01L27/092
- H01L29/06
- H01L29/775
- H01L29/786
- H10D1/20
- CPC H01L23/5227
- CPC H01L23/5283
- CPC H01L23/5286
- H01L23/485
- H10D64/01
- H10D84/01
- H10D84/03
- H10D84/83
- H10D89/10
- H01L23/538
- CPC H01L23/5389
- H01L23/544
- H01L21/3105
- CPC H01L23/544
- H01L25/07
- H01L23/053
- H01L23/29
- CPC H01L23/562
- CPC H01L24/05
- CPC H01L24/17
- CPC H01L25/0652
- H01L23/552
- CPC H01L25/0657
- CPC H01L25/167
- H02M3/07
- G11C11/413
- CPC H02M3/07
- H03K19/094
- H03K3/037
- H03K19/21
- CPC H03K19/094
- H04L65/80
- H04L43/0811
- H04L65/1089
- H04L65/613
- CPC H04L65/80
- CPC H10B10/12
- CPC H10B10/125
- H10B20/00
- CPC H10B20/60
- H10B51/20
- H10B51/10
- H10D30/67
- CPC H10B51/20
- H10B61/00
- H10N50/01
- H10N50/80
- CPC H10B61/10
- H10D1/47
- CPC H10D1/47
- CPC H10D30/62
- H10D30/00
- CPC H10D30/6217
- CPC H10D30/6729
- H01L27/088
- CPC H10D30/6735
- H10D62/13
- CPC H10D62/116
- H10D64/66
- CPC H10D62/118
- H01L21/265
- H01L21/266
- H10D62/00
- H10D62/17
- H10D84/85
- CPC H10D62/371
- H10D30/01
- CPC H10D64/01
- H10D64/60
- CPC H10D64/021
- H10D10/40
- H10D10/01
- CPC H10D64/231
- H01L21/28
- H01L29/49
- H01L29/51
- CPC H10D84/038
- H01L21/306
- H01L21/762
- H10D30/62
- H10D30/69
- CPC H10D84/834
- CPC H10D84/907
- CPC H10D89/10
- H01L27/146
- G01S7/481
- G01S17/894
- CPC H10F39/8027
- CPC H10F39/807
- H10N50/10
- CPC H10N50/80