TEXAS INSTRUMENTS INCORPORATED patent applications on May 1st, 2025

Patent Applications by TEXAS INSTRUMENTS INCORPORATED on May 1st, 2025

TEXAS INSTRUMENTS INCORPORATED: 46 patent applications

TEXAS INSTRUMENTS INCORPORATED has applied for patents in the areas of H01L23/00 (12), H01L23/31 (7), H01L21/56 (6), H01L21/48 (4), H01L29/66 (4) B07C5/38 (1), H03M1/12 (1), H02M1/0009 (1), H02M3/07 (1), H02P21/34 (1)

With keywords such as: terminal, coupled, circuitry, package, having, semiconductor, layer, substrate, input, and including in patent application abstracts.

Patent Applications by TEXAS INSTRUMENTS INCORPORATED

20250135501. COVER PLATE FOR A POKA-YOKE BULK BIN SYSTEM_simplified_abstract_(texas instruments incorporated)

Inventor(s): Eng How CHEAH of MELAKA ML for texas instruments incorporated, Kean Pin NG of KANGAR ML for texas instruments incorporated

IPC Code(s): B07C5/38, B65D19/06

CPC Code(s): B07C5/38

Abstract: one example includes a bulk bin system. the system includes a bin receptable comprising a first poka-yoke mating feature and a bulk bin configured to accommodate storage of bulk components. the bulk bin can be configured to rest on the bin receptacle and includes a second poka-yoke mating feature extending from an inner surface of the bulk bin. the second poka-yoke mating feature can be configured to engage with the first poka-yoke mating feature when the bulk bin is provided in the bin receptacle. the system further comprises a cover plate that is secured to the bulk bin via a securing feature. the cover plate includes a cover portion that extends along and is approximately aligned with the inner surface of the bulk bin to cover the second poka-yoke mating feature.

20250138054. SEMICONDUCTOR DEVICE PACKAGE WITH INTERNAL MAGNETIC SHIELD FOR HALL SENSOR_simplified_abstract_(texas instruments incorporated)

Inventor(s): Yi Yan of San Jose CA US for texas instruments incorporated, Dok Won Lee of Mountain View CA US for texas instruments incorporated, Hank Ming Sung of Sachse TX US for texas instruments incorporated, Kenji Otake of Nagano JP for texas instruments incorporated

IPC Code(s): G01R15/20, G01R19/00, H10N52/01, H10N52/80

CPC Code(s): G01R15/202

Abstract: a described example includes: a heat slug coupled to a package substrate, the heat slug configured to conduct a current between terminals of the package substrate; a first magnetic shield mounted to a top surface of the package substrate, the first magnetic shield including a die mount area; a semiconductor die flip chip mounted to the die mount area; a second magnetic shield mounted to the package substrate, the second magnetic shield having a cantilever portion extending over a portion of the semiconductor die including a hall element; electrical connections of wire bonds or ribbon bonds between bond pads of the semiconductor die and leads on the package substrate; and mold compound covering the electrical connections, the semiconductor die, the first magnetic shield, and the second magnetic shield, while a portion of the heat slug is exposed forming a thermal pad for a semiconductor device package.

20250138087. TEST LOAD BOARD_simplified_abstract_(texas instruments incorporated)

Inventor(s): PASTOR JOSE YLLANA, JR. of BAGUIO CITY PH for texas instruments incorporated, DALE OHMART of RICHMOND TX US for texas instruments incorporated

IPC Code(s): G01R31/28, G06K19/07

CPC Code(s): G01R31/2896

Abstract: a test load board includes a pcb (printed circuit board) with pads for a probe of a tester. the test load board also includes a contactor that includes contact points for connecting leads of a dut (device under test). the test load board further includes an rfid (radio frequency identification) tag affixed to the pcb. the rfid tag is loaded with a unique identifier (id) of the test load board.

20250138148. FMCW RADAR SYSTEM WITH CHIRP JITTER REDUCTION_simplified_abstract_(texas instruments incorporated)

Inventor(s): Karthik Subburaj of Bangalore IN for texas instruments incorporated, Piyush Soni of Bangalore IN for texas instruments incorporated, Vashishth Dudhia of AHMEDABAD IN for texas instruments incorporated, Ryan Smith of Lucas TX US for texas instruments incorporated, Kavithaa Rajagopalan of Bangalore IN for texas instruments incorporated, Karthik Ramasubramanian of Bangalore IN for texas instruments incorporated, Shankar Ram Narayana Moorthy of Bangalore IN for texas instruments incorporated, Indu Prathapan of Bangalore IN for texas instruments incorporated, Samala Sreekiran of Plano TX US for texas instruments incorporated

IPC Code(s): G01S7/40, G01S13/32

CPC Code(s): G01S7/4056

Abstract: in described examples, a frequency modulated continuous wave (fmcw) radar includes a reference clock, a phase locked loop (pll), a pulse generator, a counter, a chirp ramp control circuit, and a synchronization state machine. the reference clock generates a reference clock signal. the pll generates a feedback clock signal in response to the reference clock signal, and an output signal in response to the feedback clock signal. the pulse generator outputs a chirp start pulse in response to the reference clock signal. the counter increments a count in response to the feedback clock signal. the synchronization state machine provides a chirp ramp signal to a chirp ramp control circuit in response to the reference clock signal, the feedback clock signal, the chirp start pulse, and the count. the chirp ramp control circuit causes the pll to ramp a frequency of the output signal in response to the chirp ramp signal.

20250138567. METHODS AND APPARATUS TO REGULATE TRANSISTOR SWITCHING_simplified_abstract_(texas instruments incorporated)

Inventor(s): Cetin Kaya of McKinney TX US for texas instruments incorporated, FNU Nitish of Dallas TX US for texas instruments incorporated, Maik Peter Kaufmann of Freising DE for texas instruments incorporated

IPC Code(s): G05F3/26, H02P7/28, H03K17/693

CPC Code(s): G05F3/267

Abstract: an example apparatus includes: driver circuitry having a terminal; a capacitor having a terminal; diode circuitry having a first terminal and a second terminal; a transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the transistor coupled to the first terminal of the diode circuitry, the control terminal of the transistor coupled to the terminal of the capacitor and the second terminal of the diode circuitry; and current mirror circuitry having a first terminal and second terminal, the first terminal of the current mirror circuitry coupled to the terminal of the driver circuitry, the second terminal of the current mirror circuitry coupled to the second terminal of the transistor.

20250138825. PREFETCHING PROGRAM CODE FROM FLASH MEMORY BASED ON BRANCH LOGIC_simplified_abstract_(texas instruments incorporated)

Inventor(s): Veeramanikandan Raju of Bangalore IN for texas instruments incorporated, Mihir Mody of Bangalore IN for texas instruments incorporated, Shailesh Ghotgalkar of Bangalore IN for texas instruments incorporated

IPC Code(s): G06F9/30, G06F11/07

CPC Code(s): G06F9/30047

Abstract: a system for prefetching program code from flash memory that includes processing circuitry configured to execute program code and prefetch circuitry coupled to the processing circuitry. in an implementation, the prefetch circuitry is configured to analyze branch logic within the program code to identify a block of code to prefetch from flash memory. once identified, the prefetch circuitry causes the block of code to be prefetched from flash memory and loaded to a memory buffer. in another implementation, the prefetch circuitry is further configured to receive a request to supply the processing circuitry with the block of code. upon receiving the request, the prefetch circuitry determines that the block of code has already been fetched and loaded in the memory buffer. once identified in the memory buffer, the prefetch circuitry causes the block of code to be supplied to the processing circuitry.

20250139019. AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE_simplified_abstract_(texas instruments incorporated)

Inventor(s): Naveen BHORIA of Plano TX US for texas instruments incorporated, Timothy David ANDERSON of University Park TX US for texas instruments incorporated, Pete HIPPLEHEUSER of Murphy TX US for texas instruments incorporated

IPC Code(s): G06F12/128, G06F9/30, G06F9/54, G06F11/10, G06F12/02, G06F12/0802, G06F12/0804, G06F12/0806, G06F12/0811, G06F12/0815, G06F12/0817, G06F12/0853, G06F12/0855, G06F12/0864, G06F12/0884, G06F12/0888, G06F12/0891, G06F12/0895, G06F12/0897, G06F12/1027, G06F12/12, G06F12/121, G06F12/126, G06F12/127, G06F13/16, G06F15/80, G11C5/06, G11C7/10, G11C7/22, G11C29/42, G11C29/44

CPC Code(s): G06F12/128

Abstract: a caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

20250139031. DYNAMIC POWER GATING USING DETERMINISTIC INTERCONNECT_simplified_abstract_(texas instruments incorporated)

Inventor(s): Nikhil Sangani of Bangalore IN for texas instruments incorporated, Mihir Mody of Bangalore IN for texas instruments incorporated, Malav Shah of Bangalore IN for texas instruments incorporated, Athavan Arasumani of Pondicherry PY for texas instruments incorporated, Shailesh Ghotgalkar of Bangalore IN for texas instruments incorporated

IPC Code(s): G06F13/20

CPC Code(s): G06F13/20

Abstract: various examples disclosed herein relate to deterministically controlling interconnect operations to provide dynamic power gating for a system. in an example, a microcontroller unit (mcu) is provided that includes a group of processing devices, a group of target resources, interconnect circuitry, and clock control circuitry. the interconnect circuitry connects the group of processing devices to the group of target resources. the clock control circuitry is coupled to the interconnect circuitry. the clock control circuitry is configured to identify an upcoming occurrence of a communication between a pair of devices comprised of one of the processing devices and one of the target resources, and prior to the occurrence of the communication, enable a clock associated with a path through the interconnect circuitry between the pair of devices.

20250139035. TRANSMIT AND RECEIVE CIRCUITS WITH MULTIPLE INTERFACES_simplified_abstract_(texas instruments incorporated)

Inventor(s): Chunhua HU of Plano TX US for texas instruments incorporated, Sanand PRASAD of Plano TX US for texas instruments incorporated

IPC Code(s): G06F13/28, G06F13/42

CPC Code(s): G06F13/28

Abstract: a method includes transmitting first data with a first priority through a first dedicated interface on a transmit side of a pcie system. the method also includes transmitting second data with a second priority through a second dedicated interface on the transmit side of the pcie system. the method includes transmitting the first data and the second data to a receive side of the pcie system using two or more virtual channels over a pcie link, where the first data uses a first virtual channel and the second data uses a second virtual channel.

20250139038. METHODS AND APPARATUS TO DETECT L2 ENTRY AND RESET IN UNIVERSAL SERIAL BUS REPEATERS_simplified_abstract_(texas instruments incorporated)

Inventor(s): Anant Kamath of Bangalore IN for texas instruments incorporated, Suzanne M. Vining of Plano TX US for texas instruments incorporated, Rakesh Hariharan of Bangalore IN for texas instruments incorporated, Mark Wentroble of Plano TX US for texas instruments incorporated, Christopher Rodrigues of Bangalore IN for texas instruments incorporated, Prajwala P of Cambridge GB for texas instruments incorporated

IPC Code(s): G06F13/38, G06F13/40

CPC Code(s): G06F13/385

Abstract: an example apparatus includes: a pullup circuit coupled to a first usb terminal; a first pulldown circuit coupled to the first usb terminal; a second pulldown circuit coupled to a second usb terminal; a third pulldown circuit coupled to a third usb terminal; a fourth pulldown circuit coupled to a fourth usb terminal; a high-speed termination detection circuit including: a current source including a first supply terminal and a second supply terminal, the first supply terminal coupled to the first usb terminal, the second supply terminal coupled to the second usb terminal; a first comparator including a first comparator terminal and a second comparator terminal, the first comparator terminal coupled to the first usb terminal; and a second comparator including a third comparator terminal and a fourth comparator terminal, the third comparator terminal coupled to the second usb terminal; and a controller including a first control terminal and a second control terminal, the first control terminal coupled to the second comparator terminal, the second control terminal coupled to the fourth comparator terminal.

20250139302. HARDWARE PROTECTION OF INLINE CRYPTOGRAPHIC PROCESSOR_simplified_abstract_(texas instruments incorporated)

Inventor(s): Amritpal S. Mundra of Allen TX US for texas instruments incorporated, William C. Wallace of Richardson TX US for texas instruments incorporated

IPC Code(s): G06F21/79, G06F12/14, G06F21/60, G06F21/62

CPC Code(s): G06F21/79

Abstract: a real time, on-the-fly data encryption system is operable to encrypt and decrypt data flow between a secure processor and an unsecure external memory systen. multiple memory segments are supported, each with its own separate encryption capability, or no encryption at all. data integrity is ensured by hardware protection from code attempting to access data across memory segment boundaries. protection is also provided against dictionary attacks by monitoring multiple access attempts to the same memory location.

20250140560. INTEGRATED CIRCUIT (IC) WITH CORRUGATED CHANNEL STRUCTURE_simplified_abstract_(texas instruments incorporated)

Inventor(s): Jackson Bauer of Rowlett TX US for texas instruments incorporated, Sheldon Douglas Haynie of Dallas TX US for texas instruments incorporated, John Arch of Richardson TX US for texas instruments incorporated, Asad Haider of Plano TX US for texas instruments incorporated

IPC Code(s): H01L21/266, H01L21/265, H01L29/10, H01L29/66, H01L29/78

CPC Code(s): H01L21/266

Abstract: an integrated circuit (ic) device including one or more corrugated channel structures formed in a top portion of a semiconductor substrate, where a corrugated channel structure includes a first sidewall, a second sidewall and an upper portion. in an example, the corrugated channel structure is provided with a substantially uniform distribution profile of a dopant across a horizontal plane from the first sidewall to the second sidewall.

20250140620. ELECTROSTATIC DISCHARGE DEVICES WITH METALLIZED DIES_simplified_abstract_(texas instruments incorporated)

Inventor(s): Thomas KRONENBERG of Dallas TX US for texas instruments incorporated, Mohammad WASEEM HUSSAIN of Irving TX US for texas instruments incorporated

IPC Code(s): H01L23/31, H01L21/56, H01L21/683, H01L23/00

CPC Code(s): H01L23/3107

Abstract: in examples, a method for manufacturing a package comprises depositing a metal contact layer on a surface of a wafer, the wafer including first and second diodes; positioning the wafer on an expandable tape coupled to a carrier; dicing the wafer to produce first and second dies, the first die including the first diode and the second die including the second diode; wire bonding the first die to the second die using a bond wire; covering the first and second dies and the bond wire with a mold compound to produce a molded structure; decoupling the molded structure from the expandable tape; and sawing the molded structure to produce the package.

20250140624. PACKAGES WITH ISOLATED DIES_simplified_abstract_(texas instruments incorporated)

Inventor(s): Hau NGUYEN of San Jose CA US for texas instruments incorporated, Vivek ARORA of San Jose CA US for texas instruments incorporated, Patrick Francis THOMPSON of Allen TX US for texas instruments incorporated, Masamitsu MATSUURA of Beppu-Shi Oita-Ken JP for texas instruments incorporated, Daiki KOMATSU of Beppu-Shi Oita-Ken JP for texas instruments incorporated

IPC Code(s): H01L23/31, H01L21/56, H01L21/78, H01L23/00, H01L23/29, H01L25/065

CPC Code(s): H01L23/3135

Abstract: a wafer chip scale package (wcsp) comprises first and second dies in differing voltage domains and an isolation material between the first and second dies and contacting multiple surfaces of each of the first and second dies. the package also comprises a first resin material contacting multiple surfaces of the isolation material, with the isolation material between the resin material and the first and second dies. the package also comprises a fiberglass material contacting a surface of the resin material and a second resin material contacting a surface of the fiberglass material. the package also comprises first and second conductive structures coupled to the first and second dies, respectively. the package also includes a passivation material contacting the first and second dies and the first and second conductive structures.

20250140626. SENSOR ELECTRONIC DEVICE_simplified_abstract_(texas instruments incorporated)

Inventor(s): Masamitsu Matsuura of BEPPU-SHI OITA-KEN JP for texas instruments incorporated, Daiki Komatsu of BEPPU-SHI OITA-KEN JP for texas instruments incorporated, Kengo Aoya of BEPPU-SHI OITA-KEN JP for texas instruments incorporated

IPC Code(s): H01L23/31, H01L21/56, H01L23/00

CPC Code(s): H01L23/315

Abstract: an electronic device includes a package structure having opposite first and second sides, opposite third and fourth sides spaced along a first direction, opposite fifth and sixth sides spaced along an orthogonal second direction, the first and second sides spaced along a third direction orthogonal to the first and second directions, and an opening extending into the first side along the third direction, a first semiconductor die having a first side exposed in the opening of the package structure and an opposite second side partially enclosed by the package structure, and a second semiconductor die electrically connected to the first semiconductor die, the second semiconductor die enclosed by the package structure and laterally spaced apart from the first semiconductor die.

20250140628. DIELECTRIC LAYER PROTRUSIONS_simplified_abstract_(texas instruments incorporated)

Inventor(s): Enis TUNCER of Dallas TX US for texas instruments incorporated

IPC Code(s): H01L23/31, H01L21/56, H01L23/00

CPC Code(s): H01L23/3192

Abstract: a package comprises a semiconductor die having a device side in which circuitry is formed and first and second metal members coupled to and extending away from the device side. the package also comprises a passivation layer contacting the device side, at least a portion of the passivation layer positioned between the first and second metal members, the passivation layer including a top surface facing away from the semiconductor die. the package further comprises multiple passivation layer protrusions (plps) coupled to and extending away from the top surface, the multiple plps having heights ranging from 0.5 microns to 50 microns.

20250140653. HYBRID QUAD FLAT PACKAGE ELECTRONIC DEVICE_simplified_abstract_(texas instruments incorporated)

Inventor(s): Anindya Poddar of Sunnyvale CA US for texas instruments incorporated, Ashok Prabhu of San Jose CA US for texas instruments incorporated, Hau Nguyen of San Jose CA US for texas instruments incorporated, Kurt Sincerbox of San Jose CA US for texas instruments incorporated, Makoto Shibuya of Tokyo JP for texas instruments incorporated

IPC Code(s): H01L23/495, H01L21/48, H01L21/56, H01L23/00, H01L23/31

CPC Code(s): H01L23/49541

Abstract: an electronic device includes opposite first and second sides, opposite third and fourth sides spaced apart along a first direction, and opposite fifth and sixth sides spaced apart along a second direction orthogonal to the first direction, the first and second sides being spaced apart along a third direction orthogonal to the first and second directions. the electronic device includes a molded package, first leads exposed outside the molded package along the first side, and the first leads extending outward from the molded package along a respective one of the third and fourth sides, and second leads exposed outside the molded package along the first side, the second leads having a lateral side exposed outside the molded package along a respective one of the fifth and sixth sides, and the lateral side of the individual second leads being flush with a respective side of the molded package.

20250140655. CAVITIES IN PACKAGE CONDUCTIVE TERMINALS_simplified_abstract_(texas instruments incorporated)

Inventor(s): Jefferson LUGUE of Baguio City PH for texas instruments incorporated, ZuoHui CHEN of Chengdu CN for texas instruments incorporated

IPC Code(s): H01L23/495, H01L21/48, H01L23/00, H01L23/31

CPC Code(s): H01L23/49555

Abstract: in examples, a package comprises a semiconductor die, a gullwing conductive terminal coupled to the semiconductor die, and a mold compound covering the semiconductor die and the conductive terminal. the conductive terminal extends outward from the mold compound. the conductive terminal includes a top surface and a bottom surface opposing the top surface, the conductive terminal includes a first bend and a second bend more distal from the mold compound than the first bend, and the bottom surface includes a first cavity extending along a width of the conductive terminal at the first bend. the top surface includes a second cavity extending along the width of the conductive terminal at the second bend.

20250140708. SEMICONDUCTOR PACKAGE WITH SHUNT AND PATTERNED METAL TRACE_simplified_abstract_(texas instruments incorporated)

Inventor(s): Yiqi Tang of Allen TX US for texas instruments incorporated, Rajen Manicon Murugan of Dallas TX US for texas instruments incorporated, Liang Wan of Chengdu CN for texas instruments incorporated, Makarand Ramkrishna Kulkarni of Dallas TX US for texas instruments incorporated, Jie Chen of Plano TX US for texas instruments incorporated, Steven Alfred Kummerl of Carrollton TX US for texas instruments incorporated

IPC Code(s): H01L23/538, H01L21/48, H01L23/00

CPC Code(s): H01L23/5389

Abstract: a semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. the semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. the metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. the semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

20250140718. DIELECTRIC-FILLED BOND PADS IN CLIP PACKAGES_simplified_abstract_(texas instruments incorporated)

Inventor(s): Jose Arvin M. PLOMANTES of Dagupan PH for texas instruments incorporated, Jeffrey Salvacion SOLAS of Iloilo City PH for texas instruments incorporated

IPC Code(s): H01L23/00

CPC Code(s): H01L24/05

Abstract: a package comprises a semiconductor die including a device side having circuitry formed therein and a first metal member on the device side of the die and having a top surface facing away from the die. the first metal member includes a group of dielectric members, each dielectric member in the group of dielectric members extending at least partially through a thickness of the first metal member. the package also comprises solder material contacting the top surface of the first metal member and top surfaces of the dielectric members in the group of dielectric members. the package also includes a second metal member coupled to the solder material and to a conductive terminal of the package, the conductive terminal exposed to an exterior of the package.

20250140735. DIRECT COPPER WIRE BONDING ON NANOTWIN COPPER STRUCTURES_simplified_abstract_(texas instruments incorporated)

Inventor(s): Jomari AUSTRIA of Malabon City PH for texas instruments incorporated, Ray Fredric DE ASIS of Mabalacat PH for texas instruments incorporated, Jeffrey Salvacion SOLAS of Iloilo City PH for texas instruments incorporated

IPC Code(s): H01L23/00

CPC Code(s): H01L24/48

Abstract: a package comprises a semiconductor die including a device side having circuitry formed therein. the package includes a metal member coupled to the device side and a nanotwin copper member having a bottom surface coupled to the metal member, the nanotwin copper member comprising a twin boundary separating a first region having a first grain structure from a second region having a second grain structure. the package also comprises a wire bond coupled directly to a top surface of the nanotwin copper member, the wire bond contacting multiple regions of the nanotwin copper member. the package also comprises a mold compound covering the die, the metal member, the nanotwin copper member, and the wire bond.

20250140739. LASER ENHANCED WIRE BONDING FOR SEMICONDUCTOR DEVICE PACKAGES_simplified_abstract_(texas instruments incorporated)

Inventor(s): Kashyap Mohan of Irving TX US for texas instruments incorporated, Daiki Komatsu of Hiji JP for texas instruments incorporated, Amin Ahmad Sijelmassi of Dallas TX US for texas instruments incorporated

IPC Code(s): H01L23/00

CPC Code(s): H01L24/85

Abstract: an example apparatus includes: a wire bond tool including a bond wire capillary having a central opening configured for receiving a bond wire in the central opening; a first laser path formed in the capillary configured to focus a first laser beam on the end of the bond wire to form a free air ball; and a second laser path formed in the capillary configured to focus a second laser beam on a bonding location beneath the capillary.

20250140745. DIE WITH CONNECTION PAD_simplified_abstract_(texas instruments incorporated)

Inventor(s): JOSE ARVIN PLOMANTES of DAGUPAN PH for texas instruments incorporated, JEFFREY SOLAS of ILOILO CITY PH for texas instruments incorporated

IPC Code(s): H01L25/065, H01L23/00

CPC Code(s): H01L25/0655

Abstract: an ic (integrated circuit) package include an interconnect having a die attach pad and lead. the ic package also includes a die with a first side mounted on the die attach pad and a second side opposing the first side. the second side having a planar region. the planar region having selective polyimide structures between contact points of a connection pad. the ic package also includes a clip coupled to the connection pad and to a lead of the leads.

20250140769. INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED HEAT SINK_simplified_abstract_(texas instruments incorporated)

Inventor(s): Yunyi Gong of Tokyo JP for texas instruments incorporated, Kenji Otake of Nagano JP for texas instruments incorporated, Hidetoshi Inoue of Oyama-shi JP for texas instruments incorporated, Sombuddha Chakraborty of Redwood City CA US for texas instruments incorporated, Jonathan Montoya of Dallas TX US for texas instruments incorporated, Osvaldo Lopez of Annandale NJ US for texas instruments incorporated

IPC Code(s): H01L25/18, H01L21/48, H01L21/56, H01L23/00, H01L23/29, H01L23/31, H01L23/373

CPC Code(s): H01L25/18

Abstract: a packaged integrated circuit (ic) includes a package substrate and an ic on the package substrate. a first material is on the package substrate and encapsulates the ic. an inductor is coupled to the package substrate. a heat sink includes a second material. the heat sink is coupled to the ic. a third material is on the first material and encapsulates the inductor and at least part of the heat sink. the second material has a higher thermal conductivity than the first and third materials.

20250141080. DIFFERENTIAL WIDEBAND QUADRATURE SIGNAL GENERATION USING OVER-COUPLED DIRECTIONAL COUPLER_simplified_abstract_(texas instruments incorporated)

Inventor(s): Sun Hwan Jang of Allen TX US for texas instruments incorporated

IPC Code(s): H01P5/18, H03F3/19

CPC Code(s): H01P5/18

Abstract: embodiments disclosed herein relate to quadrature signal generation, and more particularly, to wideband differential quadrature signal generation at millimeter-wave frequencies using over-coupled directional couplers. in an example, a quadrature signal generation sub-circuit includes two conductive strips arranged in parallel with respect to each other on different layers of a metal interconnect of a substrate (i.e., during a complementary metal-oxide semiconductor (cmos) fabrication process) that form a directional coupler. each conductive strip has a length and a width configured such that an input end of the first conductive strip and a coupled end of the second conductive strip, that are electromagnetically coupled together, produce an over-coupling factor. the input end may be configured to couple to a local oscillator, and the coupled end may be configured to couple to a mixer. the directional coupler may provide, to the mixer, an output of a desired bandwidth based on the over-coupling factor.

20250141098. MILLIMETER WAVE QUANTUM SENSOR DEVICE_simplified_abstract_(texas instruments incorporated)

Inventor(s): Juan HERBSOMMER of Allen TX US for texas instruments incorporated, Hassan Omar ALI of Murphy TX US for texas instruments incorporated

IPC Code(s): H01Q1/36, H01Q1/38, H01Q1/48, H01Q13/06

CPC Code(s): H01Q1/366

Abstract: a device comprises a u-shaped cell configured to contain a quantum gas, a first waveguide coupled to an inlet of the u-shaped cell, and a second waveguide coupled to an outlet of the u-shaped cell. the device also comprises a multi-layer substrate including transmitter and receiver antennas that are aligned with the first and second waveguides, respectively, the substrate including a network of metal layers coupled to the transmitter and receiver antennas. the device also includes transmitter and receiver dies coupled to the transmitter and receiver antennas, respectively, by way of the network of metal layers, the substrate positioned between the u-shaped cell and the transmitter and receiver dies.

20250141333. CONTROLLER WITH AVERAGE CURRENT BALANCING CIRCUIT_simplified_abstract_(texas instruments incorporated)

Inventor(s): Seetha Seetharaman of Freising DE for texas instruments incorporated, Puneet Sareen of Freising DE for texas instruments incorporated

IPC Code(s): H02M1/00, H02M1/088, H02M3/158

CPC Code(s): H02M1/0009

Abstract: a circuit includes a compensation terminal, a current feedback terminal, a voltage feedback terminal, a reference voltage terminal, a modulator, an error amplifier, and average current balancing circuitry. a first input of the modulator is coupled to the current feedback terminal. a first input of the error amplifier is coupled to the voltage feedback terminal. a second input of the error amplifier is coupled to the reference voltage terminal. an output of the error amplifier is coupled to the compensation terminal. a first input of the average current balancing circuitry is coupled to the output of the error amplifier and the compensation terminal. a second input of the average current balancing circuitry is coupled to the current feedback terminal. an output of the average current balancing circuitry is coupled to a second input of the modulator.

20250141352. MULTI-FUNCTION HIGH SIDE FIELD-EFFECT TRANSISTOR DRIVER CIRCUIT_simplified_abstract_(texas instruments incorporated)

Inventor(s): Bradford Hunter of Austin TX US for texas instruments incorporated, Jing Ye of Dallas TX US for texas instruments incorporated, Xiaogiu Summer Huang of Dallas TX US for texas instruments incorporated, Terry Sculley of Lewisville TX US for texas instruments incorporated

IPC Code(s): H02M3/07, H02M1/00, H02M1/088, H02M1/32

CPC Code(s): H02M3/07

Abstract: an integrated circuit comprises a charge pump connected to a power source terminal and to a ground terminal, the charge pump having a charge pump output terminal; and a switch matrix having a plurality of switch matrix inputs and a plurality of switch matrix outputs, wherein pairs of the plurality of switch matrix outputs are connected to respective ones of a respective plurality of output terminals, and wherein the charge pump output terminal is connected to a first subset comprising at least three of the plurality of switch matrix inputs.

20250141382. FIELD ORIENTED CONTROL WITH SECTOR DETERMINATION_simplified_abstract_(texas instruments incorporated)

Inventor(s): Alexander Tessarolo of Lindfield AU for texas instruments incorporated

IPC Code(s): H02P21/34, H02P21/00, H02P21/10

CPC Code(s): H02P21/34

Abstract: in described examples, a device includes a non-transitory memory and a processor. the memory stores a first instruction. the processor receives the first instruction from the memory. executing the first instruction causes the processor to perform the following actions. the processor receives a position vector corresponding to a sum of a first component in a first dimension and a second component in a second dimension. the processor compares a magnitude of the first component to a magnitude of the second component, and compares the first component or the second component to zero. and the processor determines a sector in which the position vector is located responsive to the compare actions and a sector layout. in some examples, execution of additional instructions causes the processor to operate a rotational system in response to the determined sector.

20250141408. REDUCTION OF CLICK AND POP NOISE IN AN AMPLIFIER_simplified_abstract_(texas instruments incorporated)

Inventor(s): Aditya SUNDAR of Bangalore IN for texas instruments incorporated, Sumit DUBEY of Bangalore IN for texas instruments incorporated, Anand KANNAN of Bangalore IN for texas instruments incorporated

IPC Code(s): H03F1/30, H03F3/217

CPC Code(s): H03F1/305

Abstract: in an example, a system includes a loop filter including one or more integrators. the system includes a ramp generator. the system includes a comparator having a first input coupled to an output of the loop filter, a second input coupled to an output of the ramp generator, and having an output. the system includes a mute loop coupled to an input of the loop filter and the output of the comparator. the system includes a power stage having an input coupled to the output of the comparator, and having an output. the system includes a main loop coupled to the output of the power stage and the input of the loop filter. the system includes an integrated error detector having an input coupled to the loop filter, and having an output. the system includes a dual comparator having an input coupled to the output of the integrated error detector.

20250141412. METHODS AND APPARATUS TO MODULATE SIGNALS USING MULTI-CLASS MODULATION CIRCUITRY_simplified_abstract_(texas instruments incorporated)

Inventor(s): Jianquan Liao of Shanghai CN for texas instruments incorporated, Zejian Wang of Shanghai CN for texas instruments incorporated, Pourya Assem of Dallas TX US for texas instruments incorporated, Kannan Krishna of Dallas TX US for texas instruments incorporated, Zhenzhen Chen of Shanghai CN for texas instruments incorporated, Jing Xu of Shanghai CN for texas instruments incorporated, Shurong Xia of Plano TX US for texas instruments incorporated, Chi Cheong of Frisco TX US for texas instruments incorporated

IPC Code(s): H03F3/217, H03F3/21

CPC Code(s): H03F3/217

Abstract: an example apparatus includes: class d amplifier circuitry having a first input, a second input, a third input, and an output, the first input of the class d amplifier circuitry coupled to the output of the class d amplifier circuitry; and class ab amplifier circuitry having a first input, a second input, a third input, and an output, the first input of the class ab amplifier circuitry coupled to the first input of the class d amplifier circuitry and the output of the class d amplifier circuitry, the second and third inputs of the class ab amplifier circuitry coupled to the second and third inputs of the class d amplifier circuitry, and the output of the class ab amplifier circuitry.

20250141415. METHODS AND APPARATUS TO DYNAMICALLY INCREASE AMPLIFIER SLEW RATES_simplified_abstract_(texas instruments incorporated)

Inventor(s): Vivek Varier of Tucson AZ US for texas instruments incorporated, Srinivas K Pulijala of Tucson AZ US for texas instruments incorporated, Vadim V. Ivanov of Dallas TX US for texas instruments incorporated

IPC Code(s): H03F3/45

CPC Code(s): H03F3/45183

Abstract: an example apparatus includes: a first transistor having a first terminal and a control terminal; a second transistor having a first terminal and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor; a third transistor having a first terminal and a control terminal; a fourth transistor having a first terminal and a control terminal, the first terminal of the fourth transistor coupled to the first terminal of the third transistor; feedback circuitry coupled to the first transistor, the second transistor, the third transistor and the fourth transistor; current source circuitry having a first terminal and a second terminal, the first terminal of the current source circuitry coupled to the feedback circuitry; slew assist circuitry coupled to the first transistor, the second transistor, the third transistor and the fourth transistor, the feedback circuitry and the current source circuitry.

20250141443. APPARATUS AND METHODS TO CONTROL WELL BIAS IN A SEMICONDUCTOR DEVICE_simplified_abstract_(texas instruments incorporated)

Inventor(s): Taewoo Kwak of McKinney TX US for texas instruments incorporated, Benjamin Amey of Allen TX US for texas instruments incorporated, Daijiro Otani of Plano TX US for texas instruments incorporated

IPC Code(s): H03K17/10, H03K17/687, H03K19/0185

CPC Code(s): H03K17/102

Abstract: an example circuit includes a substrate including a first transistor of a gate driver output stage, the substrate including a first well region; a diode circuit including a first terminal and a second terminal, the first terminal coupled to a first tap of the first well region; and a second transistor including a first terminal, a second terminal, and a body, the first terminal of the second transistor coupled to a switching voltage terminal, and the second terminal and the body of the second transistor coupled to the first tap of the first well region and to the first terminal of the diode circuit.

20250141458. METHOD AND SYSTEM FOR OPERATING MULTIPLE ANALOG-TO-DIGITAL CONVERTORS POSITIONED ON A SINGLE SEMICONDUCTOR DIE_simplified_abstract_(texas instruments incorporated)

Inventor(s): Christy Leigh She of Allen TX US for texas instruments incorporated, Joonsung Park of Allen TX US for texas instruments incorporated, Krishnasawamy Nagaraj of Ashburn VA US for texas instruments incorporated, Srinivasa Chakravarthy of Bangalore IN for texas instruments incorporated

IPC Code(s): H03M1/08

CPC Code(s): H03M1/08

Abstract: methods for operating two or more analog-to-digital converters (adcs) are presented herein. the method may be implemented in an integrated circuit. the integrated circuit may include a first adc and a second adc disposed on a single semiconductor die. the integrated circuit may also include logic circuitry operably coupled to the first and second adcs. for a digital value obtained by conversion, by the first adc, of a first analog signal sampled by the first adc during a period of time overlapping with another period of time during which a second analog signal is being converted by the second adc, the logic circuitry may be configured to cause the digital value to be marked as noisy.

20250141460. Voltage-to-Delay Converter_simplified_abstract_(texas instruments incorporated)

Inventor(s): Sai Vikas Kandimalla of Nalgonda IN for texas instruments incorporated, Neeraj Shrivastava of Bangalore IN for texas instruments incorporated, Visvesvaraya Appala Pentakota of Bangalore IN for texas instruments incorporated, Keshav Tiwari of New Delhi IN for texas instruments incorporated

IPC Code(s): H03M1/12, G04F10/00

CPC Code(s): H03M1/12

Abstract: a voltage-to-delay converter includes a first reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal, and a second terminal coupled to a top plate of a first integrating capacitor, and a second reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal, and a second terminal coupled to a top plate of a second integrating capacitor. first and second input transistors receive first and second input voltages, and are coupled between the top plate of the first and second integrating capacitors, respectively, and a first current source. a discharge current source is coupled to bottom plates of the first and second integrating capacitors. a pulse generator has first and second inputs coupled to the top plate of the first and second integrating capacitors, respectively.

20250141462. ASYNCHRONOUS ANALOG TO DIGITAL CONVERTER_simplified_abstract_(texas instruments incorporated)

Inventor(s): Venkatesh Kadlimatti of HUBLI IN for texas instruments incorporated, Rinu Mathew of BANGALORE IN for texas instruments incorporated

IPC Code(s): H03M1/12, G05F3/02, H03M1/46

CPC Code(s): H03M1/125

Abstract: in described examples, an integrated circuit (ic) includes multiple subcircuits. the subcircuits include a first subcircuit that receives a current and sinks a portion of the current that is responsive to a threshold. in response to the current being greater than the threshold, the first subcircuit provides a difference between the current and the portion to a second subcircuit and asserts a signal corresponding to an ordinality of the first subcircuit. the second subcircuit is configured to repeat the actions with respect to the first subcircuit, with the second subcircuit in place of the first subcircuit and a third subcircuit in place of the second subcircuit, and with the difference in place of the current, in response to the ic comprising the third subcircuit.

20250141652. CLOCK RECOVERY TRAINING_simplified_abstract_(texas instruments incorporated)

Inventor(s): Bhavesh BHAKTA of Richardson TX US for texas instruments incorporated, Paul Marion MILLER, IV of Farmers Branch TX US for texas instruments incorporated, Mark Ryan LOVE of Dallas TX US for texas instruments incorporated

IPC Code(s): H04L7/00, G06F1/12, H04L7/06

CPC Code(s): H04L7/0012

Abstract: in some examples, a method includes determining a first clock data recovery (cdr) code of a cdr circuit at a first time and determining a second cdr code of the cdr circuit at a second time after the first time. the method also includes generating, by a clock generator, a sampling clock for sampling a received data signal according to the first cdr code while the cdr circuit is active and determining, by an offset circuit, a clock offset based on the first cdr code and the second cdr code. additionally, the method includes generating, by the clock generator, the sampling clock according to the clock offset responsive to disabling of the cdr circuit.

20250142072. SUB-PICTURE BASED RASTER SCANNING CODING ORDER_simplified_abstract_(texas instruments incorporated)

Inventor(s): Minhua Zhou of San Diego CA US for texas instruments incorporated

IPC Code(s): H04N19/129, H04N19/119, H04N19/174, H04N19/433, H04N19/436

CPC Code(s): H04N19/129

Abstract: a method and apparatus for sub-picture based raster scanning coding order. the method includes dividing an image into even sub-pictures, and encoding parallel sub-pictures on multi-cores in raster scanning order within sub-pictures, wherein from core to core, coding of the sub-picture is independent around sub-picture boundaries, and wherein within a core, coding of a sub-picture is at least one of dependent or independent around sub-picture boundaries.

20250142241. WAKEUP MECHANISM FOR AN AUDIO SYSTEM_simplified_abstract_(texas instruments incorporated)

Inventor(s): Udit Rawat of Allen TX US for texas instruments incorporated, Bichoy Bahr of Allen TX US for texas instruments incorporated, Baher Haroun of Allen TX US for texas instruments incorporated

IPC Code(s): H04R1/08

CPC Code(s): H04R1/08

Abstract: an acoustic device is provided which comprises an audio system including: a microphone having a microphone output, and a processing circuit having a wakeup input, an audio input, and an audio output, the audio input coupled to the microphone output. in at least one example, the acoustic device further comprises an acoustic sensor separate from the microphone, the acoustic sensor having a sensor output. in at least one example, the acoustic device further comprises a wakeup circuit having a sensor input and a wakeup output, the sensor input coupled to the sensor output, wherein the wakeup output is coupled to the wakeup input.

20250142476. COLLISION DETECTION THROUGH INTELLIGENT SILENCE_simplified_abstract_(texas instruments incorporated)

Inventor(s): Shyam Krishnan VENKATESWARAN of Atlanta GA US for texas instruments incorporated, Ariton E. XHAFA of Plano TX US for texas instruments incorporated

IPC Code(s): H04W52/02, H04W72/566

CPC Code(s): H04W52/0235

Abstract: in an example, a method includes transmitting a plurality of wake-up frames on a transmission channel from a first node having a first priority. the method also includes pausing the wake-up frames from the first node and listening to the transmission channel after a predetermined number of wake-up frames are transmitted from the first node. the method also includes receiving, at the first node, a wake-up frame from a second node on the transmission channel, wherein the second node has a second priority.

20250142709. MINIATURIZED INTEGRATED CYCLOTRON_simplified_abstract_(texas instruments incorporated)

Inventor(s): Krishna Praveen Mysore Rajagopal of MANTECA CA US for texas instruments incorporated

IPC Code(s): H05H13/00, H05H7/18, H05H15/00

CPC Code(s): H05H13/005

Abstract: an electronic device includes a first resonator electrode and a second resonator electrode in an interconnect stack over a semiconductor substrate. the first resonator electrode includes a first lower resonator electrode, a first upper resonator electrode and a first plurality of vias between the first lower resonator electrode and the first upper resonator electrode. the second resonator electrode includes a second lower resonator electrode, a second upper resonator electrode, and a second plurality of vias between the second lower resonator electrode and the second upper resonator electrode. a cavity in the interconnect stack is bounded by the first resonator electrode and the second resonator electrode. an electron emitter extends from the semiconductor surface between the first and second resonator electrodes and is configured to direct electrons into the cavity. the electronic device may be operated to produce short wavelength radiation, e.g. x-rays.

20250142800. SELECTIVE SILICON-GERMANIUM PROCESS AND STRUCTURE_simplified_abstract_(texas instruments incorporated)

Inventor(s): Manoj Mehrotra of Plano TX US for texas instruments incorporated

IPC Code(s): H10B10/00

CPC Code(s): H10B10/12

Abstract: described examples include a semiconductor device having a first p-channel field effect transistor (p-fet). the first p-fet includes: a first gate dielectric layer on a surface of a substrate; a first gate structure on the first gate dielectric layer; and first silicon-germanium (sige) regions disposed in the substrate, on both sides of the first gate structure, the first sige regions extended to a first depth from the surface of the substrate. the semiconductor device also has a second p-fet. the second p-fet includes a second gate dielectric layer on the surface of the substrate; a second gate structure on the second gate dielectric layer; and second sige regions disposed in the substrate, on both sides of the second gate structure, the second sige regions extended to a second depth from the surface of the substrate, the second depth different than the first depth.

20250142843. INTEGRATED DEEP TRENCH CAPACITOR HAVING HIGH CAPACITANCE DENSITY AND VOLTAGE LINEARITY_simplified_abstract_(texas instruments incorporated)

Inventor(s): Poornika Gayathri Fernandes of Murphy TX US for texas instruments incorporated, Jack Qian of Plano TX US for texas instruments incorporated

IPC Code(s): H01L29/94, H01L27/07, H01L29/66

CPC Code(s): H10D1/665

Abstract: an integrated circuit including an integrated trench capacitor in a substrate. the trench capacitor includes a plurality of deep trenches extending into the substrate, the trenches filled with a conductive trench-fill material. a first subset of the trenches located in an n-type well and a second subset of the trenches located in a p-type well. a first capacitor terminal connects the conductive trench-fill material in the first subset of trenches and the conductive trench-fill material in the second subset of trenches. a second capacitor terminal connects the n-type well and the p-type well.

20250142851. METHOD TO SUPPRESS BASE POLY LINKUP OVERGROWTH INTO THE EMITTER CAVITY DURING SILICON GERMANIUM SELECTIVE EPITAXY GROWTH_simplified_abstract_(texas instruments incorporated)

Inventor(s): Jerald Rock of Lisbon ME US for texas instruments incorporated, Thomas Moutinho of Gorham ME US for texas instruments incorporated, Tatsuya Tominari of Plano TX US for texas instruments incorporated, Thanas Budri of Portland ME US for texas instruments incorporated

IPC Code(s): H01L29/66, H01L21/02, H01L21/3065, H01L29/08, H01L29/10, H01L29/737

CPC Code(s): H10D10/021

Abstract: a semiconductor device includes a heterojunction bipolar transistor (hbt) having a collector, a base, and an emitter. the base includes a monocrystalline base layer, including silicon-germanium, on the collector, and an extrinsic base layer, including polycrystalline silicon, extending partway over the monocrystalline base layer. the base further includes a base link, including polycrystalline silicon-germanium, connecting the monocrystalline base layer to the extrinsic base layer. an emitter spacer, of dielectric material, laterally separates the emitter from the extrinsic base layer. the hbt has a spacer-extrinsic base vertical offset between a bottom of the emitter spacer and a bottom surface of the extrinsic base layer adjacent to the emitter spacer. the emitter spacer has a bottom width at a bottom of the emitter spacer. a sum of the spacer-extrinsic base vertical offset and the bottom width of the emitter spacer is greater than the thickness of the monocrystalline base layer.

20250142866. SELF-ALIGNED GATE STRUCTURE_simplified_abstract_(texas instruments incorporated)

Inventor(s): Zhikai Tang of Sunnyvale CA US for texas instruments incorporated, Masahiko Higashi of Aizuwakamatsu JP for texas instruments incorporated, Ujwal Radhakrishna of San Jose CA US for texas instruments incorporated, Jungwoo Joh of Allen TX US for texas instruments incorporated

IPC Code(s): H01L29/778, H01L29/20, H01L29/40, H01L29/423, H01L29/66

CPC Code(s): H10D30/475

Abstract: the present disclosure generally relates to semiconductor processing for a self-aligned gate structure and corresponding semiconductor device. in an example, a semiconductor device includes a semiconductor substrate, a semiconductor gate layer, an offset dielectric layer, and a gate metal contact. the semiconductor gate layer is over the semiconductor substrate. the offset dielectric layer is over the semiconductor gate layer. the gate metal contact is over the offset dielectric layer and is through an opening through the offset dielectric layer. the gate metal contact contacts the semiconductor gate layer through the opening through the offset dielectric layer. a first sidewall of the semiconductor gate layer, a second sidewall of the offset dielectric layer, and a third sidewall of the gate metal contact are vertically aligned over the semiconductor substrate.

20250142876. HYBRID COMPONENT WITH SILICON AND WIDE BANDGAP SEMICONDUCTOR MATERIAL_simplified_abstract_(texas instruments incorporated)

Inventor(s): Christopher Boguslaw Kocon of Mountain Top PA US for texas instruments incorporated, Henry Litzmann Edwards of Garland TX US for texas instruments incorporated, Curry Bachman Taylor of Garland TX US for texas instruments incorporated

IPC Code(s): H10D30/65, H10D64/00

CPC Code(s): H10D30/65

Abstract: a microelectronic device includes a hybrid component. the microelectronic device has a substrate including silicon semiconductor material. the hybrid component includes a silicon portion in the silicon, and a wide bandgap (wbg) structure on the silicon. the wbg structure includes a wbg semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. the hybrid component has a first current terminal on the silicon, and a second current terminal on the wbg semiconductor structure. the microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the wbg structure on the silicon.

TEXAS INSTRUMENTS INCORPORATED patent applications on May 1st, 2025