TEXAS INSTRUMENTS INCORPORATED patent applications on April 3rd, 2025
Patent Applications by TEXAS INSTRUMENTS INCORPORATED on April 3rd, 2025
TEXAS INSTRUMENTS INCORPORATED: 32 patent applications
TEXAS INSTRUMENTS INCORPORATED has applied for patents in the areas of H01L23/00 (6), H01L23/495 (6), H01L29/66 (4), H01L23/31 (4), H01L29/06 (4) G01D18/001 (1), H02J7/0063 (1), H10D64/671 (1), H10D62/115 (1), H10D30/6757 (1)
With keywords such as: terminal, having, transistor, semiconductor, device, circuit, control, layer, circuitry, and coupled in patent application abstracts.
Patent Applications by TEXAS INSTRUMENTS INCORPORATED
Inventor(s): Preetinder GARCHA of WATERTOWN MA US for texas instruments incorporated, Lawrence COTTON of ALLEN TX US for texas instruments incorporated, Dok Won LEE of MOUNTAIN VIEW CA US for texas instruments incorporated, Baher HAROUN of ALLEN TX US for texas instruments incorporated
IPC Code(s): G01D18/00, G01D5/14
CPC Code(s): G01D18/001
Abstract: in a described example, a position sensor can include a first magnetic field sensor unit having a first sensor output, a second magnet field sensor unit having a second sensor output, one or more coils having one or more footprints overlapping the first and second magnetic field sensor units, and a processing circuit having a first sensor input, a second sensor input, a current terminal, and a sensing output, the first sensor input coupled to the first sensor output, the second sensor input coupled to the second sensor output, and the current terminal coupled to the one or more coils.
20250109976. GAS VOLUME DETERMINATION IN FLUID_simplified_abstract_(texas instruments incorporated)
Inventor(s): Anand DABAK of Plano TX US for texas instruments incorporated, Srinivas LINGAM of Dallas TX US for texas instruments incorporated
IPC Code(s): G01F1/66, G01F1/667, G01F1/7082, G01F1/712, G01F1/74, G01N29/02, G01N29/024, G01N29/36, G01N29/44
CPC Code(s): G01F1/66
Abstract: an integrated circuit includes one or more central processing unit (cpu) cores configured to cause a first ultrasonic transducer to generate ultrasonic signals into a fluid moving in a pipe and the first or a second ultrasonic transducer to receive the ultrasonic signals from the fluid. the cpu core(s) also compute a first value indicative of at least one of a standard deviation and a time correlation based on the received ultrasonic signals. the cpu core(s) further determine a second value indicative of a volume of gas bubbles in the fluid using the computed first value indicative of the at least one of the standard deviation and time correlation.
Inventor(s): Abhinay PATIL of BANGALORE IN for texas instruments incorporated, Vinayak HEGDE of BANGALORE IN for texas instruments incorporated, Umang AGARWAL of BANGALORE IN for texas instruments incorporated
IPC Code(s): G01R31/28, G01R35/00
CPC Code(s): G01R31/2834
Abstract: one example includes a circuit. the circuit includes a transistor device arranged between a first terminal and a second terminal and a transistor device controller configured to control operation of the transistor device. the circuit further includes a current limit controller that includes a current limit circuit configured to regulate an amplitude of operational current through the transistor device between the first and second terminals during a normal operating mode, and a testing system configured to conduct a calibration current provided by an automated testing equipment (ate) device through an internal test resistor for the ate device to determine a resistance value of the internal test resistor during a test mode to facilitate testing of the current limit circuit via a test current provided by the ate device between the first and second terminals through the transistor device based on the determined resistance value of the internal test resistor.
20250110176. FAULT DETECTION CIRCUIT_simplified_abstract_(texas instruments incorporated)
Inventor(s): Weibing Jing of Beijing CN for texas instruments incorporated
IPC Code(s): G01R31/319, G01R31/317, G01R31/3193
CPC Code(s): G01R31/31922
Abstract: fault detection circuits and methods. an example of a fault detection circuit includes a comparator configured to compare a voltage at a voltage terminal with a reference voltage, a digital logic circuit coupled to a test terminal and configured to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator, a test signal, the digital logic circuit including at least one digital logic gate, and an edge detection circuit configured to (a) monitor a signal produced at an output of the at least one digital logic gate, and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the test terminal.
Inventor(s): Haydar BILHAN of Dallas TX US for texas instruments incorporated, Abhijit DAS of Plano TX US for texas instruments incorporated
IPC Code(s): G01R31/52, G01R31/08, H03M1/12, H03M1/46
CPC Code(s): G01R31/52
Abstract: in some examples, a method includes applying a bias voltage to a resolver system. the method also includes receiving a sensed signal, the sensed signal varying in value based on a position of a rotary element. the method also includes attenuating the sensed signal to form an attenuated signal. the method also includes performing fault detection on the attenuated signal to detect faults in the resolver system. the method also includes processing the attenuated signal to determine the position of the rotary element.
Inventor(s): Tomas Motos of Hamar NO for texas instruments incorporated, Espen Wium of Oslo NO for texas instruments incorporated, Trond Meckelborg Rognerud of Sorumsand NO for texas instruments incorporated, Aslak Ringvoll Normann of Oslo NO for texas instruments incorporated, Oskar Gustaf Fredrik Von Heideken of Oslo NO for texas instruments incorporated, Reidar Myhr of Oslo NO for texas instruments incorporated
IPC Code(s): G01S13/87, G01S7/285, G01S13/76
CPC Code(s): G01S13/878
Abstract: techniques related to measuring a time-of-flight (tof), comprising switching a first measuring station to a main operating mode, transmitting, by the first measuring station, a first tof packet to a remote device, switching the first measuring station to a receive mode to receive a first tof response packet from the remote device, receiving, by the first measuring station, the first tof response packet, determining, a time interval between transmitting of the first tof packet and receiving the first tof response packet, receiving a plurality of time intervals from one or more other measuring stations, determining a tof measurement based on the first time interval and the plurality of time intervals, switching the first measuring station to a secondary operating mode, and transmitting to a second measuring station, an indication to switch to the main operating mode.
Inventor(s): Lokesh Kumar Botcha of New Delhi IN for texas instruments incorporated, Venkata Mohana Vamsi Voora of Eluru IN for texas instruments incorporated, Ankit Garg of Bangalore IN for texas instruments incorporated, Supriyo Palit of Bangalore IN for texas instruments incorporated
IPC Code(s): G06F3/16
CPC Code(s): G06F3/162
Abstract: an apparatus includes an amplifier having an input. an interface has inputs and an output. the interface is configured to: invert each bit of a value received at a first input of the interface to produce an inverted value; and provide the inverted value at the output. a processor has an input coupled the output of the interface, has first output coupled to a second input of the interface, and has a second output coupled to the input of the amplifier. the processor is configured to determine whether to set an adjustable gain setting of an audio processing block to the inverted value.
20250111007. ACCELERATED FFT HARDWARE_simplified_abstract_(texas instruments incorporated)
Inventor(s): Kanish B of CHENNAI IN for texas instruments incorporated, Karthik Subburaj of Bangalore IN for texas instruments incorporated, Karthik Ramasubramanian of Bangalore IN for texas instruments incorporated, Anushree Pendharkar of Bangalore IN for texas instruments incorporated, Kameswaran Vengattaramane of Bangalore IN for texas instruments incorporated, Atman Kar of Bangalore IN for texas instruments incorporated
IPC Code(s): G06F17/14, G06F7/50, G06F7/523
CPC Code(s): G06F17/142
Abstract: in described examples, an integrated circuit (ic) includes a fast fourier transform (fft) engine, a first memory, a second memory, a conjugate symmetric combiner (csc), and a control circuit coupled to control them. the first and second memories are coupled to the fft engine, and the csc is coupled to the first and second memories and the fft engine. the fft engine receives and processes a first stream of samples to generate a second stream of samples. in a first phase, the fft engine provides a first portion of the second stream of samples to the first memory. in a second phase, the fft engine provides a second portion of the second stream of samples to the second memory, the first memory provides the first portion of the second stream of samples to the csc, and the csc responsively generates a third stream of samples.
Inventor(s): Veeramanikandan Raju of Bangalore IN for texas instruments incorporated, Mihir Narendra Mody of Bangalore IN for texas instruments incorporated, Tanu Hari Dixit of Bangalore IN for texas instruments incorporated
IPC Code(s): G06F21/60, G06F7/58, G06F11/07, G06F21/72
CPC Code(s): G06F21/602
Abstract: an example apparatus includes: interface circuitry; and programmable circuitry configured to: obtain a set of processor instructions; select a first subset of processor instructions from the set; encrypt the first subset of processor instructions; select a second subset of processor instructions from the set; compute a plurality of message authentication codes (macs) corresponding to the second subset of processor instructions; cause the interface circuitry to write the set of processor instructions to an external memory; and cause the interface circuitry to write a description of the first subset of processor instructions, a description of the second subset of processor instructions, and the plurality of macs to the external memory.
Inventor(s): Veeramanikandan Raju of Bangalore IN for texas instruments incorporated, Anand Kumar G of Bangalore IN for texas instruments incorporated
IPC Code(s): G06F21/75
CPC Code(s): G06F21/755
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed to protect against voltage glitch attacks in microcontrollers. an example apparatus includes logic circuitry operable to, in response to a voltage glitch, pause processing circuitry; number generator circuitry operable to generate a number; a counter operable to, after the voltage glitch ends, adjust a count corresponding to the number; and the logic circuitry operable to unpause the processing circuitry after the count reaches a value.
Inventor(s): Ruby Ann M. CAMENFORTE of PAMPANGA PH for texas instruments incorporated, Charmaine Grace FACAL of OLONGAPO CITY PH for texas instruments incorporated, John Carlo MOLINA of LIMAY PH for texas instruments incorporated, Jason B. COLTE of LA TRINIDAD PH for texas instruments incorporated
IPC Code(s): H01F27/28, H01F27/29, H01F41/04, H01L23/31, H01L23/495
CPC Code(s): H01F27/2828
Abstract: a device that includes a lead structure and a coil is provided. the lead structure, of an electrically conductive material, has a lead structure width. the coil, of the electrically conductive material, includes first and second coil ends and a number of windings of the electrically conductive material extending between the first and second coil ends. the lead structure width is greater than a largest cross sectional dimension of the windings.
Inventor(s): Enis Tuncer of Dallas TX US for texas instruments incorporated
IPC Code(s): H01F27/32, H01F27/02, H01F27/28, H01F41/04, H01L23/495, H01L23/522, H01L23/58, H01L25/00, H01L25/18
CPC Code(s): H01F27/323
Abstract: a magnetic assembly includes a multilevel lamination or metallization structure with a core dielectric layer, dielectric stack layers, a high permittivity dielectric layer, and first and second patterned conductive features, the dielectric stack layers having a first relative permittivity, the high permittivity dielectric layer extends between and contacting the first patterned conductive feature and one of the dielectric stack layers or the core dielectric layer, the high permittivity dielectric layer has a second relative permittivity, and the second relative permittivity is at least 1.5 times the first relative permittivity to mitigate dielectric breakdown in isolation products.
Inventor(s): Ninad Shahane of San Francisco CA US for texas instruments incorporated, Vivek Arora of San Jose CA US for texas instruments incorporated, Kwang-Soo Kim of Sunnyvale CA US for texas instruments incorporated
IPC Code(s): H01L23/373, H01L21/56, H01L23/00, H01L23/31, H01L23/495
CPC Code(s): H01L23/3735
Abstract: an example includes: a package substrate having a die pad with a device side surface and a thermal pad on an opposite side surface; a thermal dissipation structure mounted to the die pad, the thermal dissipation structure including a thermally conductive insulator core and thermal conductors on a device side surface and on a substrate mount surface opposite the device side surface; at least one semiconductor device die mounted to the device side surface of the thermal dissipation structure; electrical connections formed between leads on the package substrate and bond pads on the at least one semiconductor device die; and mold compound covering the electrical connections, the at least one semiconductor device, and portions of the package substrate, portions of the leads of the package substrate forming terminals, and the thermal pad exposed from the mold compound and forming a thermal pad for a semiconductor device package.
Inventor(s): Jie CHEN of Plano TX US for texas instruments incorporated, Sylvester ANKAMAH-KUSI of Dallas TX US for texas instruments incorporated, Rajen Manicon MURUGAN of Dallas TX US for texas instruments incorporated, Yong XIE of Plano TX US for texas instruments incorporated, Danny Lee BRIJA of Allen TX US for texas instruments incorporated
IPC Code(s): H01L23/495, H01L23/00, H01L25/065, H01L29/16, H01L29/20, H01L29/778
CPC Code(s): H01L23/4951
Abstract: in examples, a power device comprises a first wide bandgap semiconductor die including a high-side transistor; a second wide bandgap semiconductor die including a low-side transistor; and a conductive device coupled to the first and second wide bandgap semiconductor dies. the conductive device comprises a first layer including a first metal member having fingers at first and second ends of the first metal member, a second metal member having fingers interleaved with fingers of the first metal member at the first end, and a third metal member having fingers interleaved with fingers of the first metal member at the second end. the conductive device also comprises multiple layers in vertical alignment with the first layer, the first, second, and third metal members extending through the multiple layers. the conductive device also comprises a dielectric material covering the first layer and the multiple layers. the power device comprises a connection layer coupling the conductive device to each of the first and second wide bandgap semiconductor dies, with the connection layer including the first, second, and third metal members, and with the first metal member having connection layer fingers at the first and second ends of the first metal member. the second metal member has connection layer fingers interleaved with connection layer fingers of the first metal member at the first end, and the third metal member has connection layer fingers interleaved with connection layer fingers of the first metal member at the second end.
Inventor(s): Huo Yun DUAN of Chengdu CN for texas instruments incorporated, Tian Sheng CHEN of Chengdu CN for texas instruments incorporated, Hang YAN of Chengdu CN for texas instruments incorporated, Qin PENG of Chengdu CN for texas instruments incorporated, Xiangrui LI of Chengdu CN for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L23/49565
Abstract: in examples, a method for manufacturing a package comprises coupling first and second semiconductor dies to a first surface of a conductive terminal; applying a dry film to a second surface of the conductive terminal opposite the first surface; removing a portion of the dry film contacting the second surface to form a dry film opening, the dry film opening having a linear, non-curved edge extending along a width of the conductive terminal; etching the second surface through the dry film opening; removing the dry film; plating the second surface; and sawing through the conductive terminal to form the package.
20250112148. TRANSFORMER GUARD TRACE_simplified_abstract_(texas instruments incorporated)
Inventor(s): Vijaylaxmi Gumaste Khanolkar of Pune IN for texas instruments incorporated
IPC Code(s): H01L23/522, H01F17/00, H01F27/28, H01F41/04, H01L23/00, H01L23/495, H05K3/46
CPC Code(s): H01L23/5227
Abstract: an electronic device includes first leads along a first side, second leads along a second side, first and second dies, and a magnetic assembly with a multilevel lamination structure with first and second windings and a conductive guard trace. the lamination structure includes the first winding in a first level, and the second winding in a different level. the guard trace is between the first patterned conductive feature and the second side of the package structure. a first set of electrical connections couple the first die, the first winding, and one of the first conductive leads in a first circuit, and a second set of electrical connections couple the second die, the second winding, the guard trace and one of the second conductive leads in an isolated second circuit.
Inventor(s): Masamitsu Matsuura of BEPPU-SHI OITA-KEN JP for texas instruments incorporated, Daiki Komatsu of BEPPU-SHI OITA-KEN JP for texas instruments incorporated, Kengo Aoya of BEPPU-SHI OITA-KEN JP for texas instruments incorporated, Ting-Ta Yen of San Jose CA US for texas instruments incorporated
IPC Code(s): H01L23/00, H01L21/56, H01L23/31
CPC Code(s): H01L24/05
Abstract: a semiconductor package includes a semiconductor wafer having a first connection pad and a second connection pad spaced apart by a semiconductor region of the semiconductor wafer. portions of the semiconductor wafer are covered by a protective overcoat. the semiconductor package also includes a cap wafer mounted to the semiconductor wafer and overpassing the semiconductor region of the semiconductor wafer. the cap wafer extends between the first connection pad and the second connection pad of the semiconductor wafer. the semiconductor package further includes an insulation material overlaying the cap wafer. the insulation material comprising vias to the first connection pad and the second connection pad, the vias being filled with a conductive material.
Inventor(s): Lei Chen of McKinney TX US for texas instruments incorporated, Vishnu Ravinuthula of Dallas TX US for texas instruments incorporated, Siang Tong Tan of Dallas TX US for texas instruments incorporated, Chienyu Huang of Plano TX US for texas instruments incorporated, Richard Sterling Broughton of Dallas TX US for texas instruments incorporated
IPC Code(s): H02J7/00, B60L50/60
CPC Code(s): H02J7/0063
Abstract: an example system includes: a first device having a ground plane at a first voltage, a first transmission terminal, and a second transmission terminal; a second device having a ground plane at a second voltage, a first receiver terminal, and a second receiver terminal; wherein the first device is configured to: operate in either a linear mode or a saturation mode based on a magnitude of electromagnetic interference; and during the linear mode or the saturation mode, use the first transmission terminal and second transmission terminal to transmit a differential signal to the second device.
Inventor(s): Ariel Dario Moctezuma of Richardson TX US for texas instruments incorporated, Sethu Mathavan Meikandamuthu Ayanar of Bangalore IN for texas instruments incorporated, Nimidev Kovilparambil Prasannan of Bangalore IN for texas instruments incorporated
IPC Code(s): H02M1/00, G01R31/40, H02M1/08, H02M3/156
CPC Code(s): H02M1/0009
Abstract: an example apparatus includes: error detection circuitry having an input and an output, the error detection circuitry configured to integrate a difference between a voltage of the input of the error detection circuitry and a reference voltage to produce an integrated error voltage; peak controller circuitry coupled to the error detection circuitry, the peak controller circuitry to compare a control current to a first reference current to generate a peak control current, the control current based on an integrated error voltage, the peak control current to increase an output current of converter circuitry; and valley controller circuitry coupled to the error detection circuitry and the peak controller circuitry, the valley controller circuitry to compare the control current to a second reference current to generate a valley control current, the valley control current to decrease the output current of the converter circuitry.
Inventor(s): Hongcheng Xu of Freising DE for texas instruments incorporated
IPC Code(s): H02M3/158, G06F1/24, H02M1/00, H02M1/088
CPC Code(s): H02M3/158
Abstract: a voltage monitoring circuit is configured to monitor the input voltage in a power converter and to assert a reset signal to disable operation of the power converter in response to the input voltage falling below a threshold level. the voltage monitoring circuit may include a power-on-reset (por) block that asserts the reset signal in response to the input voltage falling below a first threshold at a first rate, and a brown-out block that asserts the reset signal in response to the input voltage falling below a second threshold at a faster second rate (e.g., the input voltage falls quickly to zero or near zero such as during a brown-out event). the brown-out block includes a backup supply voltage that maintains some positive voltage level even in the absence of the input voltage for a certain period of time and a discharge circuit designed to quickly assert the reset signal.
Inventor(s): RAJAN LAKSHMI NARASIMHA of Allen TX US for texas instruments incorporated, DAVID P MAGEE of Allen TX US for texas instruments incorporated
IPC Code(s): H02P6/182, H02P6/08, H02P6/15, H03M1/12
CPC Code(s): H02P6/182
Abstract: a method includes receiving a first measurement signal representing a first time between transitions of a motor commutation state. the method further includes receiving a second measurement signal representing a second time between transitions of a motor floating terminal voltage. the method further includes determining a motor speed state based on a combination of the first and second measurement signals, determining a motor commutation state based on the motor speed state and the motor floating terminal voltage; and providing a control signal to a motor inverter based on the motor commutations state.
Inventor(s): Pallabi PRAMANIK of Bengaluru IN for texas instruments incorporated, Mahadevan VENKITESWARAN of Bengaluru IN for texas instruments incorporated
IPC Code(s): H03F1/26, H03F1/02, H03F3/45, H03K5/24
CPC Code(s): H03F1/26
Abstract: an integrated circuit (ic) includes: first and second transistors having a respective first terminal, a respective second terminal, and a respective control terminal; and cascode circuitry having a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. the first terminal of the cascode circuitry is coupled to the control terminal of the first transistor. the second terminal of the cascode circuitry is coupled to the control terminal of the second transistor. the third terminal of the cascode circuitry is coupled to the second terminal of the first transistor. the fourth terminal of the cascode circuitry is coupled to the second terminal of the second transistor. the ic also includes dynamic biasing circuitry having a first terminal and a second terminal. the first terminal of the dynamic biasing circuitry is coupled to the first terminals of the first and second transistors.
Inventor(s): Pourya Assem of Dallas TX US for texas instruments incorporated, Yogesh Ramadass of Santa Clara CA US for texas instruments incorporated, Kevin Scoones of San Clara CA US for texas instruments incorporated, Tim Merkin of Dallas TX US for texas instruments incorporated, Zejian Wang of Shanghai CN for texas instruments incorporated, Jianquan Liao of Shanghai CN for texas instruments incorporated, Yinglai Xia of Dallas TX US for texas instruments incorporated
IPC Code(s): H03F3/217, H03F1/32, H03F3/38
CPC Code(s): H03F3/217
Abstract: an apparatus includes a first power stage circuit having a first output and a power terminal, and a second power stage circuit having a second output and the power terminal. the apparatus further includes a control circuit having a control input, a first control output, and a second control output. in an example, the control input is coupled to the power terminal, the first control output is coupled to the first output, and the second control output is coupled to the second output. in an example, the control circuit is configured to, responsive to a first voltage at the power terminal being below a threshold voltage, set the first and second outputs to a second voltage.
Inventor(s): Eung Jung Kim of Allen TX US for texas instruments incorporated, Xiaochun Zhao of Allen TX US for texas instruments incorporated, Abidur Rahman of Richardson TX US for texas instruments incorporated, Sualp Aras of Dallas TX US for texas instruments incorporated
IPC Code(s): H03K17/0812
CPC Code(s): H03K17/08122
Abstract: an example apparatus includes: a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the second terminal of the second transistor coupled to the second terminal of the first transistor; first driver circuitry having a terminal coupled to the control terminal of the first transistor; second driver circuitry having a terminal coupled to the control terminal of the second transistor; and gate balancing circuitry having a first terminal and a second terminal, the first terminal of the gate balancing circuitry coupled to the control terminal of the first transistor and the terminal of the first driver circuitry, the second terminal of the gate balancing circuitry coupled to the control terminal of the second transistor.
Inventor(s): Tawen Mei of Santa Clara CA US for texas instruments incorporated
IPC Code(s): H03K19/0185, H03K17/687
CPC Code(s): H03K19/018521
Abstract: in some aspects, an integrated circuit comprises an input voltage terminal, a capacitor terminal, a first nmos transistor connected to the input voltage terminal, a first pmos transistor connected to a first nmos gate terminal of the first nmos transistor and connected to the capacitor terminal, the first pmos transistor having a first pmos gate terminal, a second pmos transistor connected to the first nmos gate terminal of the first nmos transistor, the second pmos transistor having a second pmos gate terminal, a switched output terminal, a second nmos transistor connected to the switched output terminal, a third nmos transistor connected to the switched output terminal, an inverter, and a complementary metal oxide semiconductor (cmos) transistor pair, the cmos transistor pair having an input connected to the third nmos transistor and an output connected to a second pmos gate terminal of the second pmos transistor.
Inventor(s): Anindita BORAH of Santa Clara CA US for texas instruments incorporated, Ramsin ZIAZADEH of San Jose CA US for texas instruments incorporated, Ashwin RAMACHANDRAN of Santa Clara CA US for texas instruments incorporated
IPC Code(s): H04B1/38, H03F3/19, H03K17/56
CPC Code(s): H04B1/38
Abstract: in an example, a circuit includes a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal. the differential input circuit includes a first transistor having a first transistor control terminal and first and second terminals. the differential input circuit includes a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together. the circuit includes a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal. the circuit also includes a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal. the circuit includes a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal.
20250113047. CODING UNIT PARTITIONING_simplified_abstract_(texas instruments incorporated)
Inventor(s): Hyung Joon Kim of McKinney TX US for texas instruments incorporated, Minhua Zhou of Plano TX US for texas instruments incorporated, Akira Osamoto of Plano TX US for texas instruments incorporated, Hideo Tamama of The Colony TX US for texas instruments incorporated
IPC Code(s): H04N19/192, H04N19/103, H04N19/107, H04N19/119, H04N19/147, H04N19/169, H04N19/176, H04N19/51, H04N19/52, H04N19/593
CPC Code(s): H04N19/192
Abstract: a method for coding unit partitioning in a video encoder is provided that includes performing intra-prediction on each permitted coding unit (cu) in a cu hierarchy of a largest coding unit (lcu) to determine an intra-prediction coding cost for each permitted cu, storing the intra-prediction coding cost for each intra-predicted cu in memory, and performing inter-prediction, prediction mode selection, and cu partition selection on each permitted cu in the cu hierarchy to determine a cu partitioning for encoding the lcu, wherein the stored intra-prediction coding costs for the cus are used.
Inventor(s): THOMAS KRONENBERG of Dallas TX US for texas instruments incorporated
IPC Code(s): H01L29/866, H01L21/784, H01L23/00, H01L27/08, H01L29/06
CPC Code(s): H10D8/25
Abstract: an example arrangement includes a semiconductor device having at least two vertical diode devices spaced from one another by isolation trenches. each of the vertical diode devices includes: a first diffusion region of a first p-type or n-type conductivity formed in a device side surface of the semiconductor die, the first diffusion region extending into a first epitaxial layer of a second p-type or n-type conductivity opposite the first conductivity type; the first epitaxial layer formed over a semiconductor substrate of the first p-type or n-type conductivity. the semiconductor substrate includes a backside surface facing away from the device side surface of the semiconductor die; metal contacts on the device side surface of the semiconductor die are electrically coupled to the first diffusion region; and stud bumps formed on the metal contacts and arranged to form terminals of the semiconductor device.
20250113548. CARBON NANOTUBE DEVICES_simplified_abstract_(texas instruments incorporated)
Inventor(s): Luigi Colombo of Dallas TX US for texas instruments incorporated, Baher S. Haroun of Allen TX US for texas instruments incorporated
IPC Code(s): H01L29/786, H01L21/02, H01L29/06, H01L29/66, H01L29/775
CPC Code(s): H10D30/6757
Abstract: a method includes forming, on a dielectric layer of an integrated circuit, a first layer of a first material, forming, on the first layer, a second layer of a second material, and patterning the second layer to expose the first layer. via the patterned second layer, the exposed first layer is etched to form protrusion structures of the first layer and the second layer and grooves between adjacent ones of the protrusion structures. the method also includes forming a graphitic carbon layer on at least part of the second layer of the protrusion structures, and depositing carbon nanotubes into the grooves between the adjacent ones of the protrusion structures.
Inventor(s): Gowrisankar Damarla of Lehi UT US for texas instruments incorporated, Robert Cassel of Lehi UT US for texas instruments incorporated, Zachary Katz of Lehi UT US for texas instruments incorporated, Ryan Rust of Lehi UT US for texas instruments incorporated
IPC Code(s): H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H10D62/115
Abstract: a method of forming an integrated circuit includes forming a first trench that extends into the semiconductor substrate. a silicon nitride layer is deposited over the semiconductor substrate. the silicon nitride layer extends into the first trench. a second trench is formed that extends through the silicon nitride layer into the semiconductor substrate. the second trench is spaced apart from the first trench. an oxide layer is formed that fills the second trench. the silicon nitride layer outside the first trench is removed.
Inventor(s): Henry Litzmann Edwards of Garland TX US for texas instruments incorporated
IPC Code(s): H01L29/49, H01L21/265, H01L21/266, H01L21/28, H01L21/3215, H01L29/06, H01L29/40, H01L29/66, H01L29/78
CPC Code(s): H10D64/671
Abstract: disclosed examples include microelectronic devices, e.g. integrated circuits, which include a source region and a drain region extending into a semiconductor substrate, the semiconductor substrate having a second conductivity type, the source region and drain region having an opposite first conductivity type. a channel region having the first conductivity type extends between the source region and the drain region. a gate electrode over the channel region has a first portion and a second portion. the first portion has the second conductivity type and a first dopant concentration. the second portion extends from the first portion toward the source region and has the second conductivity type and a second higher dopant concentration. a self-aligned implant is used to simultaneously implant dopants near the source end of the gate electrode and in the semiconductor substrate near the source region.
Inventor(s): Alexei Sadovnikov of Sunnyvale CA US for texas instruments incorporated
IPC Code(s): H01L29/78, H01L21/265, H01L29/66
CPC Code(s): H10D84/153
Abstract: a method forms an integrated circuit, by steps including, in a first implant, forming in a semiconductor substrate a first and second region of a first semiconductor type, each of the first and second region having a first dopant concentration; in a second implant, forming in the semiconductor substrate a third and fourth region of the first semiconductor type, the third region at least partially overlapping the first region and the fourth region at least partially overlapping the second region, each of the third and fourth region having a second dopant concentration different than the first dopant concentration; forming a transistor source within the first and third regions; and forming one of a diode anode or a diode cathode in the second and fourth regions.
TEXAS INSTRUMENTS INCORPORATED patent applications on April 3rd, 2025
- TEXAS INSTRUMENTS INCORPORATED
- G01D18/00
- G01D5/14
- CPC G01D18/001
- Texas instruments incorporated
- G01F1/66
- G01F1/667
- G01F1/7082
- G01F1/712
- G01F1/74
- G01N29/02
- G01N29/024
- G01N29/36
- G01N29/44
- CPC G01F1/66
- G01R31/28
- G01R35/00
- CPC G01R31/2834
- G01R31/319
- G01R31/317
- G01R31/3193
- CPC G01R31/31922
- G01R31/52
- G01R31/08
- H03M1/12
- H03M1/46
- CPC G01R31/52
- G01S13/87
- G01S7/285
- G01S13/76
- CPC G01S13/878
- G06F3/16
- CPC G06F3/162
- G06F17/14
- G06F7/50
- G06F7/523
- CPC G06F17/142
- G06F21/60
- G06F7/58
- G06F11/07
- G06F21/72
- CPC G06F21/602
- G06F21/75
- CPC G06F21/755
- H01F27/28
- H01F27/29
- H01F41/04
- H01L23/31
- H01L23/495
- CPC H01F27/2828
- H01F27/32
- H01F27/02
- H01L23/522
- H01L23/58
- H01L25/00
- H01L25/18
- CPC H01F27/323
- H01L23/373
- H01L21/56
- H01L23/00
- CPC H01L23/3735
- H01L25/065
- H01L29/16
- H01L29/20
- H01L29/778
- CPC H01L23/4951
- CPC H01L23/49565
- H01F17/00
- H05K3/46
- CPC H01L23/5227
- CPC H01L24/05
- H02J7/00
- B60L50/60
- CPC H02J7/0063
- H02M1/00
- G01R31/40
- H02M1/08
- H02M3/156
- CPC H02M1/0009
- H02M3/158
- G06F1/24
- H02M1/088
- CPC H02M3/158
- H02P6/182
- H02P6/08
- H02P6/15
- CPC H02P6/182
- H03F1/26
- H03F1/02
- H03F3/45
- H03K5/24
- CPC H03F1/26
- H03F3/217
- H03F1/32
- H03F3/38
- CPC H03F3/217
- H03K17/0812
- CPC H03K17/08122
- H03K19/0185
- H03K17/687
- CPC H03K19/018521
- H04B1/38
- H03F3/19
- H03K17/56
- CPC H04B1/38
- H04N19/192
- H04N19/103
- H04N19/107
- H04N19/119
- H04N19/147
- H04N19/169
- H04N19/176
- H04N19/51
- H04N19/52
- H04N19/593
- CPC H04N19/192
- H01L29/866
- H01L21/784
- H01L27/08
- H01L29/06
- CPC H10D8/25
- H01L29/786
- H01L21/02
- H01L29/66
- H01L29/775
- CPC H10D30/6757
- H01L29/40
- H01L29/423
- H01L29/78
- CPC H10D62/115
- H01L29/49
- H01L21/265
- H01L21/266
- H01L21/28
- H01L21/3215
- CPC H10D64/671
- CPC H10D84/153
