TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on January 9th, 2025
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. on January 9th, 2025
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 41 patent applications
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. has applied for patents in the areas of H01L29/66 (18), H01L29/423 (14), H01L29/06 (12), H01L29/786 (9), H01L29/78 (8) H01L29/0673 (3), H01L29/66795 (2), G01R31/2834 (1), H01L29/66174 (1), H01L29/0649 (1)
With keywords such as: layer, semiconductor, structure, gate, dielectric, device, region, substrate, circuit, and feature in patent application abstracts.
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s): Tai-Chun Huang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Ju Yu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Stefan Rusu of Sunnyvale CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B5/18, G02B6/293
CPC Code(s): G02B5/1823
Abstract: some embodiments relate to an optical module including a substrate; a first grating coupler overlying the substrate; and a second grating coupler overlying the first grating coupler, where the second grating coupler is configured to receive a first transverse mode of an input optical signal while passing a second transverse mode of the input optical signal to the first grating coupler, and where the first grating coupler is configured to receive the second transverse mode of the input optical signal.
Inventor(s): Yi-Hsin Nien of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hidehiro Fujiwara of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C5/06, G11C11/418
CPC Code(s): G11C5/063
Abstract: a memory device includes a first memory array comprising first memory cells; a second memory array comprising second memory cells; a third memory array comprising third memory cells, the second memory array interposed between the first memory array and the third memory array along a lateral direction; a first bit line segment extending along the lateral direction and coupled to each of the first memory cells; a second bit line segment extending along the lateral direction and coupled to each of the second memory cells; and a third bit line segment extending along the lateral direction and coupled to each of the third memory cells. the first bit line segment is formed in a first metallization layer, the second bit line segment is formed in a second metallization layer, and the third bit line segment is formed in a third metallization layer.
Inventor(s): Sheng-Chih LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Jun WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/39, H01L27/102, H01L29/66
CPC Code(s): G11C11/39
Abstract: a thyristor memory cell includes a semiconductor cathode, a first un-doped semiconductor feature connected to the semiconductor cathode, a second un-doped semiconductor feature connected to the first un-doped semiconductor feature, a semiconductor anode connected to the second un-doped semiconductor feature, and a gate feature disposed on the first un-doped semiconductor feature or the second un-doped semiconductor feature. among the semiconductor cathode, the first un-doped semiconductor feature, the second un-doped semiconductor feature and the semiconductor anode, the semiconductor anode has the highest bottom edge of conduction band, followed by the first un-doped semiconductor feature, the second un-doped semiconductor feature and the semiconductor cathode in the given order; and the semiconductor anode has the highest top edge of the valence band, followed by the first un-doped semiconductor feature, the second un-doped semiconductor feature and the semiconductor cathode in the given order.
Inventor(s): Jun-Cheng LIU of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd., Zhi-Min ZHU of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd., Chien-Yu HUANG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei WU of Nantou County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/4074, G11C11/4094, G11C11/4096
CPC Code(s): G11C11/4074
Abstract: a memory device is provided, including at least one bit cell, a pair of transistors, and a voltage generation circuit. the voltage generation circuit is coupled to the negative voltage line and is configured to pull down a voltage of at least one of the pair of data lines to a negative voltage level through the negative voltage line. the voltage generation circuit includes a first capacitive unit, a second capacitive unit, and a switch circuit. the first capacitive unit includes a first capacitor. the second capacitive unit includes a second capacitor. the switch circuit is configured to connect the first capacitor, the second capacitor, or the combination thereof to the negative voltage line in response to a first kick signal and a second kick signal that are different from each other.
Inventor(s): Ku-Feng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chieh LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kazumasa UNO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C17/12, G11C5/06, H01L23/522, H01L23/528, H10B20/00, H10B20/20
CPC Code(s): G11C17/12
Abstract: a method of generating an ic layout diagram includes dividing a column of nor-type read-only memory (rom) bit cells into a plurality of n-bit groups separated by isolation features, wherein each group includes the number of bits n greater than two, based on a rom code programming pattern of the column, assigning one or more logic patterns to each n-bit group of the plurality of n-bit groups, and storing an ic layout diagram including the logic patterns in a storage device.
Inventor(s): Zheng Yong LIANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ting YEH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., I-Han HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hao WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., An-Hsuan LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin CHAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Yun PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Chu LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/3105, H01L23/00, H01L29/66
CPC Code(s): H01L21/76819
Abstract: an integrated circuit (ic) chip with polish stop layers and a method of fabricating the ic chip are disclosed. the method includes forming a first ic chip having a device region and a peripheral region. forming the first ic chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. the method further includes performing a bonding process on the second dielectric layer to bond a second ic chip to the first ic chip.
Inventor(s): Fan Hsuan Chien of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Su-Yu Yeh of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Teng-Ta Hung of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Jen Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pei Yen Cheng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chi Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L29/78
CPC Code(s): H01L21/823481
Abstract: a method includes etching a gate stack to form a trench extending through the gate stack, the gate stack including a metal gate electrode and a gate dielectric, wherein forming the trench removes a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion; extending the trench through an isolation region under the gate stack and into a semiconductor substrate under the isolation region; conformally depositing a first dielectric material on surfaces in the trench; and depositing a second dielectric material on the first dielectric material to fill the trench, wherein the first dielectric material is a more flexible material than the second dielectric material.
Inventor(s): Kenichi Sano of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsiu Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pinyen Lin of Rochester NY (US) for taiwan semiconductor manufacturing company, ltd., Wei-Yen Woon of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L29/06, H01L29/423, H01L29/66
CPC Code(s): H01L21/823878
Abstract: methods of forming a metal gate structure of a stacked multi-gate device are provided. a method according to the present disclosure includes depositing a titanium nitride (tin) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the tin layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.
Inventor(s): Chih-Hong Wang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Shien Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ting Hao Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chia Lai of Zhunan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/48, H01L25/065
CPC Code(s): H01L23/3185
Abstract: gap-fill dielectrics for die structures and methods of forming the same are provided. in an embodiment, a device includes: an outer gap-fill dielectric having a first coefficient of thermal expansion; a first integrated circuit die in the outer gap-fill dielectric; a second integrated circuit die in the outer gap-fill dielectric; an inner gap-fill dielectric between the first integrated circuit die and the second integrated circuit die, the inner gap-fill dielectric having a second coefficient of thermal expansion, the second coefficient of thermal expansion being greater than the first coefficient of thermal expansion; and a third integrated circuit die over the inner gap-fill dielectric, the third integrated circuit die bonded to the first integrated circuit die and to the second integrated circuit die.
Inventor(s): Bi-Shen LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hua LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Dang TRINH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Yi YU of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yuan TSAI of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L23/532
CPC Code(s): H01L23/5223
Abstract: in some implementations described herein, a capacitor structure may include a metal-insulator-metal structure in which work function metal layers are included between the insulator layer of the capacitor structure and the conductive electrode layers of the capacitor structure. the work function metal layers may enable high-k dielectric materials to be used for the insulator layer in that the work function metal layers may provide an increased electron barrier height between the insulator layer and the conductive electrode layers, which may increase the breakdown voltage and may reduce the current leakage for the capacitor structure.
Inventor(s): Chieh-En Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hsien Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shyh-Fann Ting of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Chih Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L23/00, H01L23/48, H01L23/498, H01L25/065
CPC Code(s): H01L23/5226
Abstract: an integrated chip including a semiconductor substrate having a first side and a second side, opposite the first side. a first transistor and a second transistor are along the first side of the semiconductor substrate. a dielectric structure including a plurality of dielectric layers is under the first side of the semiconductor substrate. a first metal line is within the dielectric structure. a second metal line is within the dielectric structure and under the first metal line. a first metal via extends between the first metal line and the second metal line. a through-substrate via (tsv) extends from the second side of the semiconductor substrate, through the semiconductor substrate between the first transistor and the second transistor, to the first metal line and the second metal line.
Inventor(s): Yu-Chung Lai of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Yao Lai of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Chiu Huang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Ku Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-An Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Ting Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L23/00, H01L23/48, H01L23/498
CPC Code(s): H01L23/5389
Abstract: one aspect of the present disclosure pertains to an integrated (ic) structure. the ic structure includes a semiconductor substrate; an interconnect structure formed over the substrate; and a redistribution layer (rdl) structure formed over the interconnect structure. the rdl structure includes: a rdl pad portion having a pad via array with multiple vias landing on a first top metal line of the interconnect structure; a rdl signal routing portion having a signal routing via landing on a second top metal line of the interconnect structure; and a rdl top portion over the rdl pad portion and the rdl signal routing portion. the multiple vias of the pad via array include a block via and an adjacent sacrificial via, the block via having a block via width, the sacrificial via having a sacrificial via width, and the block via width is greater than the sacrificial via width.
Inventor(s): Chih CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Syuan HE of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Cheng SHIE of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/768, H01L23/48, H01L23/532
CPC Code(s): H01L24/80
Abstract: a method includes forming a first conductive feature over a first semiconductor structure; forming a first dielectric layer over the first conductive feature and the first semiconductor structure; removing a portion of the first dielectric layer to expose a top surface of the first conductive feature; forming a second conductive feature over a second semiconductor structure, wherein the first and second conductive features comprise nanotwinned copper; forming a second dielectric layer over the second conductive feature and the second semiconductor structure, wherein the second dielectric layer comprises a same material as the first dielectric layer; removing a portion of the second dielectric layer to expose a top surface of the second conductive feature; and performing a hybrid bonding process to bond the first dielectric layer to the second dielectric layer and bond the first conductive feature to the second conductive feature.
Inventor(s): Hsing-Yuan HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi Chen HO of Taichung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/36, H01L25/00
CPC Code(s): H01L25/0657
Abstract: the present disclosure provides a dummy die with improved thermal conductivity and warpage control. the dummy die includes an adjustment layer formed over a semiconductor substrate. the adjustment layer has a thermal conductivity in a range between about 30 w/mk and about 100 w/mk. the adjustment layer may include silicon nitride or silicon carbide.
Inventor(s): Sheng-Fu HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Fan CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L21/8252, H01L23/522
CPC Code(s): H01L27/0248
Abstract: providing a resistor between a gate of a target device (e.g., a gallium nitride (gan) high-electron-mobility transistor device) and a clamp circuit improves electrostatic discharge (esd) protection between an input/output (io) and the target device. for example, the resistor may result in esd protection between the io and a source of the target device and between the io and a drain of the target device may be at least 2 kilovolts under the human body model. because esd protection is improved, chances of burn out in the target device are reduced. additionally, larger currents may be applied in the clamp circuit without risk of esd.
Inventor(s): Pin-Hsin CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Heng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L21/8222, H02H9/04
CPC Code(s): H01L27/0255
Abstract: an integrated circuit includes a first horizontal conductor and a second horizontal conductor. the integrated circuit includes a first diode between a first first-type block and a first second-type block, a second diode between a second first-type block and a second second-type block, and a third diode between a third first-type block and a third second-type block. the first first-type block and the first second-type block are aligned along a first column. the second first-type block and the second second-type block are aligned along a second column. the third first-type block and the third second-type block are aligned along a third column. the second first-type block is connected to the first second-type block through the second horizontal conductor. the third first-type block is conductively connected to the second second-type block through the first horizontal conductor.
Inventor(s): Ken-Hao FAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ti Su of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Fu Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Hua Hsu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02
CPC Code(s): H01L27/0262
Abstract: a semiconductor device that includes an n-buried layer, a p-well region over the n-buried layer, an n-channel mosfet that includes an n-drain region, and a vertical npn bjt having a collector that is the n-drain region and a base that is the p-well region. the p-well region is floating.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Chao Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Cheng Lai of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng Liang of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chiang Hong of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Chang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L27/088
Abstract: a semiconductor device, a semiconductor chip and manufacturing methods thereof are provided. the semiconductor device includes: channel structures, vertically spaced apart from one another; a gate structure, intersecting the channel structures and wrapping around each of the channel structures; source/drain structures, in lateral contact with the channel structures from opposite sides of the channel structures; and protection structures, separately disposed along a bottom surface of the gate structure, wherein the channel structures are located between the protection structures, and the protection structures comprise a semiconductor material.
Inventor(s): Szu-Wei Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiun-Ming Kuo of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Ching Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Yi Chao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/311, H01L21/8234, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L27/0886
Abstract: the embodiments of the disclosure provide a finfet. the finfet includes a substrate, a first gate stack and a second gate stack. the substrate has a first fin and a second fin. the first gate stack is across the first fin and extends along a widthwise direction of the first fin. the second gate stack is across the second fin and extends along a widthwise direction of the second fin. a bottommost surface of the first gate stack is lower than a bottommost surface of the second gate stack, and a first gate height of the first gate stack directly on the first fin is substantially equal to a second gate height of the second gate stack directly on the second fin.
Inventor(s): Hsiang-Lin Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Shin Chu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yin-Kai Liao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sin-Yi Jiang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Wen Huang Chen of Nantou County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14607
Abstract: some embodiments relate to an integrated circuit light sensor device. the integrated circuit light sensor device includes a semiconductor substrate, as well as a plurality of first light-absorption regions and a plurality of second light-absorption regions located in the semiconductor substrate. each of the first light-absorption regions includes an implantation region of the semiconductor substrate. the implantation region and the semiconductor substrate form at least a portion of a corresponding one of a plurality of first photodetectors for a first light wavelength band. each of the second light-absorption regions includes a semiconductor material different from the semiconductor substrate. the semiconductor material forms at least a portion of a corresponding one of a plurality of second photodetectors for a second light wavelength band different from the first light wavelength band.
Inventor(s): Tien Yu Chu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Li Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Hsuan Kung of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsiao Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L27/088, H01L29/08, H01L29/78, H01L29/786
CPC Code(s): H01L29/0615
Abstract: semiconductor devices are provided. in one example, a semiconductor device includes: a substrate, a first circuit region and a second circuit region extending in a first direction, and a gate structure extending in a second direction that is substantially perpendicular to the first direction. the gate structure further includes: two gate electrode sections respectively located in the first and second circuit regions, and a low-resistance section between and interconnecting the two gate electrode sections. the two gate electrode sections are configured as gate electrodes for two transistors respectively located in the first and second circuit regions. the two gate electrodes have a first width (w) along the first direction, the low-resistance section has a second width (w) along the first direction, and a ratio of w to w(w/w) is at least 1.1.
Inventor(s): Shu KUAN of Keelung City (TW) for taiwan semiconductor manufacturing company, ltd., Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Han LEE of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chieh CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/161, H01L29/423
CPC Code(s): H01L29/0649
Abstract: in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. an inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. at least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.
Inventor(s): Yu-Lung TUNG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Xiaodong WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy LIAW of Zhudong Township, Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L27/092, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a semiconductor structure is provided. a logic cell includes first and second nanostructure transistors. the first nanostructure transistor is formed in a first active region over a first well region having a first conductivity type. the second nanostructure transistor is formed in a second active region over a second well region having a second conductivity type. the first and second nanostructure transistors share a gate structure. first and second source/drain features of the first nanostructure transistor are formed in the first active region. third and fourth source/drain features of the second nanostructure transistor are formed in a first portion and a second portion of the second active region, respectively. a first distance between the first active region and the first portion of the second active region is different from a second distance between the first active region and the second portion of the second active region.
Inventor(s): Wan Chen HSIEH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Zhen-Cheng WU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/02, H01L21/8234, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a method includes the following steps. a transistor including a first gate structure is formed on a first substrate. a first dielectric layer is deposited over the transistor using plasma enhanced atomic layer deposition (peald). a multilayer stack is formed on a second substrate. the multilayer stack comprises alternately stacked semiconductor layers and sacrificial layers. a second dielectric layer is deposited over the multilayer stack using a plasma enhanced atomic layer deposition (peald). the second dielectric layer is bonded with the first dielectric layer. the sacrificial layers are replaced with a second gate structure.
Inventor(s): Shi-Sheng Hu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Hung Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Tai Chan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a method for forming a semiconductor structure is provided. the method includes forming a fin structure over a substrate. the fin structure includes alternatingly stacked first semiconductor layers and second semiconductor layers. the method also includes laterally recessing the first semiconductor layers of the fin structure to form a plurality of notches, forming a plurality of inner spacers in the notches, laterally recessing the inner spacers to form a plurality of recesses in the inner spacers, and growing a source/drain feature over the fin structure. the recesses are sealed by the source/drain feature and the inner spacers to form a plurality of air spacers.
Inventor(s): Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Han LEE of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chee-Wee LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-En TSAI of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Ya LIN of Chaozhou Township (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chieh CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/161, H01L29/40, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/161
Abstract: the present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. the buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. the semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. the epitaxial structure includes germanium and tin.
Inventor(s): Jian-Zhi HUANG of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Tung LIN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., En-Cheng CHANG of Pingtung County (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Ying CHIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., I-Chih NI of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-I WU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/18, H01L29/16, H01L29/417, H01L29/43
CPC Code(s): H01L29/18
Abstract: a semiconductor device includes a substrate, a first dielectric layer, a channel layer and source/drain electrodes. the first dielectric layer is over the substrate. the channel layer is over the first dielectric layer. source/drain electrodes are over the channel layer. the source/drain electrodes comprise a 2d semimetal material. the channel layer comprises a 2d semiconductor material interfacing the 2d semimetal material of the source/drain electrodes.
Inventor(s): Guo-Zhou HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Kuan SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen Han HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ling-Sung WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L29/40, H01L29/423
CPC Code(s): H01L29/41775
Abstract: a method for manufacturing a semiconductor device includes: forming a transistor on a semiconductor substrate, in which the transistor includes a gate structure and a source/drain structure; forming a patterned dielectric layer on the semiconductor substrate, in which the patterned dielectric layer includes an opening extending from a top surface of the patterned dielectric layer to a top surface of the source/drain structure; forming a dielectric contact spacer to cover a sidewall of the opening; and forming a conductive contact in the opening such that the conductive contact is connected to the source/drain structure and is isolated from the gate structure by the dielectric contact spacer and the patterned dielectric layer.
Inventor(s): Georgios Vellianitis of Heverlee (BE) for taiwan semiconductor manufacturing company, ltd., Blandine Duriez of Bruxelles (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/02, H01L21/8234, H01L29/06, H01L29/423, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L29/41791
Abstract: an exemplary method includes forming an opening in an interlevel dielectric (ild) layer. the opening in the ild layer exposes a doped epitaxial layer. the method further includes performing an in-situ doping deposition process, an annealing process, and an etching process to form a doped semiconductor layer over the doped epitaxial layer. the doped semiconductor layer partially fills the opening. the method further includes forming a metal-comprising structure that fills a remainder of the opening. the metal-comprising structure is disposed over a top and sidewalls of the doped epitaxial layer. the doped semiconductor layer is disposed between the metal-comprising structure and the top of the doped epitaxial layer and between the metal-comprising structure and the sidewalls of the doped epitaxial layer. the in-situ deposition process may implement a temperature less than about 350� c. the doped epitaxial layer includes p-type dopant (e.g., boron), and the doped semiconductor layer includes gallium.
Inventor(s): Ming-Shuan Li of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Zi-Ang Su of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/423
CPC Code(s): H01L29/66174
Abstract: semiconductor structures and a method of forming the same are provided. in an embodiment, an exemplary semiconductor structure includes a doped region in a substrate and comprising a first-type dopant, a plurality of nanostructures disposed directly over the doped region, a gate structure wrapping around each nanostructure of the plurality of nanostructures, a first epitaxial feature and a second epitaxial feature coupled to the plurality of nanostructures, wherein each of the first epitaxial feature and the second epitaxial feature comprises the first-type dopant, a first insulation feature disposed between the first epitaxial feature and the doped region, and a second insulation feature disposed between the second epitaxial feature and the doped region.
Inventor(s): Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L29/66439
Abstract: a semiconductor structure is provided. the semiconductor structure includes forming an active region over a substrate, etching the active region to form a recess, forming a sacrificial layer in the recess, forming a source/drain feature over the sacrificial layer in the recess, removing the substrate, etching the active region and the sacrificial layer to form an opening exposing a backside surface of the source/drain feature, and forming a first contact plug in the opening.
Inventor(s): Tzu-Ging Lin of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chun Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jih-Jse Lin of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/3065, H01L29/78
CPC Code(s): H01L29/66795
Abstract: semiconductor devices and methods of fabrication are provided. a method includes providing a semiconductor structure with a first sidewall distanced from a second sidewall, fins located between the first sidewall and the second sidewall, and isolation regions located between the first sidewall and the second sidewall, wherein adjacent fins are separated by a respective isolation region. the method further includes performing a plasma etching process to etch the fins and the isolation regions, wherein the plasma etching process chemically etches the fins, wherein the plasma etching process physically etches the isolation regions to recesses defining a crown-shaped depth profile.
Inventor(s): Wen-Yi LIN of Tainan County (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Sheng HU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hao CHU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Chi CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/423, H01L29/775, H01L29/78
CPC Code(s): H01L29/66795
Abstract: a method of fabricating a semiconductor device includes providing a first fin extending from a substrate. in some embodiments, the method further includes forming a first gate stack over the first fin. in various examples, the method further includes forming a first doped layer along a surface of the first fin including beneath the first gate stack. in some cases, a first dopant species of the first doped layer is of a same polarity as a second dopant species of a source/drain feature of the semiconductor device.
Inventor(s): Yu-Lien HUANG of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Chun CHANG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/768, H01L21/8234, H01L23/485, H01L23/522, H01L23/532, H01L27/088, H01L29/08, H01L29/417, H01L29/66
CPC Code(s): H01L29/785
Abstract: a semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ild) layer formed over the electronic device, a wiring pattern formed on the ild layer and a contact formed in the ild layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. an insulating liner layer is provided on sidewalls of the contact between the contact and the ild layer. a height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ild layer and the wiring pattern.
Inventor(s): Chien-Hao HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Hsiang HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chang CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H. CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/66
CPC Code(s): H01L29/7869
Abstract: a semiconductor device includes a feol structure and a beol structure. the beol structure is formed over the feol structure and includes a barrier dielectric layer, a transistor and a first barrier. the barrier dielectric layer has an upper surface and a lower surface. the transistor is partially formed in the barrier dielectric layer and includes an electrode element, and the electrode element has a first lateral surface, wherein the first lateral surface extends from the upper surface toward the lower surface. the first barrier covers the entirety of the first lateral surface of the electrode element.
20250015800. LEVEL SHIFTER_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Wan-Yen Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hui Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Jung Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K17/689, H03K3/356, H03K19/0175, H03K19/0185
CPC Code(s): H03K17/689
Abstract: a level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. a cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. the input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. a tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.
Inventor(s): Shih-Yu Liao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Liang Cheng of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B12/00, H01L21/8234, H01L23/48, H01L27/088, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10B12/33
Abstract: memory cells, semiconductor devices, semiconductor stacked structures, and fabrication methods are provided. an example memory cell includes a capacitor and a transistor stacked over the capacitor in a compact configuration. the capacitor includes a floating gate, a high-k dielectric layer, and a metal gate. the metal gate extends horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface. the transistor includes the metal gate and a gate dielectric layer disposed on the metal gate. the gate dielectric layer includes two side portions respectively disposed on the two sidewalls of the metal gate and, and a top portion disposed on the top surface of the metal gate. the transistor further includes two separate s/d regions respectively formed on the two side portions of the gate dielectric layer, and a channel region formed on the top portion of the gate dielectric layer.
Inventor(s): Wen-Chao Shen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/25, H01L29/66, H01L29/78
CPC Code(s): H10B20/25
Abstract: a non-volatile memory (nvm) device. the nvm device includes: a semiconductor substrate having a plurality of fin-type structures; a select transistor formed on the semiconductor substrate, the select transistor including a gate layer disposed over a first dielectric isolation layer positioned over a first section of the plurality of fin-type structures, where the select transistor is a p-channel metal oxide semiconductor transistor; a storage device formed on the semiconductor substrate, the storage device including a storage gate layer disposed over a second dielectric isolation layer positioned over a second section on the plurality of fin-type structures, where the storage gate layer is arranged to trap charges, and where the storage device is a p-channel storage device, where the select transistor is coupled to the storage device; and the first section of the plurality of fin-type structures is adjacent to the second section of the plurality of fin-type structures.
Inventor(s): Yun-Feng Kao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H. Chiang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B43/35, G11C16/14, H01L23/522, H03K19/21
CPC Code(s): H10B43/35
Abstract: some embodiments relate to an integrated circuit including first and second charge-trapping devices and a control circuit. the first charge-trapping device includes a first charge-trapping structure arranged over a substrate between a first gate structure and a first channel region. the second charge-trapping device is coupled in series with the first charge-trapping device and includes a second charge-trapping structure arranged over the substrate between a second gate structure and a second channel region. the control circuit is coupled to the first and second gate structures and is configured to store a first input of an imply operation as a stored value of the first charge-trapping device, store a second input of the imply operation as a stored value of the second charge-trapping device, and update the stored value of the second charge-trapping device based on the stored value of the first charge-trapping device to perform the imply operation.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on January 9th, 2025
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- G02B5/18
- G02B6/293
- CPC G02B5/1823
- Taiwan semiconductor manufacturing company, ltd.
- G11C5/06
- G11C11/418
- CPC G11C5/063
- G11C11/39
- H01L27/102
- H01L29/66
- CPC G11C11/39
- G11C11/4074
- G11C11/4094
- G11C11/4096
- CPC G11C11/4074
- G11C17/12
- H01L23/522
- H01L23/528
- H10B20/00
- H10B20/20
- CPC G11C17/12
- H01L21/768
- H01L21/3105
- H01L23/00
- CPC H01L21/76819
- H01L21/8234
- H01L27/088
- H01L29/78
- CPC H01L21/823481
- H01L21/8238
- H01L29/06
- H01L29/423
- CPC H01L21/823878
- H01L23/31
- H01L21/56
- H01L23/48
- H01L25/065
- CPC H01L23/3185
- H01L23/532
- CPC H01L23/5223
- H01L23/498
- CPC H01L23/5226
- H01L23/538
- CPC H01L23/5389
- CPC H01L24/80
- H01L23/36
- H01L25/00
- CPC H01L25/0657
- H01L27/02
- H01L21/8252
- CPC H01L27/0248
- H01L21/8222
- H02H9/04
- CPC H01L27/0255
- CPC H01L27/0262
- H01L29/417
- H01L29/775
- CPC H01L27/088
- H01L21/311
- CPC H01L27/0886
- H01L27/146
- CPC H01L27/14607
- H01L29/08
- H01L29/786
- CPC H01L29/0615
- H01L29/161
- CPC H01L29/0649
- H01L27/092
- CPC H01L29/0673
- H01L21/02
- H01L29/40
- CPC H01L29/161
- H01L29/18
- H01L29/16
- H01L29/43
- CPC H01L29/18
- CPC H01L29/41775
- CPC H01L29/41791
- CPC H01L29/66174
- CPC H01L29/66439
- H01L21/3065
- CPC H01L29/66795
- H01L23/485
- CPC H01L29/785
- CPC H01L29/7869
- H03K17/689
- H03K3/356
- H03K19/0175
- H03K19/0185
- CPC H03K17/689
- H10B12/00
- CPC H10B12/33
- H10B20/25
- CPC H10B20/25
- H10B43/35
- G11C16/14
- H03K19/21
- CPC H10B43/35
