TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on January 23rd, 2025
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. on January 23rd, 2025
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 26 patent applications
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. has applied for patents in the areas of H01L29/66 (9), H01L21/8238 (8), H01L27/092 (8), H01L29/423 (7), H01L29/06 (6) H01L29/41791 (2), H01L23/481 (2), B25J15/0616 (1), H01L27/0924 (1), H01L27/092 (1)
With keywords such as: structure, layer, semiconductor, gate, dielectric, drain, source, transistor, substrate, and forming in patent application abstracts.
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s): Bo-Huan HSIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Han CHIOU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Cheng CHANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392
CPC Code(s): G06F30/392
Abstract: the present disclosure describes an example layout and method for cell placement in an integrated circuit (ic) layout design. the layout includes a first semiconductor structure having a first channel with a first channel width and a second semiconductor structure having a second channel with a second channel width different from the first channel width. the first and second channels can be in contact with each other. the method includes disposing a first diffusion region in a layout area and disposing a second diffusion region in the layout area. the first diffusion region can have a first diffusion region width and the second diffusion region can have a second diffusion region width different from the first diffusion region width.
Inventor(s): Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L21/8234, H01L27/088, H01L29/423
CPC Code(s): H01L21/28185
Abstract: semiconductor devices and methods of manufacturing are presented wherein a gate dielectric is treated within an analog region of a semiconductor substrate. the gate dielectric may be treated with a plasma exposure and/or an annealing process in order to form a recovered region of the gate dielectric. a separate gate dielectric is formed within a logic region of the semiconductor substrate, and a first gate electrode and second gate electrode are formed over the gate dielectrics.
Inventor(s): Ming-Feng LEE of Chiayi County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ting CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Chung LAI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522
CPC Code(s): H01L21/76804
Abstract: a method for forming an interconnection structure includes depositing a dielectric layer over a first interconnect layer, wherein the first interconnect layer comprises a first metallization layer; forming a via opening in the dielectric layer, and forming a conductive via in the via opening. forming the via opening includes: etching a recess in the dielectric layer above the first metallization layer; etching a first lateral recess in the dielectric layer at a sidewall of the recess; and after etching the first lateral recess, etching the recess downward to expose the first metallization layer.
Inventor(s): Szu-Ling Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/10, H01L23/00, H01L23/58
CPC Code(s): H01L23/10
Abstract: seal ring structures having alignment marks are disclosed herein. an exemplary semiconductor structure includes a seal ring surrounding a circuit region and a corner seal ring (csr) structure at an interior corner of the seal ring. the csr structure includes a bridge section between a first edge and a second edge of the seal ring, an l-shaped section between the seal ring and the bridge section and between the first edge and the second edge of the seal ring, a first area between the seal ring and the l-shaped section, and a second area between the l-shaped section and the bridge section. the seal ring includes a first top metal line and an aluminum pad (ap) disposed over and connected to the first top metal line. the l-shaped section includes a second top metal line having an l-shape. the first area and the second area are free of dummy ap.
Inventor(s): Yi-Ren CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Cheng CHI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48
CPC Code(s): H01L23/481
Abstract: a semiconductor device includes a substrate, a plurality of oxide definition structures, a plurality of metal gates and a first conductive via. the oxide definition structures are formed on the substrate and arranged in a first direction. the metal gates are formed on the substrate and extend in a second direction. the first conductive via is formed on the substrate, located between two of the metal gates, extends in the first direction and has a first width in the second direction. there is a pitch between adjacent two of the metal gates in the second direction, and a first ratio of the first width to the pitch ranges between 0.2 and 0.7.
Inventor(s): Chieh-En Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hsien Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shyh-Fann Ting of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/768, H01L23/522, H01L23/528
CPC Code(s): H01L23/481
Abstract: some embodiments relate to an integrated circuit device incorporating a dual via structure for through-chip connections. the integrated circuit device includes a substrate, at least one dielectric layer disposed over a frontside surface of the substrate, and a plurality of metal layers residing in the at least one dielectric layer. the integrated circuit device also includes a first via structure and a second via structure. the first via structure includes a plurality of vias. the first via structure is electrically connected to one of the plurality of metal layers and extends through the frontside surface of the substrate. the second via structure extends from a backside surface of the substrate opposite the frontside surface into the substrate and contacts the first via structure.
Inventor(s): Yun-Feng Kao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hao Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Gao-Ming Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H CHIANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H10B12/00
CPC Code(s): H01L23/5223
Abstract: a three-dimensional integrated structure and the manufacturing method(s) thereof are described. the three-dimensional integrated structure includes a substrate having conductive features therein, and a component array disposed over the substrate and on the conductive features. the component array includes a metallic material layer and capacitor structures separated by the metallic material layer. each of the capacitor structures includes a first metallic pillar, a first dielectric sheath surrounding the first metallic pillar, a second metallic sheath surrounding the first dielectric sheath, and a second dielectric sleeve surrounding the second metallic sheath. the metallic material layer laterally encapsulates the capacitor structures.
Inventor(s): Chun-Yuan CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi CHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/535, H01L21/02, H01L21/8234, H01L27/088, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L23/535
Abstract: an integrated circuit includes a substrate at a front side of the integrated circuit. a first gate all around transistor is disposed on the substrate. the first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. a shallow trench isolation region extends into the integrated circuit from the backside. a backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. the backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.
Inventor(s): Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Jung Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tai-Min Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L23/31, H01L23/528, H01L25/00
CPC Code(s): H01L24/14
Abstract: a package structure includes an integrated circuit die and an encapsulant laterally encapsulating the integrated circuit die. the integrated circuit die includes a semiconductor substrate, an interconnection structure, a testing pad, a dummy post, a conductive post, and a protection layer. the interconnection structure is disposed on the semiconductor substrate. the testing pad is disposed on the interconnection structure. the dummy post is disposed on the testing pad. the conductive post is aside the dummy post. the protection layer is disposed between the conductive post and the dummy post.
Inventor(s): Dian-Sheng YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hua PAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-He CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/12
Abstract: a semiconductor device is provided. the semiconductor device includes a first pull-down transistor, a first pull-up transistor, a second pull-down transistor, a second pull-up transistor, a first pass gate transistor, a second pass gate transistor, a first bit line, a second bit line, a word line and a voltage supply line. the first pull-down transistor and the first pull-up transistor form a first inverter. the second pull-down transistor and the second pull-up transistor form a second inverter. an input of the first inverter is connected to an output of the second inverter through a first node butted contact. the first node butted contact includes a metal contact directly contacted a gate of the first pull-down transistor and the first pull-up transistor and directly contacted a source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.
Inventor(s): Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jer-Fu Wang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chiang Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Fan Chang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/30, G11C5/06, H01L21/28, H01L29/51, H01L29/66, H01L29/78, H10B12/00, H10B51/10
CPC Code(s): H10B51/30
Abstract: a memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. the first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. the second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. the third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.
Inventor(s): Bo-Jiun Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Sheng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chao Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B53/30, H10B51/30
CPC Code(s): H10B53/30
Abstract: a method of forming a semiconductor device is provided. a first ferroelectric inducing layer including ru is deposited on a substrate. a ferroelectric layer including hfzro is deposited on the first ferroelectric inducing layer. a second ferroelectric inducing layer including ru is deposited on the ferroelectric layer, wherein the hfzro of the ferroelectric layer is in physical contact with the ru of the first ferroelectric inducing layer and the ru of the second ferroelectric inducing layer. the second ferroelectric inducing layer, the ferroelectric layer and the first ferroelectric inducing layer are patterned.
Inventor(s): Mu-Min Hung of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Fan Hsuan Chien of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jyh-Nan Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Shiung Hsu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chien Cheng of Bade City (TW) for taiwan semiconductor manufacturing company, ltd., Su-Yu Yeh of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/66795
Abstract: a semiconductor device with a barrier layer between a gate structure and gate spacer layers, and a method of fabricating the same are disclosed. the a method includes forming a fin structure on a substrate, forming a polysilicon structure on the fin structure, performing a nitridation operation to form a barrier layer on the polysilicon structure and the fin structure, forming gate spacer layers on the barrier layer, forming a source/drain region in the fin structure and adjacent to the barrier layer, annealing the gate spacer layers, and replacing the polysilicon structure with a gate structure.
Inventor(s): Wei-Hao Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan Yu Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/66, H01L29/78
CPC Code(s): H01L29/41791
Abstract: a method includes forming an epitaxial source/drain region in a substrate; forming a first inter-layer dielectric over the epitaxial source/drain region; forming a gate stack over the substrate and adjacent to the first inter-layer dielectric; forming a gate mask over the gate stack; forming a source/drain plug through the first inter-layer dielectric and electrically connected to the epitaxial source/drain region; depositing a dielectric layer over the gate mask and the first inter-layer dielectric, the dielectric layer having a different etch selectivity than the gate mask; forming a second inter-layer dielectric over the dielectric layer; etching an opening through the second inter-layer dielectric and the dielectric layer, the opening exposing the source/drain plug and the gate mask; and forming a conductive feature in the opening, the conductive feature being electrically connected to the source/drain plug.
Inventor(s): Min-Hsuan LU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Tsung WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh SU of Tianzhong Township (TW) for taiwan semiconductor manufacturing company, ltd., Tzu Pei CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Heng LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hung LIN of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/66, H01L29/78
CPC Code(s): H01L29/41791
Abstract: a semiconductor device may include one or more transistor structures that include a plurality of source/drain regions and a gate structure between the source/drain regions. the semiconductor device may further include one or more dielectric layers between a source/drain contact structure and a gate structure of the one or more of the transistor structures. the one or more dielectric layers may be manufactured using on oxidation treatment process to tune the dielectric constant of the one or more dielectric layers. the dielectric constant of the one or more dielectric layers may be tuned to reduce the parasitic capacitance between the source/drain contact structure and the gate structure (which are conductive structures). in particular, the dielectric constant of the one or more spacer dielectric may be tuned using the oxidation treatment process to lower the as-deposited dielectric constant of the one or more dielectric layers.
Inventor(s): Che Chi SHIH of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Jhih-Rong HUANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Han-Yu LIN of Nantou County (TW) for taiwan semiconductor manufacturing company, ltd., Ku-Feng YANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yen WOON of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya LIAO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8238, H01L23/373, H01L27/092, H01L29/06, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/42392
Abstract: method to implement heat dissipation multilayer and reduce thermal boundary resistance for high power consumption semiconductor devices is provided. the heat dissipation multilayer comprises a first crystalline layer that possesses a first phonon frequency range, a second crystalline layer that has a second phonon frequency range which does not overlap with the first phonon frequency range, and an amorphous layer located between the first and second crystalline layers. the amorphous layer has a third phonon frequency range that overlaps both the first and second phonon frequency ranges.
Inventor(s): Kuan-Kan Hu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chin Chang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Olivia Pei-Hua Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ku-Feng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L27/088, H01L29/417, H01L29/423, H01L29/49, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: method to form low-contact-resistance contacts to source/drain features are provided. a method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, selectively depositing a first silicide layer on the surface of the p-type source/drain feature while the surface of the n-type source/drain feature is substantially free of the first silicide layer, depositing a metal layer on the first silicide layer and the surface of the n-type source/drain feature, and depositing a second silicide layer over the metal layer. the selectively depositing includes passivating the surface of the surface of the n-type source/drain features with a self-assembly layer, selectively depositing the first silicide layer on the surface of the p-type source/drain feature, and removing the self-assembly layer.
Inventor(s): Yu-Heng Cheng of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Chi Huang of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/08, H01L29/423, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/66545
Abstract: provided are semiconductor dies and methods for manufacturing semiconductor devices on a die. a method for manufacturing semiconductor devices on a die includes forming semiconductor devices with a gate length of 3 nanometers (nm) and having metal gates, wherein over 99% of the semiconductor devices with the gate length of 3 nanometers (nm) have a gate height of from 10 to 14 nanometers (nm).
Inventor(s): Jhih-Rong HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mrunal Abhijith KHADERBAD of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Bo LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Tien TUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yen WOON of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L27/088, H01L27/092, H01L29/40, H01L29/45
CPC Code(s): H01L29/41725
Abstract: a semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. the first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. the first source/drain portion has a conductivity type different from that of the second source/drain portion. the first and second metal contacts are respectively formed on the first and second source/drain portions. the first conductive carbon layer is formed between the first source/drain portion and the first metal contact.
Inventor(s): Yu-Hung Lin of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Jih-Churng Twu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Su-Chun Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Peng Tai of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hao Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/822, H01L21/3065, H01L21/311, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L25/065
CPC Code(s): H01L21/8221
Abstract: a method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.
Inventor(s): Chun Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zheng Hui Lim of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen Chuang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Shun-Siang Jhan of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ching Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ji-Yin Tsai of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238
CPC Code(s): H01L21/823828
Abstract: in an embodiment, a method includes: patterning a lower semiconductor nanostructure, an upper semiconductor nanostructure, and a dummy nanostructure, the dummy nanostructure disposed between the lower semiconductor nanostructure and the upper semiconductor nanostructure, the dummy nanostructure including doped silicon; forming an opening between the lower semiconductor nanostructure and the upper semiconductor nanostructure by etching the doped silicon of the dummy nanostructure; forming an isolation structure in the opening; and depositing a gate dielectric around the isolation structure, the upper semiconductor nanostructure, and the lower semiconductor nanostructure.
Inventor(s): Wei-Chih HOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Ming CHANG of Taitung City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Jun LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kao-Ting LAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L21/823807
Abstract: a method for forming a semiconductor device structure is provided. the method includes forming a first fin structure and a second fin structure. each of the first fin structure and the second fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner, and the first fin structure is substantially as wide as the second fin structure. the method also includes forming a gate stack wrapped around the first fin structure and the second fin structure. the method further includes simultaneously removing the sacrificial layers of the first fin structure and the second fin structure. remaining portions of the semiconductor layers of the first fin structure form multiple first semiconductor nanostructures, and remaining portions of the semiconductor layers of the second fin structure form multiple second semiconductor nanostructures. each of the first semiconductor nanostructures is thicker than each of the second semiconductor nanostructures.
Inventor(s): Feng-Ming CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Che-Chia Hsu of Taoyuan city (TW) for taiwan semiconductor manufacturing company, ltd., Kao-Ting Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238
CPC Code(s): H01L27/092
Abstract: a semiconductor device includes a plurality of first nanosheets of a first conductive type, a plurality of second nanosheets of a second conductive type and a gate structure. the gate structure wraps the first nanosheets and the second nanosheets, wherein a first thickness of at least one of the first nanosheets is smaller than a second thickness of at least one of the second nanosheets.
Inventor(s): Chung-Hui Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Ching Chang of Dali City (TW) for taiwan semiconductor manufacturing company, ltd., Weichih Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wan-Te Chen of Danshui Township (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Hsin Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Hsiang Hsieh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, G06F30/327, G06F30/36, G06F30/392, G06F115/06, G06F117/12
CPC Code(s): H01L27/0924
Abstract: an integrated circuit (ic) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. the smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.
Inventor(s): Sheng Chieh CHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu Yen KUNG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Tsun-Kai TSAO of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ming Chyi LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1463
Abstract: embodiments of the present disclosure relate to a structure, which includes a plurality of photodiode doping regions formed in a substrate, and a deep trench isolation (dti) structure formed in the substrate, wherein the dti structure separates photodiode doping regions, and the dti structure comprises a first filling material defining an air gap therein. the first filling material includes a top, a sidewall, and a bottom. the structure also includes a first isolation layer surrounding and in contact with the top, the sidewall, and the bottom of the first filling material.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on January 23rd, 2025
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- G06F30/392
- CPC G06F30/392
- Taiwan semiconductor manufacturing company, ltd.
- H01L21/28
- H01L21/8234
- H01L27/088
- H01L29/423
- CPC H01L21/28185
- H01L21/768
- H01L23/522
- CPC H01L21/76804
- H01L23/10
- H01L23/00
- H01L23/58
- CPC H01L23/10
- H01L23/48
- CPC H01L23/481
- H01L23/528
- H10B12/00
- CPC H01L23/5223
- H01L23/535
- H01L21/02
- H01L29/06
- H01L29/417
- H01L29/66
- H01L29/786
- CPC H01L23/535
- H01L21/56
- H01L23/31
- H01L25/00
- CPC H01L24/14
- H10B10/00
- CPC H10B10/12
- H10B51/30
- G11C5/06
- H01L29/51
- H01L29/78
- H10B51/10
- CPC H10B51/30
- H10B53/30
- CPC H10B53/30
- H01L21/8238
- H01L27/092
- H01L29/775
- CPC H01L29/66795
- CPC H01L29/41791
- H01L23/373
- CPC H01L29/42392
- H01L29/49
- CPC H01L29/0673
- H01L29/08
- CPC H01L29/66545
- H01L29/40
- H01L29/45
- CPC H01L29/41725
- H01L21/822
- H01L21/3065
- H01L21/311
- H01L23/498
- H01L25/065
- CPC H01L21/8221
- CPC H01L21/823828
- CPC H01L21/823807
- CPC H01L27/092
- G06F30/327
- G06F30/36
- G06F115/06
- G06F117/12
- CPC H01L27/0924
- H01L27/146
- CPC H01L27/1463