TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on February 20th, 2025
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. on February 20th, 2025
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 98 patent applications
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. has applied for patents in the areas of H01L29/66 (24), H01L23/00 (20), H01L29/06 (14), H01L29/423 (12), H01L21/02 (11) H01L29/66545 (4), H01L23/562 (3), H01L23/5283 (2), H01L29/785 (2), H01L27/0266 (2)
With keywords such as: layer, semiconductor, structure, gate, substrate, region, device, forming, disposed, and dielectric in patent application abstracts.
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s): Zheng Long CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): A61B17/22, A61B17/00, A61B17/3203, A61B90/10, A61M5/00, A61M25/00, A61M25/01
CPC Code(s): A61B17/22
Abstract: an integrated circuit includes a drain in a substrate, wherein the drain comprising a doped drain well. the doped drain well includes a first zone, wherein the first zone has a first concentration of a first dopant; and a second zone, wherein the second zone has a second concentration of the first dopant, a top-most surface of the first zone is coplanar with a top-most surface of the second zone, and the first concentration is different from the second concentration. the integrated circuit further includes a gate electrode over the substrate, the gate electrode being separated from each of the first zone and the second zone in a direction parallel to a top surface of the substrate by a distance greater than 0.
Inventor(s): Zheng-Long CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): A61N1/372, A61N1/05, A61N1/36
CPC Code(s): A61N1/37247
Abstract: a semiconductor device includes substrate, a first gate structure, a second gate structure, and an epitaxy layer. the first gate structure and the second gate structure are over the substrate, in which the first gate structure and the second gate structure each comprises a shielding electrode, a gate electrode over the shielding electrode, and a first gate dielectric layer vertically separating the shielding electrode from the gate electrode. the epitaxy layer is over the substrate and cups an underside of the first gate structure and the second gate structure, in which the epitaxy layer comprises a doped region laterally between the first gate dielectric layer of the first gate structure and the first gate dielectric layer of the second gate structure, a dopant concentration of the doped region being non-uniform along a lateral direction.
Inventor(s): Chia-Ming HUNG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chuan TAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Heng CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Da WANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Fu CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B06B1/02, B81B3/00, B81B7/02
CPC Code(s): B06B1/0292
Abstract: a micro-electromechanical-system (mems) device may include a capacitive micromachined ultrasonic transducer (cmut) that includes an actuation membrane and a sensing dielectric layer that are spaced apart by a cavity. the sensing dielectric layer may be formed such that the thickness of the sensing dielectric layer may extend the operational of the cmut while enabling the cmut to accommodate a sufficiently high direct current voltage bias for collapsed mode operation. in this way, the thickness of the sensing dielectric layer enables the cmut to operate in the collapsed mode, which enables the cmut to achieve greater sound pressure output relative to other operational modes and enables the frequency response of the cmut to be adjustable, thereby enabling the frequency response to be optimized for specific use cases and applications.
Inventor(s): Yu-Ann LAI of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Ruo-Rung HUANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Kun-Lung CHEN of Chu Pei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yi YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chan-Hong CHERN of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R31/26, G01R31/27, H03K3/017, H03K17/687
CPC Code(s): G01R31/2621
Abstract: an apparatus and method for testing gallium nitride field effect transistors (gan fets) are disclosed herein. in some embodiments, the apparatus includes: a high side gan fet, a low side gan fet, a high side driver coupled to a gate of the high side gan fet, a low side driver coupled to a gate of the low side gan fet, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side gan fets, wherein the high and low side gan fets and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (feol) process.
Inventor(s): Hsing-Kuo Hsia of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Yu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ren-Fen Tsui of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Jui Lin Chao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/293, G02B6/12
CPC Code(s): G02B6/29338
Abstract: optical devices and methods of manufacture are presented in which a resonant ring is incorporated with a optical device on an interposer substrate. the material for the resonant ring may be a material that can trigger second order non-linearity in received light or a material that can trigger third order non-linearity without electrical driving mechanisms.
Inventor(s): Feng-Wei KUO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Shiang Liao of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/34, G02B6/124, G02B6/13, H01L21/02
CPC Code(s): G02B6/34
Abstract: a semiconductor structure including a semiconductor substrate, a first patterned dielectric layer, a grating coupler and a waveguide is provided. the semiconductor substrate includes an optical reflective layer. the first patterned dielectric layer is disposed on the semiconductor substrate and covers a portion of the optical reflective layer. the grating coupler and the waveguide are disposed on the first patterned dielectric layer, wherein the grating coupler and the waveguide are located over the optical reflective layer.
Inventor(s): Che-Hsiang Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shi Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chieh Hsieh of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Yi Kuo of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yuan Yu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hua-Kuei Lin of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ming Weng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4214
Abstract: a package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. the prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.
Inventor(s): Lan-Chou CHO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chewn-Pu JOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Min-Hsiang HSU of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02F1/225, G02F1/21
CPC Code(s): G02F1/2255
Abstract: apparatus, circuits and methods for reducing mismatch in an electro-optic modulator are described herein. in some embodiments, a described optical includes: a splitter configured for splitting an input optical signal into a first optical signal and a second optical signal; a phase shifter coupled to the splitter; and a combiner coupled to the phase shifter. the phase shifter includes: a first waveguide arm configured for controlling a first phase of the first optical signal to generate a first phase-controlled optical signal, and a second waveguide arm configured for controlling a second phase of the second optical signal to generate a second phase-controlled optical signal. each of the first and second waveguide arms includes: a plurality of straight segments and a plurality of curved segments. the combiner is configured for combining the first and second phase-controlled optical signals to generate an output optical signal.
Inventor(s): Cheng-Yeh LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Fang YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsueh-Wei HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Cheng HO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yi YIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/42
CPC Code(s): G03F1/42
Abstract: a method includes: generating a designed mask overlay mark associated with an actual mask overlay mark to be formed in a mask; forming the actual mask overlay mark in the mask based on the designed mask overlay mark, the actual mask overlay mark including a plurality of overlay patterns; forming a device feature pattern adjacent to the actual mask overlay mark; forming an alignment of the mask by a mask metrology apparatus including a light source having a wavelength and a numerical aperture, wherein a pitch between adjacent two of the plurality of overlay patterns does not exceed the wavelength divided by twice the numerical aperture; and forming a pattern in a layer of a wafer by transferring the device feature pattern while the mask is under the alignment.
Inventor(s): Tzu-Ang CHAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Ching CHENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Han WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Yang LI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Gregory Michael PITNER of Sunnyvale CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/62, G03F1/64
CPC Code(s): G03F1/62
Abstract: a pellicle for an euv photo mask includes a first layer, a second layer, and a main membrane disposed between the first layer and second layer. the main membrane includes a plurality of co-axial nanotubes, each of which includes an inner tube and one or more outer tubes surrounding the inner tube, and two of the inner tube and one or more outer tubes are made of different materials from each other.
Inventor(s): Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Jung Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tai-Min Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/42, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L23/538
CPC Code(s): G03F7/426
Abstract: a method for removing a resist layer including the following steps is provided. a patterned resist layer on a material layer is formed. a stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.
Inventor(s): Ming-Hung CHANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Luping KONG of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd., Jun XIE of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd., Ching-Wei WU of Nantou County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F1/08, G11C16/24, G11C16/28
CPC Code(s): G06F1/08
Abstract: a memory device is provided and includes a memory array, first to second latch circuits and a gating circuit. read and write operations are triggered by first and second edges of an internal clock signal respectively. the first latch circuit generates a first output signal in response to an input signal and a first latch clock signal, a first edge of the first latch clock signal generated based on the first edge of the internal clock signal. the second latch circuit generates a second output signal in response to the first output signal and a second latch clock signal, a first edge of the second latch clock signal being between first and second edges of the first latch clock signal. the gating circuit generates, in response to the second output signal and a gating clock generated, a third output signal to the memory array.
Inventor(s): Saman M. I. ADHAM of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ramin SHARIAT-YAZDI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Lien Linus LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F11/10, G06F12/14
CPC Code(s): G06F11/1016
Abstract: a memory circuit includes: a memory configured to store a data unit and a corresponding first code; a decoding circuit configured to do as follows including, generate a second code based on a read address associated with the stored data unit, and generate a decoded write address based on the second code; a first error detecting circuit configured to do as follows including, determine an address fault by performing a first comparison between the read address and the decoded write address, and generate an error signal indicative of a result of the first comparison.
Inventor(s): Shang-Chih HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Fu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Wei CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Jen TSENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, H01L21/768, H01L27/02, H01L27/118
CPC Code(s): G06F30/392
Abstract: an integrated circuit includes a plurality of routing lines extending along a first direction, the plurality of routing lines being separated in the first direction by integral multiples of a nominal minimum pitch. the integrated circuit includes a plurality of standard cells, at least one of the plurality of standard cells having a first boundary coinciding with a routing line of the plurality of routing lines, and a second boundary offset from each of the plurality of routing lines.
Inventor(s): Sanjeev Kumar Jain of Ottawa (CA) for taiwan semiconductor manufacturing company, ltd., Sahil Preet Singh of Amritsar (IN) for taiwan semiconductor manufacturing company, ltd., Atul Katoch of Kanata (CA) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/12, G11C7/10, G11C7/20
CPC Code(s): G11C7/12
Abstract: systems and methods are provided for controlling a wake-up operation of a memory circuit. the memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. the first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. the first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. the first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal. the second logic circuitry may be configured to generate a second bit line pre-charge signal for a second memory cell of the plurality of memory cells, where the second bit line pre-charge signal is generated in response to the delayed sleep signal. the second switching circuitry may be configured to provide power to one or more bit line of the second memory cell in response to the second bit line pre-charge signal.
20250061934. MEMORY REFRESH_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Perng-Fei YUH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/406, G11C11/408, G11C11/4099
CPC Code(s): G11C11/40615
Abstract: limiting a leakage current of a memory device is provided. a sensing current that is a representative of a leakage current of a memory cell array of a memory device is generated. a reference current having a preset value is generated. the sensing current is compared with the reference current. an enable signal is generated based on the comparison. a bias voltage applied to a plurality of word lines of the memory cell array is adjusted based on the enable signal.
Inventor(s): Sanjeev Kumar Jain of Ottawa (CA) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419, G11C11/418
CPC Code(s): G11C11/419
Abstract: circuits and methods are described herein for controlling a bit line precharge circuit. for example, a control circuit includes a first latch circuit and a second latch circuit. the first latch circuit is configured to receive a first light sleep signal. the first latch circuit generates a second light sleep signal according to a clock signal. the second latch circuit is configured to receive the second light sleep signal. the second latch circuit generates a third light sleep signal according to a sense amplifier enable signal. the second latch circuit provides the third light sleep signal to a bit line reading switch, so the bit line reading switch is cutoff after a sense amplifier is enabled.
Inventor(s): Hung-Te Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei Liu of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Chih Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L21/266, H01L21/308, H01L21/761, H01L29/66
CPC Code(s): H01L21/02496
Abstract: in a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. the semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. with the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. with the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. after filling the containment structure with the base semiconductor material, the mask is removed. at least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.
Inventor(s): Su-Chun Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jui Hsuan Tsai of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jih-Churng Twu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shi Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/266, H01L21/762
CPC Code(s): H01L21/266
Abstract: a method of a semiconductor-on-insulator structure includes the following steps. a semiconductor donor substrate is provided. a first implantation process is performed to form an exfoliation layer of the semiconductor donor substrate with a first ion concentration. a second implantation process is performed on a perimeter region of the exfoliation layer to form a high concentration region of the exfoliation layer with a second ion concentration higher than the first ion concentration. the semiconductor donor substrate is bonded to a semiconductor handle substrate, so that the exfoliation layer with the high concentration region is bonded to the semiconductor handle substrate. an annealing process is performed to separate the exfoliation layer from the rest of the semiconductor donor substrate.
Inventor(s): Ming-Tsu Chung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chi Lin of Su-Lin City (TW) for taiwan semiconductor manufacturing company, ltd., Yan-Zuo Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yang-Chih Hsueh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Shih Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/56, H01L23/00, H01L23/31, H01L23/48, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L21/56
Abstract: a method includes bonding a device die onto a package component. the device die includes a semiconductor substrate, and a through-via extending into the semiconductor substrate. the method further includes depositing a dielectric liner lining sidewalls of the device die, depositing a dielectric layer on the dielectric liner, and planarizing the dielectric layer and the device die. remaining portions of the dielectric liner and the dielectric layer form a gap-filling region, and a top end of the through-via is revealed. an implantation process is performed to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. a redistribution line is formed over and electrically connecting to the through-via.
Inventor(s): Tzu-Hsuan CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Rong-Teng Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Bi-Xian Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Teng-Chin Hsu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Hong Yang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Liang Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jam-Wem Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ji Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wun-Jie Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/56, C08J3/09, C08K3/04, C08L1/02, H01L23/00, H01L23/29, H01L23/31, H01L25/10
CPC Code(s): H01L21/565
Abstract: a method for fabricating a package structure is provided. the method includes premixing cellulose nanofibrils (cnfs) and a graphene material in a solvent to form a solution; removing the solvent from the solution to form a composite filler; mixing a prepolymeric material with the composite filler to form a composite material; and performing a molding process using the composite material.
Inventor(s): De-Wei YU of Pingtung (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chia CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hua YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsueh-Chang SUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chii-Horng LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, F27B17/00, H01L29/66
CPC Code(s): H01L21/67017
Abstract: embodiments of the present disclosure provide a furnace for semiconductor processing that includes an inner tube defining a reaction chamber and including a sidewall defined along a longitudinal axis of the inner tube and including one or more slits defined through the sidewall in a radial direction with respect to the longitudinal axis. the one or more slits include at least one of a first slit with a width in a range between 10 mm and 100 mm, or a plurality of separate slits with a total number in a range between 2 and 15. the inner tube includes a closed end substantially enclosing the reaction chamber and an open end opposite the closed end with respect to the longitudinal axis. the reaction chamber is configured to be loaded with one or more semiconductor wafers via the open end.
Inventor(s): Jieh-Chau HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ying Ting Hsia of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Jung Huang of Douliou (TW) for taiwan semiconductor manufacturing company, ltd., Pei Yen Hsia of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Bi-Ming Yen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Lung Hu of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, H01L21/673, H01L21/687
CPC Code(s): H01L21/67051
Abstract: the present disclosure relates to an apparatus for wafer cleaning. the apparatus includes an enclosure made of a noncombustible material, a wafer holder, a cleaning nozzle, at least one sensor, and an exhaust unit. the wafer holder can hold and heat a wafer. the cleaning nozzle can supply a flow of a cleaning fluid onto a surface of the wafer. the at least one sensor can detect attributes of the wafer. the exhaust unit can expel a vapor generated by the cleaning fluid in the enclosure. the exhaust unit can include a rinse nozzle to rinse the vapor passing through the exhaust unit with a mist.
Inventor(s): Jie CHEN of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Chuang LI of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Qiang SU of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Haobo NI of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, H01L21/02, H01L21/677
CPC Code(s): H01L21/67086
Abstract: a method includes placing a wafer in a process bath filled with a process solution; determining whether the wafer is in the process bath after a pre-set process time after placing the wafer in the process bath; and in response the determination determines that the wafer is in the process bath after the pre-set process time, draining the process solution from the process bath while the wafer is in the process bath.
Inventor(s): Rong Syuan FAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Yuan CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Hsuan LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/677, B60L1/00, B60L50/60, G05B19/418, H01L21/673
CPC Code(s): H01L21/67724
Abstract: a semiconductor processing system includes a first semiconductor processing site and a second semiconductor processing site. the system includes an unmanned electric vehicle configured to carry a portable cleanroom stocker between the first and second semiconductor processing sites. the portable cleanroom stocker is configured to maintain cleanroom conditions within the portable cleanroom stocker during transportation.
Inventor(s): Chien-Fa LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsu-Shui LIU of Pingjhen City (TW) for taiwan semiconductor manufacturing company, ltd., Jiun-Rong PAI of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shou-Wen KUO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Hung CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., M.C. LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., C.C. CHIEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsuan LEE of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Boris HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/683, H01L21/02, H01L21/304, H01L21/66
CPC Code(s): H01L21/6836
Abstract: a system and method for cleaning ring frames is disclosed. in one embodiment, a ring frame processing system includes: a plurality of blades for mechanically removing tapes and tape residues from surfaces of a ring frame; a plurality of wheel brushes for conditioning the surfaces of the ring frame; and a transport mechanism for transporting the ring frame.
Inventor(s): Wen-Li CHIU of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Kuo of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Hsiang Su of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hsun Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L21/76232
Abstract: a method for forming a semiconductor device structure is provided. the method includes providing a substrate having a base and a fin over the base. the method includes forming a first gate stack wrapped around the fin. the method includes forming a first gate spacer over a first sidewall of the first gate stack. the method includes partially removing the fin, which is not covered by the first gate stack and the first gate spacer. the method includes removing a first upper portion of the first gate stack to expose a second upper portion of the first gate spacer. the method includes removing the second upper portion of the first gate spacer. the method includes removing a first lower portion of the first gate stack and the fin originally wrapped by the first gate stack. the method includes forming a dielectric channel-cut structure in the trench.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Liang Shao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L21/265, H01L21/268
CPC Code(s): H01L21/76254
Abstract: a method includes implanting a substrate with a dopant to form an implanted layer in the substrate, and the implanted layer is at an intermediate level between a top surface and a bottom surface of the substrate. a laser beam is projected on the implanted layer, and is projected on a sidewall of the substrate. after the laser beam is projected, the substrate is heated, so that the substrate is cut at the implanted layer, and is cut into a top portion and a bottom portion.
Inventor(s): Chen-Ming Lee of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/8238, H01L23/48, H01L27/088
CPC Code(s): H01L21/76898
Abstract: in an embodiment, an exemplary method includes forming a source/drain opening extending into a substrate, forming a semiconductor layer in a bottom portion of the source/drain opening, forming a dielectric feature in the source/drain opening and on the semiconductor layer, epitaxially growing a source/drain feature in the source/drain opening, wherein the source/drain feature is in direct contact with the dielectric feature, removing the semiconductor layer and a portion of the substrate disposed directly under the semiconductor layer to form a trench, selectively removing the dielectric feature to enlarge the trench, after the selectively removing of the dielectric feature, forming a silicide layer in the enlarged trench, and depositing a conductive layer in the enlarged trench and in direct contact with the silicide layer.
Inventor(s): Chen-Hung LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Chin CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsien LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, C23C14/06, C23C14/18, C23C14/35, C23C14/54, H01J37/34, H01L21/285
CPC Code(s): H01L22/26
Abstract: embodiments are directed to a method of optimizing thickness of a target material film deposited on a semiconductor substrate in a semiconductor processing chamber, wherein the semiconductor processing chamber includes a magnetic assembly positioned on the semiconductor processing chamber, the magnetic assembly including a plurality of magnetic columns within the magnetic assembly. the method includes operating the semiconductor processing chamber to deposit a film of target material on a semiconductor substrate positioned within the semiconductor processing chamber, measuring an uniformity of the deposited film, adjusting a position of one or more magnetic columns in the magnetic assembly, and operating the semiconductor processing chamber to deposit the film of the target material after adjusting position of the one or more magnetic columns.
Inventor(s): Chun-Liang LU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Wei CHIA of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hao CHOU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng LEE of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, H01L23/00, H01L23/58
CPC Code(s): H01L22/34
Abstract: a semiconductor device includes a first wafer and a second wafer. the semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsun Lee of Chu-tung Town (TW) for taiwan semiconductor manufacturing company, ltd., Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/48, H01L21/56, H01L23/00, H01L23/498
CPC Code(s): H01L23/3114
Abstract: an integrated fan out package is utilized in which the dielectric materials of different redistribution layers are utilized to integrate the integrated fan out package process flows with other package applications. in some embodiments an ajinomoto or prepreg material is utilized as the dielectric in at least some of the overlying redistribution layers.
Inventor(s): Jian WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Feng HAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shuai ZHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/36, H01L21/48, H01L23/367, H01L27/12
CPC Code(s): H01L23/36
Abstract: a method of making an integrated circuit includes growing a semiconductor material layer over a substrate. the method includes doping the semiconductor material layer to define a first source structure comprising a first doped well having a first dopant type, and a drain structure comprising a second doped well having the first dopant type. the method includes etching the semiconductor material layer to define an opening. the method includes depositing a dielectric material into the opening to define a first deep trench isolation (dti), wherein the first dti extends through the first doped well. the method includes etching the first dti to define a contact opening. the method includes filling the contact opening with a thermally conductive material to define a first thermal contact, wherein the thermal contact is in direct contact with the substrate; and the first dti is between the thermal contact and the first doped well.
Inventor(s): Chao-Wei Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsuan-Ting Kuo of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L23/3675
Abstract: a method includes depositing a first metal layer on a package component, wherein the package component comprises a first device die, forming a dielectric layer on the package component, and plating a metal thermal interface material on the first metal layer. the dielectric layer includes portions on opposing sides of the metal thermal interface material. a heat sink is bonded on the metal thermal interface material. the heat sink includes a second metal layer physically joined to the metal thermal interface material.
Inventor(s): Chi-Yang Yu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Liang Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lin Ho of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Min Liang of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Lin Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/373, H01L23/00, H01L23/31, H01L23/495
CPC Code(s): H01L23/373
Abstract: a semiconductor package and a manufacturing method thereof are provided. the semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. the first and second semiconductor dies are different types of dies and are disposed side by side. the molding compound encloses the first and second semiconductor dies. the heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. the adhesive material is filled and contacted between the heat dissipation module and the molding compound. the semiconductor package has a central region and a peripheral region surrounding the central region. the first and second semiconductor dies are located within the central region. a sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.
Inventor(s): Wen-Shiang Liao of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Chieh-Yen Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/433, H01L21/48, H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L23/4334
Abstract: a semiconductor package includes a die, a first thermal pattern and an interposer. the first thermal pattern is disposed aside the die. the interposer is bonded to the die and includes a substrate, a wiring structure between the substrate and the die and a second thermal pattern. the second thermal pattern is thermally coupled to the first thermal pattern.
Inventor(s): Cheng-Lung Yang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hung Su of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Shien Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hon-Lin Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kun-Ming Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Je Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/48, H01L23/00, H01L23/528
CPC Code(s): H01L23/481
Abstract: a semiconductor device includes a first conductive layer, a second conductive layer, a third conductive layer, a first organic layer, a first inorganic layer and a first silicon-containing layer. the third conductive layer is disposed between and electrically isolated from the first conductive layer and the second conductive layer. the first organic layer continuously covers the first conductive layer and the third conductive layer. the first inorganic layer is disposed over the first organic layer. the first silicon-containing layer is inserted between the first organic layer and the first inorganic layer, wherein the second conductive layer is disposed on and disposed in the first organic layer, the first silicon-containing layer and the first inorganic layer, to electrically connect to the first conductive layer.
Inventor(s): Chih-Yu LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yu LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Syuan CIOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Wen CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/768
CPC Code(s): H01L23/481
Abstract: a device includes a plurality of tracks, wherein at least one of the plurality of tracks comprises a first power rail for a first voltage. the device further includes a first via in electrical contact with the power rail. the device further includes a first contact in electrical contact with the first via. the device further includes a first transistor in electrical contact with the first contact. the device further includes a second transistor in electrical isolation with the first transistor. the device further includes a second contact in electrical contact with the second transistor. the device further includes a second via in electrical contact with the second contact. the device further includes a second power rail in electrical contact with the second via, wherein the second power rail is configured to carry a second voltage.
Inventor(s): Chen-Shien Chen of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yen Lin of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wu-An Weng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsu-Hsien Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/02, H01L21/683, H01L23/00, H01L25/065
CPC Code(s): H01L23/49816
Abstract: a package includes a first integrated circuit die and a second integrated circuit die over and bonded to the first integrated circuit die. a first surface region of the second integrated circuit die is hydrophobic, and the first integrated circuit die and the second integrated circuit die are bonded together with dielectric-to-dielectric bonds and metal-to-metal bonds. the package further includes a first insulating material over the first integrated circuit and surrounding the second integrated circuit die. the first insulating material contacts the first surface region.
Inventor(s): Chun-Yi Sung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Hsuan Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hua-Wei Tseng of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Mill-Jer Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L23/00, H01L25/065
CPC Code(s): H01L23/49822
Abstract: a semiconductor die and methods of forming the same and a package structure are provided. the semiconductor die includes a semiconductor substrate, a plurality of conductive pads over the semiconductor substrate, a passivation layer over the semiconductor substrate and partially covering the plurality of conductive pads, an interconnecting line disposed on the passivation layer, and a plurality of connectors disposed on and electrically connected to the plurality of conductive pads. each of the plurality of connectors includes a stacked structure of a first conductive pillar and a second conductive pillar disposed directly on the first conductive pillar, wherein a span of the second conductive pillar is smaller than a span of the first conductive pillar, and an orthogonal projection of the second conductive pillar falls within an orthogonal projection of the first conductive pillar, and the interconnecting line is located beside and spaced apart from the plurality of connectors.
Inventor(s): Yan-Zuo Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Tsu Chung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yang-Chih Hsueh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chi Lin of Su-Lin (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L21/768, H01L23/16, H01L23/528
CPC Code(s): H01L23/49827
Abstract: a package includes a first die over and bonded to a first side of a second die, where the second die includes a first substrate, a first interconnect structure over the first substrate, a seal ring disposed within the first interconnect structure, first dummy through substrate vias (tsvs) extending through edge regions of the first substrate of the second die and in physical contact with the seal ring, and functional tsvs extending through a central region of the first substrate of the second die.
Inventor(s): Wen-Sheng CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ling CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L23/522, H01L23/66
CPC Code(s): H01L23/49838
Abstract: a semiconductor device and a semiconductor package structure are provided. the semiconductor device includes a radio frequency (rf) circuit, at least one ultra thick metal (utm) layer and at least one aluminum (ap) mesh layer. the utm layer is stacked on the rf circuit. the aluminum mesh layer is stacked on the utm layer, and the utm layer is connected to a power source or a ground through the aluminum mesh layer.
Inventor(s): Meng-Che Tu of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Sih-Hao Liao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/56, H01L21/768, H01L21/78, H01L23/31, H01L23/528
CPC Code(s): H01L23/5226
Abstract: a package including a device die and an encapsulant is provided. the device die includes a semiconductor substrate, an interconnect structure, a conductive via, and a dielectric layer. the interconnect structure is disposed over the semiconductor substrate. the conductive via is disposed over and electrically coupled to the interconnect structure. the dielectric layer is disposed over the interconnect structure and laterally encapsulating the conductive via, wherein the dielectric layer includes a sidewall and a bottom surface facing the interconnect structure, and the sidewall of the dielectric layer is tilted with respect to the bottom surface of the dielectric layer. the encapsulant laterally encapsulates the device die.
Inventor(s): Ching-Ho CHIN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hao Tsai of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chuei-Tang WANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L23/522, H01L27/06
CPC Code(s): H01L23/5283
Abstract: a three-dimensional integrated circuit stack comprises a first integrated circuit structure, a second integrated circuit structure bonding to the first integrated circuit structure, and a redistribution structure. the first integrated circuit structure comprises a first semiconductor device, a first buffer structure, a first interconnect structure, a first conductive via, and a first through via. the first semiconductor device is located between the first buffer structure and the first interconnect structure. the first conductive via is extending through the first buffer structure and in contact with the first semiconductor device. the first through via is extending from the first buffer structure to the first interconnect structure. the redistribution structure is disposed on the first buffer structure, electrically connected to the first semiconductor device through the first conductive via, and electrically connected to the first interconnect structure through the first through via.
Inventor(s): Kuo-Yen Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao Yi Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L23/498, H01L23/522
CPC Code(s): H01L23/5283
Abstract: a method includes forming an integrated circuit device on a semiconductor substrate, forming a through-via penetrating through the semiconductor substrate, and forming dummy patterns surrounding the through-via. the dummy patterns include a first plurality of dummy patterns having a first pattern density, and a second plurality of dummy patterns. the first plurality of dummy patterns are between the through-via and the second plurality of dummy patterns. the second plurality of dummy patterns have a second pattern density different from the first pattern density.
Inventor(s): Ming-Chou Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yi Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Yi Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/768, H01L29/06
CPC Code(s): H01L23/5286
Abstract: a method includes forming a conductive layer over a first dielectric layer; etching a recess in the conductive layer, wherein the recess exposes a top surface of the first dielectric layer; selectively depositing a capping layer on exposed sidewalls of the conductive layer within the recess; depositing a liner on the capping layer; forming a sacrificial material in the recess; and forming a second dielectric layer on the sacrificial material and on sidewalls of the recess; and after forming the second dielectric layer, performing a thermal process to remove the sacrificial material.
Inventor(s): Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Liang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ju Chen of Yunlin County (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/31, H01L23/538, H01L25/00, H01L25/065, H01L25/10
CPC Code(s): H01L23/562
Abstract: a semiconductor structure includes a circuit substrate, at least one semiconductor package, at least one semiconductor device, and a ring structure. the at least one semiconductor package is disposed on the circuit substrate, and the semiconductor package includes a plurality of integrated circuit structures. the at least one semiconductor device, disposed on the circuit substrate and aside the semiconductor package. the ring structure is disposed on the circuit board. the ring structure includes at least one opening pattern corresponding to the semiconductor device.
Inventor(s): Yang-Chih Hsueh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yan-Zuo Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Tsu Chung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chi Lin of Su-Lin City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/3115, H01L21/66, H01L23/528
CPC Code(s): H01L23/562
Abstract: a method includes depositing a dielectric layer on a package component having a first warpage, and performing an implantation process to implant the dielectric layer with a stress modulation dopant. after the implantation process, the package component has a second warpage smaller than the first warpage.
Inventor(s): Kuan-Yu Huang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Hui Huang of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Yun Hou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L21/78, H01L23/31, H01L23/48, H01L23/498, H01L25/00, H01L25/065
CPC Code(s): H01L23/562
Abstract: a semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. the first semiconductor die includes an active surface and a rear surface opposite to the active surface. the second semiconductor die is disposed on the active surface of the first semiconductor die. the insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. the warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.
Inventor(s): Meng-Sheng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yih Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, G11C17/16, G11C17/18, H10B20/25
CPC Code(s): H01L23/573
Abstract: a memory device includes an array comprising a plurality of one-time-programmable (otp) memory cells; a plurality of word lines (wls); a plurality of bit lines (bls); and a plurality of control gate (cg) lines. each of the otp memory cells comprises a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. the first fuse resistor and the second fuse resistor are coupled to a corresponding one of the bls, while the first transistor and the second transistor are gated by a first one and a second one of the cg lines, respectively.
Inventor(s): Min-Chien Hsiao of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Wen Shih of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chiang Ting of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ming Chen of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L25/065
CPC Code(s): H01L24/08
Abstract: a semiconductor device and methods of manufacture are discussed herein. a device includes a first semiconductor package including a first semiconductor die encapsulated in an insulating material, a first thermal expansion resistant layer over the first semiconductor die, a bonding layer over the first thermal expansion resistant layer and the insulating material, and a second semiconductor die directly bonded to the bonding layer.
Inventor(s): Jen-Hao Liu of Zhunan Township (TW) for taiwan semiconductor manufacturing company, ltd., Amram Eitan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yuan Chiu of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Chun Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hong Du of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/74
Abstract: a bonding apparatus with a bonding head having vacuum channels and switchable channels, and the method of forming the same are provided. the bonding apparatus may include a vacuum pump, a blower, a controller communicatively coupled to the vacuum pump and the blower, and a bonding head. the bonding head may include a main body, a first vacuum channel in the main body, wherein the first vacuum channel is connected to the vacuum pump, and a first switchable channel in the main body, wherein the first switchable channel is connected to the vacuum pump and the blower.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Wei Hong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/683, H01L23/00, H01L23/60, H01L25/00
CPC Code(s): H01L25/0657
Abstract: a package includes a first die, a second die, a first encapsulant, first through insulating vias (tiv), second encapsulant, and second tivs. the second die is stacked on the first die. the first encapsulant laterally encapsulates the first die. the first tivs are aside the first die. the first tivs penetrate through the first encapsulant and are electrically floating. the second encapsulant laterally encapsulates the second die. the second tivs are aside the second die. the second tivs penetrate through the second encapsulant and are electrically floating. the second tivs are substantially aligned with the first tivs.
Inventor(s): Chan-Hong Chern of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/16, G02B6/42, G02B6/43, H01L23/00, H01L23/31, H01L23/367, H10B80/00
CPC Code(s): H01L25/167
Abstract: various embodiments of the present disclosure are directed towards a semiconductor package structure including a first integrated circuit (ic) chip overlying a base structure. an electrical ic chip overlies the base structure and is disposed around the first ic chip. the electrical ic chip is electrically coupled to the first ic chip. a photonic ic chip overlies the base structure and is electrically coupled to the electrical ic chip. the photonic ic chip is configured to receive an input optical signal. the photonic ic chip is adjacent to the electrical ic chip.
Inventor(s): Chin-Ming Fu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03L7/081, H03L7/091, H04L7/00, H04L7/033
CPC Code(s): H03L7/0814
Abstract: the disclosure provides a voltage droop monitor (vdm) and a voltage droop monitoring method. the method includes: receiving a first reference clock signal and delaying the first reference clock signal as a first clock signal; delaying the first clock signal as a corresponding second clock signal; receiving the corresponding second clock signal from the corresponding first dcdl and generating a corresponding third clock signal via modifying a phase of the corresponding second clock signal; receiving the corresponding third clock signal; receiving a second reference clock signal; and collectively outputting a tdc code combination based on the second reference clock signal and the corresponding third clock signal, wherein the tdc code combination varies in response to a voltage variation of a to-be-monitored voltage.
Inventor(s): Hsin-Fu TSENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chiang TU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei WEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsing LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H05G2/00
CPC Code(s): H05G2/005
Abstract: a tin (sn) auto-filling device and system provided to provide new liquid sn to an inner sidewall surface of a rotation crucible. a laser is exposed to the liquid sn at the inner sidewall surface of the rotation crucible to generate extreme-ultraviolet-light (euv) that is utilized to process workpieces within a semiconductor manufacturing plant (fab). the auto-filling device automatically refills as the liquid sn at the inner sidewall surface of the rotation crucible is consumed due to the liquid sn at the inner sidewall surface of the rotation crucible being exposed to the laser.
Inventor(s): Hidehiro FUJIWARA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chang ZHAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsin NIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G03F1/70, G06F30/392, H01L23/522, H01L23/528
CPC Code(s): H10B10/12
Abstract: a method (of manufacturing a memory device) includes forming active regions extending in a first direction; over the active regions, doing as follows including, forming gate structures extending in a second direction perpendicular to the first direction, and forming contact-to-source/drain structures (md structures) which extend in the second direction and are interspersed among corresponding ones of the gate structures; forming via-to-gate/md (vgd) structures over corresponding ones of the gate structures and the md structures; in a first metallization layer over the vgd structures, forming first front-side segments extending in the first direction and including one or more front-side routing (frte) segments; under the active regions, forming buried segment-to-source/drain structures (bvd structures); and in a first buried metallization layer under the bvd structures, forming first back-side segments extending in the first direction and including one or more first back-side power grid (bpg) segments.
Inventor(s): Yangsyu LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lung LEE of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chi TIEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chiting CHENG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G11C11/412, G11C11/419, H01L23/522, H01L23/528, H01L27/02, H01L27/092
CPC Code(s): H10B10/18
Abstract: a static random access memory (sram) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an sram array. the sram periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. the second well region occupies a second distance in the row direction equal to the bitcell-pitch of the sram array. the second well region is disposed adjacent to the first well region in the row direction.
Inventor(s): I-Che Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huai-Ying Huang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Chieh Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Gang Chiu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Wen Cheng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/315
Abstract: a semiconductor device includes a substrate, an interconnect, a memory cell, and a plurality of first barrier structures. the interconnect is disposed over the substrate. the memory cell is disposed in the interconnect within a memory region of the substrate, where the memory cell includes a transistor and a capacitor. the transistor includes a gate, source/drain elements respectively standing at two opposite sides of the gate, and a channel disposed between the source/drain elements and overlapped with the gate. the capacitor is disposed over the transistor and electrically coupled to one of the source/drain elements. the plurality of first barrier structures line sidewalls and bottom surfaces of the source/drain elements, and each include a first barrier layer and a second barrier layer disposed between the source/drain elements and the first barrier layer, where a first absorption interface is disposed between the first barrier layer and the second barrier layer.
Inventor(s): Sai-Hooi Yeong of Cheras (MY) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chen Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, G11C5/06, G11C11/22, H01L21/28, H01L29/66, H10B43/10, H10B43/20, H10B51/10, H10B53/20
CPC Code(s): H10B51/20
Abstract: in an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.
Inventor(s): Chao-I Wu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B63/00, G11C7/18, G11C8/14, H01L23/522, H01L29/78, H10N70/00, H10N70/20
CPC Code(s): H10B63/34
Abstract: a memory device and method of forming the same are provided. the memory device includes a first memory cell disposed over a substrate. the first memory cell includes a transistor and a data storage structure coupled to the transistor. the transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. the drain electrode is separated from the source electrode a dielectric layer therebetween. the data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. the drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.
Inventor(s): Shu-Hui SU of Tucheng City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Li CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., YingKit Felix TSUI of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd., Tuo-Hsin CHIEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Jyun-Ying LIN of Wujie Township (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Min WU of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chi CHANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Chen HSU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10K10/40
CPC Code(s): H01L28/91
Abstract: some implementations described herein provide techniques and apparatuses for an integrated circuit device including a trench capacitor structure that has a merged region. a material filling the merged region is different than a material that is included in electrode layers of the trench capacitor structure. furthermore, the material filling the merged region includes a coefficient of thermal expansion and a modulus of elasticity that, in combination with the architecture of the trench capacitor structure, reduce thermally induced stresses and/or strains within the integrated circuit device relative to another integrated circuit device having a trench capacitor structure including a merged region and electrode layers of a same material.
Inventor(s): Hsin-Li Cheng of Hsin Chu (TW) for taiwan semiconductor manufacturing company, ltd., Jyun-Ying Lin of Wujie Township (TW) for taiwan semiconductor manufacturing company, ltd., Alexander Kalnitsky of San Francisco CA (US) for taiwan semiconductor manufacturing company, ltd., Shih-Fen Huang of Jhubei (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Hui Su of Tucheng City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Chen Hsu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tuo-Hsin Chien of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Felix Ying-Kit Tsui of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd., Shi-Min Wu of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chi Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L21/3213, H01L21/764, H01L23/00, H01L29/66, H01L29/94
CPC Code(s): H01L28/91
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. a stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. the stack of layers comprises a first segment in the first trench and a second segment in the second trench. a first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.
Inventor(s): Chih-Lun LU of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Ling CHEN of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Wei PAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234
CPC Code(s): H01L29/66795
Abstract: a method for forming a semiconductor device structure is described. in some embodiments, the method includes forming a gate electrode, forming a mask structure over the gate electrode, patterning the mask structure to form an opening, and performing a first etch process on the gate electrode by applying a first source power and a first bias power with a first pulsing scheme. the first bias power has a first frequency to control etching along a lateral direction. the method further includes performing a second etch process on the mask structure exposed within the opening by applying a second source power and a second bias power with a second pulsing scheme, and the second bias power has a second frequency to control etching along a vertical direction. the first and second frequencies are substantially different.
Inventor(s): Chan-Yu HUNG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Cheng Ho of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Fei-Yun Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chang Jong of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Puo-Yu Chiang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tun-Yi Ho of Keelung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/40, H01L29/78
CPC Code(s): H01L29/66689
Abstract: the present disclosure describes a structure with a conductive plate and a method for forming the structure. the structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. the structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. the structure further includes a second insulating layer in contact with the conductive plate.
Inventor(s): Cheng-Wei CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hung CHU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsu-Kai CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li WANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Kan HU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shuen-Shin LIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kao-Feng LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung Pin LU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ying LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chuan-Hui SHEN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/285, H01L21/768, H01L29/40, H01L29/417
CPC Code(s): H01L29/785
Abstract: a titanium precursor is used to selectively form a titanium silicide (tisi) layer in a semiconductor device. a plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. the diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. the titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. the selective titanium silicide layer formation results in the formation of a titanium silicon nitride (tisin) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.
Inventor(s): Chun-Chieh Wang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Wei Yeh of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yueh-Ching Pai of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Jen Yang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/768, H01L23/532, H01L27/088, H01L29/16, H01L29/49, H01L29/66
CPC Code(s): H01L29/785
Abstract: provided are a gate structure and a method of forming the same. the gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. the metal layer is disposed over the gate dielectric layer. the cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. in addition, a semiconductor device including the gate structure is provided.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Heng TSAI of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/285, H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/41733
Abstract: a method for forming a semiconductor device structure is provided. the method includes providing a substrate and a nanostructure stack. the method includes forming a first gate stack and a second gate stack wrapped around the nanostructure stack. the method includes forming a first source/drain structure in the nanostructure stack and between the first gate stack and the second gate stack. the method includes removing the second gate stack, the nanostructure stack and the fin under the second gate stack to form a trench passing through the nanostructure stack and the fin. the method includes forming a dielectric isolation structure in the trench. the method includes removing the first gate stack and the first nanostructure. the method includes forming a third gate stack wrapped around the second nanostructure. the method includes forming a first contact structure over the first source/drain structure.
Inventor(s): Bo-Jiun Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chao Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/76, H01L29/24, H01L29/40, H01L29/45, H01L29/66
CPC Code(s): H01L29/7606
Abstract: a semiconductor device including a substrate, a semiconductor layer, a gate, a dielectric structure, and a source/drain structure is provided. the semiconductor layer is disposed on the substrate, and is made of a first low dimensional material. the gate is disposed on the substrate and overlaps the semiconductor layer. the dielectric structure is disposed on the semiconductor layer and includes a trench structure reaching a portion of the semiconductor layer. the source/drain structure includes a barrier layer made of a second low dimensional material continuously extending along the trench structure and a metal fill filling a volume surrounded by the barrier layer.
Inventor(s): Chun-Chieh Lu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Ching Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Ang Chao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lain-Jong Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/76, H01L21/02, H01L29/24, H01L29/417, H01L29/66, H01L29/786
CPC Code(s): H01L29/7606
Abstract: a transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. the fin structures are disposed on a material layer. the fin structures are arranged in parallel and extending in a first direction. the source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. the channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. the gate structure is disposed on the channel layers and across the fin structures. the gate structure extends in a second direction perpendicular to the first direction. the materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.
Inventor(s): Chun Hsiung TSAI of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsin KO of Fongshan City (TW) for taiwan semiconductor manufacturing company, ltd., Clement Hsing Jen WANN of Carmel NY (US) for taiwan semiconductor manufacturing company, ltd., Ya-Yun CHENG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/265, H01L21/306, H01L21/3065, H01L29/66
CPC Code(s): H01L29/0653
Abstract: a semiconductor device including a fet includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Weng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Pi Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin Chao of Hillsboro OR (US) for taiwan semiconductor manufacturing company, ltd., Chung-Liang Cheng of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kun-Yu Lee of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Tzer-Min Shen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Tien Tung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-I Wu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/324, H01L21/8234, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/0665
Abstract: a method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. the first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. the method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.
Inventor(s): Che-Lun Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Ting Pan of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: provided are devices and methods for forming devices. an exemplary method includes etching a cavity in a vertical direction into a fin structure including at least one semiconductor nanosheet overlying a sacrificial layer, wherein the cavity is formed with a sidewall; recessing the sacrificial layer by a lateral distance to a recessed surface; forming an inner spacer laterally adjacent to the recessed surface of the sacrificial layer, wherein the inner spacer has a lateral width greater than the lateral distance; and growing epitaxial material in the cavity to form a source/drain region laterally adjacent to the inner spacer.
Inventor(s): Yu-Shiang HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ting CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L27/088, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0676
Abstract: semiconductor structures and methods for forming the same are provided. the semiconductor structure includes a plurality of nanostructures formed over a substrate, and an inner spacer layer between two adjacent nanostructures. the semiconductor structure includes a source/drain (s/d) structure formed adjacent to the inner spacer layer, and a barrier layer adjacent to the inner spacer layer. the barrier layer extends from the first position to the second position, and the first position is between the inner spacer layer and the nanostructure, and the second position is between the nanostructures and the s/d structure.
Inventor(s): Yan-Ming Tsai of Toufen Township (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsing Tsai of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hsuan Lin of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Hsu Chen of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yip Loh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/02, H01L21/8238, H01L27/092, H01L29/66, H01L29/78
CPC Code(s): H01L29/0847
Abstract: a device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including nisi, a second silicide region on the first silicide region, the second silicide region including tisi, and a conductive material on the second silicide region.
Inventor(s): Fu-Hsiang SU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Chun WU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Je-Wei HSU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hong-Chih CHEN of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao KUO of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hsun CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L29/66545
Abstract: a method for forming a semiconductor device structure includes forming nanostructures over a substrate. the method also includes forming a gate structure wrapped around the nanostructures. the method also includes forming source/drain epitaxial structures over opposite sides of the nanostructures. the method also includes forming a first interlayer dielectric structure over the source/drain epitaxial structures. the method also includes removing the first interlayer dielectric structure. the method also includes forming a recess in the source/drain epitaxial structures. the method also includes forming a silicide structure in the recess. the method also includes forming a second interlayer dielectric structure over the silicide structure.
Inventor(s): Shu-Uei Jang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shu Wu of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Wei Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L29/66545
Abstract: a semiconductor fabrication method includes: forming, on a substrate, an epitaxial stack comprising at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a fin in the epitaxial stack; forming a sacrificial gate stack on channel regions of the fin; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; performing pre-treatment operations to remove impurities from the at least one sacrificial epitaxial layer; recessing the at least one sacrificial epitaxial layer to form a cavity; forming inner spacer material in the cavity; forming source/drain features; removing the sacrificial gate stack and the at least one sacrificial epitaxial layer in the fins; and forming a metal gate to replace the sacrificial gate stack and the at least one sacrificial epitaxial layer, wherein the inner spacers have sufficient thickness to resist epi damage.
Inventor(s): Tsung-Lin Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chang Wen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Tai Chan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih Chieh Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Da-Wen Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/08, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L29/66545
Abstract: semiconductor structures and methods of fabrication are provided. a method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. the channel extension features include undoped silicon.
Inventor(s): Jia-Chuan YOU of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chu-Yuan HSU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/08, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L29/66545
Abstract: gate isolation processes (e.g., gate-to-source/drain contact isolation) are described herein. an exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (cgi) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the cgi opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the cgi opening. a dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. a dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. a dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.
Inventor(s): Kun-Yu LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ling KO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., I-Chen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Teng LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Jen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L29/66, H01L29/78
CPC Code(s): H01L21/823431
Abstract: in a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.
Inventor(s): Hung-Yao Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Chu Liang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsueh-Chang Sung of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Ren Jeng of Chu-Bei City (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/8238, H01L27/088, H01L27/092
CPC Code(s): H01L21/823431
Abstract: in an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.
Inventor(s): Wang-Chun Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/02, H01L21/306, H01L21/308, H01L21/8234, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L27/0886
Abstract: the present disclosure describes a structure including a fin field effect transistor (finfet) and a nano-sheet transistor on a substrate and a method of forming the structure. the method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. the method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess.
Inventor(s): Yu-Lung TUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Xiaodong WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L27/092
Abstract: a semiconductor structure includes a first active region, a second active region and a dielectric wall. the second active region is disposed adjacent to the first active region, wherein there is a space between the first active region and the second active region. the dielectric wall is formed within the space between the first active region and the second active region. the dielectric wall has a first wall width and a second wall width different from the first wall width.
Inventor(s): Shun-Jang LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chun LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Hui WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hsun CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/28, H01L21/768, H01L21/8234, H01L21/8238, H01L27/088, H01L29/49, H01L29/78
CPC Code(s): H01L27/0922
Abstract: a semiconductor device includes first-type-channel field effect transistors (fets) including a first first-type-channel fet including a first gate structure and a second first-type-channel fet including a second gate structure. the first first-type-channel fet has a smaller threshold voltage than the second first-type-channel fet. the first gate structure includes a first work function adjustment material (wfm) layer and the second gate structure includes a second wfm layer. at least one of thickness and material of the first and second wfm layers is different from each other.
Inventor(s): Wei-Hsuan Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Lun Chung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Anhao Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Wei Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Liang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Shang Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238
CPC Code(s): H01L27/0928
Abstract: a semiconductor device includes a first well region laterally separated from a second well region in a substrate, a shallow trench isolation (sti) structure laterally between the first well region and the second well region in the substrate, a first implant region of a dopant type opposite to a dopant type of the first well region in the substrate, disposed vertically lower than the sti structure and laterally between the first well region and a lateral center of the sti structure, and a second implant region of a dopant type opposite to a dopant type of the second well region in the substrate, disposed vertically lower than the sti structure and laterally between the second well region and the lateral center of the sti structure.
Inventor(s): Jhon-Jhy LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/118, H01L27/092, H01L29/10, H01L29/16, H01L29/165, H01L29/167, H01L29/24, H01L29/267, H01L29/78, H10B10/00
CPC Code(s): H01L27/11807
Abstract: an ic is provided. the ic includes a first p-type finfet and a second p-type finfet. the first p-type finfet includes a discontinuous sige fin. the second p-type finfet includes a continuous si-base fin. the ic further includes first source/drain regions on the discontinuous sige fin and second source/drain regions on the continuous si-base fin. a first depth of the first source/drain regions is greater than a second depth of the second source/drain regions.
Inventor(s): Hung-Wen Hsu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Chang Chang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jiech-Fun Lu of Madou Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/12, C30B25/04, C30B33/10, H01L21/02, H01L21/308, H01L21/762
CPC Code(s): H01L27/1207
Abstract: a method of manufacturing a hybrid soi substrate includes epitaxially growing a sacrificial layer and then an upper semiconductor layer over a semiconductor body. the sacrificial layer may be a heavily doped semiconductor. the heavy doping allows the sacrificial layer to be selectively etched while leaving the upper semiconductor layer largely intact. an soi region of the semiconductor body is masked while the upper semiconductor layer and the sacrificial layer are etched from a peripheral region of the semiconductor body. a bulk semiconductor is then grown to replace the etched layers on the peripheral region. holes are formed through the upper semiconductor layer in the soi region and the sacrificial layer is etched from beneath the upper semiconductor. the holes may then be filled with dielectric leaving a cavity beneath the upper semiconductor layer in the soi region.
Inventor(s): Kam-Tou SIO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L21/02, H01L21/8238, H01L23/528, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L27/0207
Abstract: an integrated circuit includes a driver cell and at least one transmission cell. the driver cell includes a first active area and a second active area, and a first conductive line coupled to the first active area and the second active area on a back side of the integrated circuit. the at least one transmission cell having a second cell height includes a third active area and a fourth active area, a second conductive line coupled to the third active area and the fourth active area on the back side of the integrated circuit, and a conductor coupled to the third active area and the fourth active area. the integrated circuit further includes a third conductive line coupled between the first conductive line and the second conductive line on the back side to transmit a signal between the driver cell and the at least one transmission cell.
Inventor(s): Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Fan CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Fu HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-An LAI of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chan-Hong CHERN of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd., Cheng-Hsiang HSIEH of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H02H9/04
CPC Code(s): H01L27/0248
Abstract: this disclosure is directed to a circuit that includes a substrate, a target device on the substrate, and an electrostatic discharge (esd) device electrically coupled to the target device. the esd device includes an esd detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the esd detection circuit and configured to trigger in response to an esd event on the first or second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and configured to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and configured to discharge a remaining current passing through the rectifier circuit.
Inventor(s): Te-Chin Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Jier Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02
CPC Code(s): H01L27/0266
Abstract: the present disclosure provides embodiments of semiconductor structures. a semiconductor structure according to the present disclosure includes a first transistor and a second transistor. the first transistor includes a first source feature, a first drain feature, and a first gate structure. the second transistor includes a second source feature, a second drain feature, and a second gate structure. the first source feature is electrically coupled to the second source feature and the second drain feature is electrically coupled to the first gate structure.
Inventor(s): Ya-Qi MA of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Lei PAN of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Zhen TANG of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L27/06
CPC Code(s): H01L27/0266
Abstract: an integrated circuit includes first to second transistors and a resistive device. the first transistor is coupled between a pad and a first voltage terminal that provides a first supply voltage. the second transistor is coupled in parallel with the first transistor. a breakdown voltage of the first transistor is different from a trigger voltage of the second transistor. the resistive device is coupled between the pad and a second voltage terminal that provides a second supply voltage higher than the first supply voltage, and operates with the second supply voltage in an electrostatic discharge (esd) event when the first and second transistors discharge a esd current between the pad and the first voltage terminal.
Inventor(s): Hung-Te Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L21/762, H01L27/12
CPC Code(s): H01L27/0292
Abstract: semiconductor structure and methods for fabricating the same are provided. an example semiconductor structure includes a bulk substrate having a top surface and a silicon-on-insulator (soi) substrate merged in the bulk substrate. the soi substrate further includes a heavily doped layer, an insulating layer disposed on and surrounded by the heavily doped layer, and an active substrate disposed on and surrounded by the insulating layer. the semiconductor structure further includes one or more semiconductor devices disposed in the active substrate, a peripheral heavily doped region connected to the heavily doped layer, and a discharging metal structure electrically interconnecting the semiconductor devices to the peripheral heavily doped region.
20250063833. IMAGE SENSOR_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Ming-Hsien YANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Kun-Hui LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hao CHOU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng LEE of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14643
Abstract: a semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, wherein certain of the metal isolation features extend through the substrate to provide for full isolation between adjacent photodetectors and certain of the metal isolation features extend partially through the semiconductor layer to provide partially isolation between adjacent photodetectors.
Inventor(s): Chieh-En CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hsien LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shyh-Fann TING of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chih WENG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Chi HUNG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1464
Abstract: a polysilicon well is formed at a cross-road portion between a plurality of pixel sensors in a pixel sensor array. moreover, the underlying oxide layer between the polysilicon well and a semiconductor layer of the pixel sensor array may be thinner than other areas of the oxide layer. the polysilicon well and the thinner oxide layer may reduce the likelihood of and/or the magnitude of lateral etching that occurs during etching of the semiconductor layer to form recesses in which a bdti structure of the pixel sensor array is formed. moreover, the bottom of the bdti structure being surrounded by the polysilicon well enables a voltage bias to be applied to the bdti structure through the polysilicon well to passivate damage that might have occurred to the semiconductor layer around the bottom of the bdti structure.
Inventor(s): Feng-Chien HSIEH of Pingtung City (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Wei CHENG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng LEE of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Ming WU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H04N5/33, H04N23/10, H04N25/76
CPC Code(s): H01L27/14607
Abstract: a pixel array includes octagon-shaped pixel sensors and a combination of visible light pixel sensors (e.g., red, green, and blue pixel sensors) and near infrared (nir) pixel sensors. the color information obtained by the visible light pixel sensors and the luminance obtained by the nir pixel sensors may be combined to increase the low-light performance of the pixel array, and to allow for low-light color images in low-light applications. the octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. the capability to accommodate different sizes of visible light pixel sensors and nir pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.
Inventor(s): Shih-Yu LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, G01S7/481
CPC Code(s): H01L27/1461
Abstract: a semiconductor device with an image sensor and a method of fabricating the same are disclosed. the semiconductor device includes a substrate, a pixel region with a pixel structure, an isolation region with an isolation structure disposed adjacent to the pixel region, and a contact pad region with a pad structure disposed adjacent to the isolation region. the pixel structure includes an epitaxial structure, which includes an embedded portion with a stepped structure disposed in the substrate and a protruding portion extending above a top surface of the substrate. the pixel structure further includes a capping layer disposed on the protruding portion.
Inventor(s): Chun-Yen Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hau-Yan Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., YingKit Felix Tsui of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L31/18, H01L31/028, H01L31/0392, H01L31/107
CPC Code(s): H01L31/1808
Abstract: a photonic device includes a substrate, a p-type doped component disposed over the substrate, an n-type doped component disposed over the substrate, an optical absorption layer disposed over the substrate, and a charging layer disposed over the substrate. the optical absorption layer is disposed between the p-type doped component and the n-type doped component. the optical absorption layer and the substrate have different material compositions. a charging layer is disposed between the p-type doped component and the n-type doped component. the charging layer has a first side surface that is substantially linear. the first side surface is in direct contact with the optical absorption layer.
Inventor(s): Tzu-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hung SHIH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chi TU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Ting CHU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Harry-Haklay CHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/20, H10N70/00
CPC Code(s): H10N70/25
Abstract: a semiconductor structure includes a ferroelectric layer and a semiconductor layer. thee ferroelectric layer has a first surface and a second surface opposite to the first surface. the semiconductor layer is formed on one of the first surface and the second surface.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on February 20th, 2025
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- A61B17/22
- A61B17/00
- A61B17/3203
- A61B90/10
- A61M5/00
- A61M25/00
- A61M25/01
- CPC A61B17/22
- Taiwan semiconductor manufacturing company, ltd.
- A61N1/372
- A61N1/05
- A61N1/36
- CPC A61N1/37247
- B06B1/02
- B81B3/00
- B81B7/02
- CPC B06B1/0292
- G01R31/26
- G01R31/27
- H03K3/017
- H03K17/687
- CPC G01R31/2621
- G02B6/293
- G02B6/12
- CPC G02B6/29338
- G02B6/34
- G02B6/124
- G02B6/13
- H01L21/02
- CPC G02B6/34
- G02B6/42
- CPC G02B6/4214
- G02F1/225
- G02F1/21
- CPC G02F1/2255
- G03F1/42
- CPC G03F1/42
- G03F1/62
- G03F1/64
- CPC G03F1/62
- G03F7/42
- H01L21/48
- H01L21/56
- H01L21/683
- H01L23/00
- H01L23/31
- H01L23/538
- CPC G03F7/426
- G06F1/08
- G11C16/24
- G11C16/28
- CPC G06F1/08
- G06F11/10
- G06F12/14
- CPC G06F11/1016
- G06F30/392
- H01L21/768
- H01L27/02
- H01L27/118
- CPC G06F30/392
- G11C7/12
- G11C7/10
- G11C7/20
- CPC G11C7/12
- G11C11/406
- G11C11/408
- G11C11/4099
- CPC G11C11/40615
- G11C11/419
- G11C11/418
- CPC G11C11/419
- H01L21/266
- H01L21/308
- H01L21/761
- H01L29/66
- CPC H01L21/02496
- H01L21/762
- CPC H01L21/266
- H01L23/48
- H01L23/498
- H01L25/065
- CPC H01L21/56
- C08J3/09
- C08K3/04
- C08L1/02
- H01L23/29
- H01L25/10
- CPC H01L21/565
- H01L21/67
- F27B17/00
- CPC H01L21/67017
- H01L21/673
- H01L21/687
- CPC H01L21/67051
- H01L21/677
- CPC H01L21/67086
- B60L1/00
- B60L50/60
- G05B19/418
- CPC H01L21/67724
- H01L21/304
- H01L21/66
- CPC H01L21/6836
- H01L29/06
- H01L29/417
- H01L29/423
- H01L29/775
- CPC H01L21/76232
- H01L21/265
- H01L21/268
- CPC H01L21/76254
- H01L21/8238
- H01L27/088
- CPC H01L21/76898
- C23C14/06
- C23C14/18
- C23C14/35
- C23C14/54
- H01J37/34
- H01L21/285
- CPC H01L22/26
- H01L23/58
- CPC H01L22/34
- CPC H01L23/3114
- H01L23/36
- H01L23/367
- H01L27/12
- CPC H01L23/36
- CPC H01L23/3675
- H01L23/373
- H01L23/495
- CPC H01L23/373
- H01L23/433
- CPC H01L23/4334
- H01L23/528
- CPC H01L23/481
- CPC H01L23/49816
- CPC H01L23/49822
- H01L23/16
- CPC H01L23/49827
- H01L23/522
- H01L23/66
- CPC H01L23/49838
- H01L21/78
- CPC H01L23/5226
- H01L27/06
- CPC H01L23/5283
- CPC H01L23/5286
- H01L25/00
- CPC H01L23/562
- H01L21/3115
- G11C17/16
- G11C17/18
- H10B20/25
- CPC H01L23/573
- CPC H01L24/08
- CPC H01L24/74
- H01L23/60
- CPC H01L25/0657
- H01L25/16
- G02B6/43
- H10B80/00
- CPC H01L25/167
- H03L7/081
- H03L7/091
- H04L7/00
- H04L7/033
- CPC H03L7/0814
- H05G2/00
- CPC H05G2/005
- H10B10/00
- G03F1/70
- CPC H10B10/12
- G11C11/412
- H01L27/092
- CPC H10B10/18
- H10B12/00
- CPC H10B12/315
- H10B51/20
- G11C5/06
- G11C11/22
- H01L21/28
- H10B43/10
- H10B43/20
- H10B51/10
- H10B53/20
- CPC H10B51/20
- H10B63/00
- G11C7/18
- G11C8/14
- H01L29/78
- H10N70/00
- H10N70/20
- CPC H10B63/34
- H10K10/40
- CPC H01L28/91
- H01L21/3213
- H01L21/764
- H01L29/94
- H01L21/8234
- CPC H01L29/66795
- H01L29/40
- CPC H01L29/66689
- CPC H01L29/785
- H01L23/532
- H01L29/16
- H01L29/49
- CPC H01L29/41733
- H01L29/76
- H01L29/24
- H01L29/45
- CPC H01L29/7606
- H01L29/786
- H01L21/306
- H01L21/3065
- CPC H01L29/0653
- H01L21/324
- CPC H01L29/0665
- H01L29/08
- CPC H01L29/0673
- CPC H01L29/0676
- CPC H01L29/0847
- CPC H01L29/66545
- CPC H01L21/823431
- CPC H01L27/0886
- CPC H01L27/092
- CPC H01L27/0922
- CPC H01L27/0928
- H01L29/10
- H01L29/165
- H01L29/167
- H01L29/267
- CPC H01L27/11807
- C30B25/04
- C30B33/10
- CPC H01L27/1207
- CPC H01L27/0207
- H02H9/04
- CPC H01L27/0248
- CPC H01L27/0266
- CPC H01L27/0292
- H01L27/146
- CPC H01L27/14643
- CPC H01L27/1464
- H04N5/33
- H04N23/10
- H04N25/76
- CPC H01L27/14607
- G01S7/481
- CPC H01L27/1461
- H01L31/18
- H01L31/028
- H01L31/0392
- H01L31/107
- CPC H01L31/1808
- CPC H10N70/25
