TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on August 29th, 2024
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. on August 29th, 2024
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 53 patent applications
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. has applied for patents in the areas of H01L29/66 (22), H01L29/06 (16), H01L29/78 (14), H01L29/423 (12), H01L29/786 (11) H01L29/41733 (4), H01L29/66545 (4), H10B10/12 (2), H01L29/785 (2), H01L27/14634 (2)
With keywords such as: layer, structure, gate, semiconductor, dielectric, region, device, substrate, source, and conductive in patent application abstracts.
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s): Tzu-Yang LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/038, G03F7/039, H01L21/027, H01L21/311, H01L21/3213
CPC Code(s): G03F7/038
Abstract: a method of manufacturing a semiconductor device includes forming a photoresist layer on a target layer. the photoresist layer includes a polymer including first repeating units and second repeating units, the first repeating units are
Inventor(s): Tzu-Yang LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/038, G03F7/039, H01L21/027, H01L21/311, H01L21/3213
CPC Code(s): G03F7/038
Abstract:
Inventor(s): Tzu-Yang LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/038, G03F7/039, H01L21/027, H01L21/311, H01L21/3213
CPC Code(s): G03F7/038
Abstract: and the second repeating units are selected from the group consisting of
Inventor(s): Tzu-Yang LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/038, G03F7/039, H01L21/027, H01L21/311, H01L21/3213
CPC Code(s): G03F7/038
Abstract:
Inventor(s): Tzu-Yang LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/038, G03F7/039, H01L21/027, H01L21/311, H01L21/3213
CPC Code(s): G03F7/038
Abstract: xand xare respectively an arylene group. x, x, and xare respectively a trivalent functional group derived from an arene by removal of three hydrogen atoms. x, x, x, x, —x—oh, —x—oh, —x—oh, and —x—oh are respectively an acid labile group. r, r, r, r, and rare respectively hydrogen or a methyl group. the photoresist layer is selectively exposed to a radiation. the photoresist layer is developed to form a patterned photoresist layer. the target layer is etched by using the patterned photoresist layer as an etching mask.
Inventor(s): Christine Y Ouyang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/42, G03F7/00, G03F7/004, G03F7/027, H01L21/027, H01L21/308, H01L21/311, H01L21/56, H01L23/00, H01L23/31, H01L23/528
CPC Code(s): G03F7/427
Abstract: a method for removing a resist layer is provided. a resist layer is formed with a material comprising a metal oxide core with organic ligands. a chlorine-containing compound or a methyl group-containing compound is globally applied onto the resist layer to allow the chlorine-containing compound or the methyl group-containing compound to perform a ligand exchange process with the resist layer so as to remove the resist layer through sublimation.
Inventor(s): Atul Katoch of Kanata (CA) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/22, G11C11/4076, G11C11/408, G11C11/418, H03K19/20
CPC Code(s): G11C7/222
Abstract: memory clock drivers, memories, and methods of operating memory clock drivers are provided. a memory device contains two memory clock drivers disposed opposite each other across an array of rows of memory cells. the memory clock drivers contain decoders, which decode an address corresponding to one or more rows of memory cells. the decoders are configured to decode the address to provide a plurality of word line signals to the corresponding rows of memory cells. the memory device also includes a row select circuit, which receives a row select address and activates a corresponding row of memory cells. the memory device includes control circuitry to control the arrays of memory cells at a local and a global level, as well as i/o modules to send signals to different parts of the memory device and integrate the memory device into external devices.
Inventor(s): Xiu-Li YANG of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., He-Zhou WAN of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Lu-Ping KONG of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd., Wei-Yang JIANG of Jiangshan City (CN) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419
CPC Code(s): G11C11/419
Abstract: a device is provided. the device includes multiple transistors, a first sense circuit, and a precharge circuit. the transistors are coupled to a tracking bit line and configured to generate a first tracking signal. the first sense circuit is configured to generate a first sense tracking signal in response to the first tracking signal. the precharge circuit is configured to generate, in response to a rising edge and a falling edge of the first sense tracking signal, a precharge signal for precharging data lines.
Inventor(s): Yu-Der CHIH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Fan CHANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., May-Be CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Xin XUE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Je-Syu LIU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C13/00, G06F7/544, G11C7/06, G11C7/10, G11C7/14
CPC Code(s): G11C13/004
Abstract: a system is provided. the system includes a multiply-and-accumulate circuit and a local generator. the multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. the local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. the local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.
Inventor(s): Gu-Huan LI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Cheng CHANG of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Perng-Fei YUH of Walnut Creek CA (US) for taiwan semiconductor manufacturing company, ltd., Chia-En HUANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Ying LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yih WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C17/18, G11C17/16, H10B20/20
CPC Code(s): G11C17/18
Abstract: a memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. the first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. the second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. when the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.
Inventor(s): Anderson Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Ren Cheng of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yuan Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Fen Huang of Jhubei (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chuan Teng of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yi Heng Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., You-Ru Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Wen Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Chun Huang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Fan Hu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hui Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yan-Jie Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01G4/012, H01G4/12, H01G4/228, H01L21/311, H01L21/3213, H10N30/30, H10N30/50, H10N30/87
CPC Code(s): H01G4/012
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure and a second conductive structure. a dielectric structure is arranged between the first conductive structure and the second conductive structure. the dielectric structure comprises an upper region over a lower region. the lower region comprises a first lateral surface and a second lateral surface on opposing sides of the upper region. a passivation layer overlies the second conductive structure and the dielectric structure. the passivation layer comprises a lateral segment contacting the first lateral surface. a height of the lateral segment is greater than a height of the upper region. a top surface of the lateral segment is below a top surface of the passivation layer.
Inventor(s): Ya-Chin KING of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chrong-Jung LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Burn-Jeng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Ping WANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Hua WANG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Lin CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/304, G03F7/00, H01J37/30, H01L27/144, H01L31/02, H01L31/113, H01L31/18
CPC Code(s): H01J37/304
Abstract: a semiconductor structure includes a substrate, a semiconductor detector, a peripheral circuit, and a multilayer interconnection structure. the substrate has a sensing region and a peripheral region. the semiconductor detector is on the sensing region of the substrate. the semiconductor detector includes a first detector unit, a second detector unit, and a third detector unit. each of the first, second, third detector units includes a first transistor and a second transistor connected in series. a gate of the second transistor is a floating gate. the peripheral circuit is on the peripheral region of the substrate and is coupled to the semiconductor detector. the multilayer interconnection structure is over the substrate. a first number of metallization layers of the multilayer interconnection structure directly above the peripheral circuit is greater than a second number of metallization layers of the multilayer interconnection structure directly above the semiconductor detector.
Inventor(s): Otto CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Ying WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chih CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/32, H01J37/244
CPC Code(s): H01J37/32935
Abstract: an ion collector includes a plurality of segments and a plurality of integrators. the plurality of segments are physically separated from one another and spaced around a substrate support. each of the segments includes a conductive element that is designed to conduct a current based on ions received from a plasma. each of the plurality of integrators is coupled to a corresponding conductive element. each of the plurality of integrators is designed to determine an ion distribution for a corresponding conductive element based, at least in part, on the current conducted at the corresponding conductive element. an example benefit of this embodiment includes the ability to determine how uniform the ion distribution is across a wafer being processed by the plasma.
Inventor(s): Shu-Uei Jang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Yi Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ryan Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., An Chyi Wei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Yuan Ku of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L21/02, H01L21/3213, H01L21/762, H01L21/8234, H01L29/66
CPC Code(s): H01L21/28123
Abstract: a method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. a second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. after the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. the trench is filled with a dielectric region, which contacts the sidewall of the gate stack.
Inventor(s): Pei Ying Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chieh Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsueh-Ju Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Da Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Hao Hou of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/324, H01L21/8238, H01L25/07, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L21/324
Abstract: dipole engineering techniques are disclosed that incorporate dipole dopant and/or nitrogen into gate dielectrics (e.g., high-k dielectric layers thereof) to realize multi-threshold voltage transistor tuning of transistors. the dipole engineering techniques include (1) forming a dipole dopant source layer over gate dielectrics of some transistors, but not other transistors, (2) forming a mask over gate dielectrics of some transistors, but not other transistors, (3) performing a nitrogen-containing thermal drive-in process, and (4) removing the dipole dopant source layer and the mask after the nitrogen-containing thermal drive-in process. the nitrogen-containing thermal drive-in process diffuses nitrogen and dipole dopant (n-dipole dopant and/or p-dipole dopant) into unmasked gate dielectrics having the dipole dopant source layer formed thereon, nitrogen into unmasked gate dielectrics, and dipole dopant into masked gate dielectrics having the dipole dopant source layer formed thereon. masked gate dielectrics without the dipole dopant source layer formed thereon remain undoped.
Inventor(s): Chia-Chung Chen of Keelung (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Feng Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Victor Chiang Liang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hao Chu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu Yang of Taichung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/324, H01L29/08, H01L29/165, H01L29/45, H01L29/66, H01L29/78
CPC Code(s): H01L21/76814
Abstract: a semiconductor device includes a first gate stack structure over a substrate, a source/drain epitaxial layer, a lightly doped region, and a silicide region. the source/drain epitaxial layer is disposed in the substrate and adjacent to the first gate stack structure. the lightly doped region is located in the substrate to be electrically connected to the source/drain epitaxial layer. the lightly doped region includes a first portion protrudes from a sidewall of the source/drain epitaxial layer. the silicide region is in contact with a top surface and sidewalls of a top portion of the source/drain epitaxial layer and a top surface of the first portion of the lightly doped region. the top portion of the source/drain epitaxial layer is higher than the top surface of the first portion of the lightly doped region.
Inventor(s): Chin-Lung Chung of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Yi Yang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L21/76834
Abstract: a semiconductor structure includes a first dielectric layer, a first metallic feature over the first dielectric layer, an air gap over the first dielectric layer and adjacent to the first metallic feature, a second dielectric layer disposed above the air gap and on a sidewall of the first metallic feature, and a third dielectric layer disposed above the air gap and on a sidewall of the second dielectric layer. a lower portion of the first metallic feature is exposed in the air gap. the third and the second dielectric layers are substantially co-planar.
Inventor(s): Pang-Sheng Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Hsun Wang of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Yi Chao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Yun Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Chieh Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Wei Hsu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L21/7684
Abstract: a method includes forming a first conductive feature over a semiconductor substrate, forming an ild layer over the first conductive feature, patterning the ild layer to form a trench, and forming a conductive layer over the patterned ild layer to fill the trench. the method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ild layer, polishing the exposed top surface of the ild layer, such that a top portion of the via contact protrudes from the exposed top surface of the ild layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.
Inventor(s): Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsiung Lu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chin Wei Kang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Han Chuang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Lung-Kai Mao of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Sheng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/00
CPC Code(s): H01L21/76885
Abstract: a method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. a protection layer is plated on the second conductive feature. the method further includes removing the patterned photo resist, and etching the metal seed layer.
Inventor(s): Hsin-Yi LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Yu WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung HUNG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-On CHUI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L29/66, H01L29/78
CPC Code(s): H01L21/823431
Abstract: a method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.
Inventor(s): Yao-Teng CHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Te-Yang LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Lun LIN of Keelung City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Da LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On CHUI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/3115, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L21/823857
Abstract: dipole engineering techniques for stacked device structures are disclosed herein. according to various aspects of the present disclosure, an exemplary dipole engineering technique includes (1) forming at least two patterned dipole dopant source layers having different patterns and covering gate dielectric layers of some transistors, but not other transistors, (2) performing a thermal drive-in process (e.g., a dipole drive-in anneal), and (3) after removing the dipole dopant source layer, forming gate electrodes for the transistors, where a same gate electrode material is used for the transistors. thickness(es) and/or material characteristics (e.g., dipole dopant) of the patterned dipole dopant source layers and/or parameters of the thermal drive-in process may be configured to achieve desired threshold voltages. such technique may provide 2threshold voltages (vt), where n is a number of patterned dipole dopant source layers formed on the gate dielectric layers of the transistors to tune their threshold voltages.
Inventor(s): Shu-Shen Yeh of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chih Yew of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L23/24, H01L25/00, H01L25/18
CPC Code(s): H01L23/3675
Abstract: provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. the stiffener ring is disposed on the substrate. the stiffener ring has an inner perimeter to enclose an accommodation area. the eccentric die is disposed within the accommodation area on the substrate. the eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. the lid layer is disposed on the stiffener ring and overlays the eccentric die. the buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. the buffer layer has a thickness less than a thickness of the lid layer.
Inventor(s): Hsin-Yen HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Kuan LEE of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chin LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528, H01L29/66, H01L29/78
CPC Code(s): H01L23/5226
Abstract: an interconnect structure is provided. the interconnect structure includes a first metal line and a second metal line in a first dielectric layer, a catalyst layer on the first dielectric layer, a dielectric block on the catalyst layer, an etching stop layer along the second metal line, the catalyst layer and the dielectric block, a second dielectric layer over the etching stop layer, and a first via through the second dielectric layer and the etching stop layer on the first metal line. a first interface between the etching stop layer and the second metal line is level to a second interface between the catalyst layer and the first dielectric layer.
Inventor(s): Shao-Kuan LEE of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chin LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yen HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/3213, H01L21/768, H01L23/522
CPC Code(s): H01L23/5283
Abstract: an interconnect structure is provided. the interconnect structure includes a first metal line and a second metal line, a first dielectric layer including a potion between the first metal line and the second metal line, and a first etching stop layer on the potion of the first dielectric layer.
Inventor(s): Shao-Kuan LEE of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chin LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yen HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/3213, H01L21/768, H01L23/522
CPC Code(s): H01L23/5283
Abstract: a bottom surface of the first etching stop layer is level to a top surface of the first metal line and a top surface of the second metal line. the interconnect structure also includes a second etching stop layer including a first portion extending along the top surface of the second metal line, a second portion extending along a first sidewall of the first etching stop layer, and a third portion extending along a top surface of the first etching stop layer. the interconnect structure also includes a via on the first metal line.
Inventor(s): Chun-Yen LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, G06F30/392
CPC Code(s): H01L23/5286
Abstract: an integrated circuit (ic) device includes a complementary field-effect transistor (cfet) device, a power rail at a first side of the cfet device, and a conductor at a second side of the cfet device. the cfet device includes a local interconnect. the first side is one of a front side and a back side of the cfet device. the second side is the other of the front side and the back side of the cfet device. the local interconnect of the cfet device electrically couples the power rail to the conductor.
Inventor(s): Ya-Chin CHIU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsien LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Tung HSU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Lun-Chieh CHIU of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/768
CPC Code(s): H01L23/53266
Abstract: a semiconductor structure includes a conductive line, a pad layer, and a barrier layer. the conductive line is embedded in a multi-level interconnect structure. the pad layer is over the conductive line. the barrier layer is between the conductive line and the pad layer. the pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. a boundary is between the first poly-crystalline layer and the second poly-crystalline layer.
Inventor(s): Chih-Hsuan TAI of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Ting KUO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chih HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hua CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da CHENG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua HSIEH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shi LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/683, H01L23/31
CPC Code(s): H01L24/02
Abstract: a package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. the molding compound is in contact with a sidewall of the semiconductor device. the first dielectric layer is over the molding compound and the semiconductor device. the through-via is in the molding compound and the first dielectric layer. the through-via is a continuous element and in contact with the first dielectric layer.
Inventor(s): Sin-Yao Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Shyan Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Pei Chou of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Hsuan Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L27/146
CPC Code(s): H01L24/08
Abstract: various embodiments of the present disclosure are directed towards a method for forming a semiconductor device including a shallow trench isolation (sti) structure disposed between a first side and a second side of the semiconductor substrate. an intermetal dielectric structure comprising a first metal interconnect is on the second side. a first etching process is performed to form a first trench extending from the first side of the semiconductor substrate to the sti structure. an etch stop layer is deposited on the first side. a dielectric material is deposited into the first trench to form a dielectric spacer. a second trench is etched during a second etching process. the second trench is aligned with the first trench and extends through the sti structure to the first metal interconnect. a conductive material is deposited into the second trench to form a contact pad that contacts the first metal interconnect.
Inventor(s): Hsien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/48, H01L25/00
CPC Code(s): H01L25/0657
Abstract: three dimensional structures and methods are provided in which capacitors are formed separately from a first semiconductor device and then connected to the first semiconductor device. for example, a capacitor chip is provided and then bonded to a first semiconductor die. the capacitor chip and the first semiconductor die are encapsulated with a first encapsulant, and one of the capacitor chips and the first semiconductor die are thinned to expose through vias.
Inventor(s): Wei-Xiang YOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Long FAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ta LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szuya LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/06, H01L23/522, H01L23/528
CPC Code(s): H01L27/0629
Abstract: an integrated circuit device includes a first-type transistor and a second-type transistor stacked with each other at a front side of a substrate. the second-type transistor is between the first-type transistor and the substrate. the integrated circuit device also includes a front-side inductor having one or more conductors in a front-side upper metal layer above both the first-type transistor and the second-type transistor, and a back-side inductor having one or more conductors in a back-side lower metal layer at a back side of the substrate. the front-side inductor, the first-type transistor, and the second-type transistor form a stack directly above the back-side inductor.
Inventor(s): Harry-Hak-Lay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei Cheng Wu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Feng Teng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jung Liu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L29/06, H01L29/417
CPC Code(s): H01L27/0886
Abstract: various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (fets) with fin field-effect transistors (finfets). a semiconductor substrate is patterned to define a mesa and a fin. a trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. a first gate dielectric layer is formed on the mesa, but not the fin. the trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. a second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. a first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar fet. a second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finfet.
Inventor(s): Tsun-Kai Tsao of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Hsien Chou of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jiech-Fun Lu of Madou Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14621
Abstract: various embodiments of the present disclosure are directed towards a method for forming an integrated chip. the method includes forming a mask layer on a first side of a semiconductor substrate. the mask layer comprises a plurality of sidewalls defining a plurality of openings. a first etch process is performed on the semiconductor substrate to form a plurality of recesses within the semiconductor substrate. a second etch process is performed on the semiconductor substrate to expand the plurality of recesses and form a plurality of protrusions that comprise curved opposing sidewalls.
Inventor(s): Chi-Hsien Chung of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Jui Wang of Fengshan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chi Hsiao of Tianzhong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Jong Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14634
Abstract: various embodiments of the present disclosure are directed towards an image sensor comprising a pixel with a dual-pd layout for enhanced scaling down. the pixel spans a first integrated circuit (ic) die and a second ic die stacked with the first ic die. the pixel comprises a plurality of photodetectors in the first ic die, and further comprises a plurality of pixel transistors split amongst the first ic die and the second ic die. the plurality of photodetectors are grouped into one or more pairs, each having the dual-pd layout. a dti structure completely and individually surrounds the plurality of photodetectors, and further extends completely through a substrate within which the plurality of photodetectors are arranged. as such, the dti structure completely separates the plurality of photodetectors from each other.
Inventor(s): Chi-Hsien Chung of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Jui Wang of Fengshan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chi Hsiao of Tianzhong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Jong Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H04N25/79
CPC Code(s): H01L27/14634
Abstract: the present disclosure relates to an image sensor integrated chip structure. the image sensor integrated chip structure includes one or more logic devices disposed within a first substrate and coupled to a first interconnect structure on the first substrate. a plurality of pixel support devices are disposed along a first-side of a second substrate and coupled to a second interconnect structure on the second substrate. the first substrate is bonded to the second substrate. a plurality of image sensing elements are disposed within a third substrate in pixel regions respectively including two or more of the plurality of image sensing elements. a plurality of transfer gates and a third interconnect structure are disposed on a first-side of the third substrate. the third interconnect structure includes interconnect wires and vias confined between the first-side of second substrate and the first-side of the third substrate.
Inventor(s): Zheng-Long CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768
CPC Code(s): H01L28/87
Abstract: a capacitor includes a first spiral electrode and a second spiral electrode. the first spiral electrode is over a substrate. the second spiral electrode is over the substrate and is concentric with the first spiral electrode. a first turn of the second spiral electrode connecting to a spiral center of the second spiral electrode is free of a via thereon.
Inventor(s): Chansyun David Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Keh-Jeng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chan-Lon Yang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Perng-Fei Yuh of Walnut Creek CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/66, H01L29/78
CPC Code(s): H01L29/0673
Abstract: a semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. the semiconductor device includes a stack of nanostructured channel regions disposed on a fin structure, a first gate structure disposed within the stack of nanostructured channel regions, a second gate structure surrounds the first gate structure about a first axis and surrounds the nanostructured channel regions about a second axis different from the first axis, and first and second contact structures disposed on the first and second gate structures, respectively.
Inventor(s): Meng-Huan Jao of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yuan Chen of HsinChu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh Su of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/49, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/41733
Abstract: semiconductor structures and processes are provided. a semiconductor structure according to the present disclosure includes a channel region of a semiconductor body rising above an isolation feature, a gate structure wrapping over the channel region, a source/drain feature in contact with a sidewall of the channel region, a backside silicide layer disposed on a bottom surface of the source/drain feature, and a backside contact feature extending through the isolation feature to contact a bottom surface of the backside silicide layer. a sidewall of the backside contact feature is spaced apart from the isolation feature by a first backside contact etch stop layer (cesl) and a second backside cesl.
Inventor(s): Yun Ju Fan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yuan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh Su of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L23/48, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a method includes forming a fin over a semiconductor layer, depositing an isolation feature on sidewalls of the fin, recessing a portion of the fin to form a first trench exposing a top surface of the semiconductor layer, forming a sacrificial feature in the first trench, forming an epitaxial feature over the sacrificial feature, exposing a bottom surface of the sacrificial feature, removing the sacrificial feature to form a second trench exposing a bottom surface of the epitaxial feature, and forming a conductive feature in the second trench. the conductive feature electrically couples to the epitaxial feature.
Inventor(s): Huan-Chieh SU of Tianzhong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yuan CHEN of HsinChu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Zhen YU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chuan CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi CHUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a stack of semiconductor nanostructures over a base structure and a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. the semiconductor device structure also includes a gate stack wrapped around each of the semiconductor nanostructures and a backside conductive contact connected to the second epitaxial structure. a first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. the semiconductor device structure further includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.
Inventor(s): Li-Zhen Yu of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh Su of Tianzhong Township (TW) for taiwan semiconductor manufacturing company, ltd., Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/02, H01L23/528, H01L29/06, H01L29/423, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. the second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.
Inventor(s): Tze-Chung LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Han-Yu LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Pinyen LIN of Rochester NY (US) for taiwan semiconductor manufacturing company, ltd., Fang-Wei LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Te LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/3065, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/41775
Abstract: the present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. the stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. the method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.
Inventor(s): Wei Cheng Wu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Alexander Kalnitsky of San Francisco CA (US) for taiwan semiconductor manufacturing company, ltd., Shih-Hao Lo of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Pin Ko of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L29/66
CPC Code(s): H01L29/42376
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure on a semiconductor substrate. a gate electrode structure is on the gate dielectric structure. the gate electrode structure includes a lower conductive structure and a gate body structure. the gate body structure includes an upper segment over a top surface of the lower conductive structure and a lower segment disposed between opposing inner sidewalls of the lower conductive structure.
Inventor(s): Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Lin CHEN of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Xuan HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jin CAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/423, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/66545
Abstract: semiconductor structures and methods for manufacturing the same are provided. the semiconductor structure includes a channel layer extending along a vertical direction, and a top s/d structure formed on the channel layer. the semiconductor structure also includes a bottom s/d structure formed below the channel layer, and a gate structure adjacent to the channel layer. the channel layer is surrounded by the gate structure. the semiconductor structure includes a top inner spacer layer formed on the gate structure, and a top surface of the channel layer is higher than a bottom surface of the top inner spacer layer.
Inventor(s): Wei-De Ho of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/423
CPC Code(s): H01L29/66545
Abstract: a semiconductor device includes a backside gate etch stop layer (esl) on a backside of a first gate stack, wherein a plurality of first nanostructures overlaps the backside gate esl. the backside gate esl may comprise a high-k dielectric material. the semiconductor device further includes the plurality of first nanostructures extending between first source/drain regions and a plurality of second nanostructures over the plurality of first nanostructures and extending between second source/drain regions. a first gate stack is disposed around the plurality of first nanostructures, and a second gate stack over the first gate stack is disposed around the plurality of second nanostructures. a backside gate contact extends through the backside gate esl to be electrically coupled to the first gate stack.
Inventor(s): Meng-Sheng Chang of Chu-bei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd., I-Hsin Yang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L27/06, H01L27/092, H01L29/06, H01L29/78, H01L29/786
CPC Code(s): H01L29/66545
Abstract: an embodiment includes a method including forming a first conductive feature and a second conductive feature in a substrate. the method also includes forming a first complementary field-effect transistor (cfet) over the substrate, the forming including forming a first lower transistor including a first gate and a first source/drain region. the method also includes forming a first upper transistor including a second gate and a second source/drain region, the first upper transistor overlapping the first lower transistor. the method also includes forming a conductive via fuse connected to the first conductive feature and the second source/drain region.
Inventor(s): Chih-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Ching Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Cheng Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/06, H01L29/08, H01L29/417, H01L29/423, H01L29/78
CPC Code(s): H01L29/66545
Abstract: a semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.
Inventor(s): Chen-Huang Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Jhe Sie of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chung Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Hua Hsu of Taitung City (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Uei Jang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., An Chyi Wei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shiang-Bau Wang of Pingzchen City (TW) for taiwan semiconductor manufacturing company, ltd., Ryan Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L27/092, H01L29/78
CPC Code(s): H01L29/6656
Abstract: a method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. in accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0� c., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.
Inventor(s): Chang-Miao Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Lun Min of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/78
CPC Code(s): H01L29/6681
Abstract: a semiconductor device includes a substrate, two source/drain features disposed on the substrate, a stack of channel layers disposed over the substrate and between the two source/drain features, and a gate structure disposed over and wrapping around the stack of channel layers. each channel layer of the stack of channel layers has a dog-bone shape in a cross-sectional view including the two source/drain features and the stack of channel layers. the gate structure includes a seam.
Inventor(s): Sheng-Kai Su of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jin Cai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/24, H01L29/786
CPC Code(s): H01L29/66969
Abstract: a method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. the method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.
Inventor(s): Chih-Chuan Yang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hsiu Hsu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Ming Chang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kian-Long Lim of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lien Jung Hung of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L27/088, H01L29/06, H01L29/16, H01L29/417, H01L29/66
CPC Code(s): H01L29/785
Abstract: a semiconductor device including nanosheet field-effect transistors (nsfets) in a first region and fin field-effect transistors (finfets) in a second region and methods of forming the same are disclosed. in an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.
Inventor(s): Yu-Lien Huang of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Ren Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Feng Fu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L21/8238, H01L29/417, H01L29/49, H01L29/66
CPC Code(s): H01L29/785
Abstract: in an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ild) layer over the source/drain region; a silicide between the first ild layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ild layer, the second portion of the first source/drain contact extending through the first ild layer and contacting the silicide.
Inventor(s): Tai-Chun Huang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chewn-Pu Jou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Stefan Rusu of Sunnyvale CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H04B10/60
CPC Code(s): H04B10/60
Abstract: an optical analog-to-digital converter (o-adc) converts an input optical signal (ios) into an output digital signal. the o-adc includes adc stages, each of which can generate an electrical bit of the output digital signal and an optical bit. an adc stage can include a photodetector, an adc circuit, and an optical output circuit. the photodetector generates an analog electrical signal based on a portion of the ios. the adc circuit generates a digital electrical signal (electrical bit) based on the analog electrical signal and a reference analog electrical signal, which is based on a portion of a reference optical signal (ros). the optical output circuit provides an output optical signal (oos) (optical bit) based on the digital electrical signal and the portion of the ros. photodetectors of subsequent adc stages generate analog electrical signals based further on an oos from an optical output circuit of a previous respective adc stage.
Inventor(s): Jui-Lin Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Yuan Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ting Fang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., I-Wen Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, H01L21/02, H01L21/768, H01L23/522, H01L29/40, H01L29/417
CPC Code(s): H10B10/12
Abstract: a semiconductor device includes a fin structure. a source/drain region is formed on the fin structure. a first gate structure is disposed over the fin structure. a source/drain contact is disposed over the source/drain region. the source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. the source/drain contact electrically couples together the source/drain region and the first gate structure.
Inventor(s): Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G11C11/412, H01L29/06, H01L29/10, H01L29/78
CPC Code(s): H10B10/12
Abstract: a semiconductor structure includes a first region and a second region over a substrate, a first transistor on the first region and including vertically stacked multiple first channels, and a second transistor on the second region and including vertically stacked multiple second channels. the first transistor is of a first type and the second transistor is of a second type different from the first type. one channel of the first channels has a first width and a first thickness, and one channel of the second channels has a second width and a second thickness. a first ratio of the first width to the first thickness is greater than a second ratio of the second width to the second thickness.
Inventor(s): Chih-Chuan Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Pao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Kuan Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Lien-Jung Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, H01L21/02, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H10B10/125
Abstract: a semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. the gate extension structure is in direct contact with the first source/drain feature.
Inventor(s): Meng-Sheng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Yu Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yih Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/20, G06F30/392, G11C17/16, G11C17/18, H01L23/525, H01L23/528, H01L23/532
CPC Code(s): H10B20/20
Abstract: a memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first cpode associated with a first program word line, the second polysilicon line intersecting the first active region and the first cpode intersecting the second active region. the memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second cpode associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second cpode intersecting the first active region to form a cross-arrangement of cpode.
Inventor(s): Chih-Ming Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Yi Yu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N30/50, H10N30/074, H10N30/87
CPC Code(s): H10N30/50
Abstract: the present disclosure, in some embodiments, relates to a device. the device includes a first electrode on a substrate, a piezoelectric layer on the first electrode, and a second electrode on the piezoelectric layer. a layer of hydrogen getter material is disposed on the first electrode and is separated from the piezoelectric layer by the first electrode. the layer of hydrogen getter material laterally extends past opposing outermost sidewalls of the first electrode, as viewed in a cross-sectional view.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on August 29th, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- G03F7/038
- G03F7/039
- H01L21/027
- H01L21/311
- H01L21/3213
- CPC G03F7/038
- Taiwan semiconductor manufacturing company, ltd.
- G03F7/42
- G03F7/00
- G03F7/004
- G03F7/027
- H01L21/308
- H01L21/56
- H01L23/00
- H01L23/31
- H01L23/528
- CPC G03F7/427
- G11C7/22
- G11C11/4076
- G11C11/408
- G11C11/418
- H03K19/20
- CPC G11C7/222
- G11C11/419
- CPC G11C11/419
- G11C13/00
- G06F7/544
- G11C7/06
- G11C7/10
- G11C7/14
- CPC G11C13/004
- G11C17/18
- G11C17/16
- H10B20/20
- CPC G11C17/18
- H01G4/012
- H01G4/12
- H01G4/228
- H10N30/30
- H10N30/50
- H10N30/87
- CPC H01G4/012
- H01J37/304
- H01J37/30
- H01L27/144
- H01L31/02
- H01L31/113
- H01L31/18
- CPC H01J37/304
- H01J37/32
- H01J37/244
- CPC H01J37/32935
- H01L21/28
- H01L21/02
- H01L21/762
- H01L21/8234
- H01L29/66
- CPC H01L21/28123
- H01L21/324
- H01L21/8238
- H01L25/07
- H01L27/092
- H01L29/06
- H01L29/423
- H01L29/775
- H01L29/786
- CPC H01L21/324
- H01L21/768
- H01L29/08
- H01L29/165
- H01L29/45
- H01L29/78
- CPC H01L21/76814
- H01L23/522
- H01L23/532
- CPC H01L21/76834
- CPC H01L21/7684
- CPC H01L21/76885
- CPC H01L21/823431
- H01L21/3115
- CPC H01L21/823857
- H01L23/367
- H01L23/24
- H01L25/00
- H01L25/18
- CPC H01L23/3675
- CPC H01L23/5226
- CPC H01L23/5283
- G06F30/392
- CPC H01L23/5286
- CPC H01L23/53266
- H01L21/683
- CPC H01L24/02
- H01L27/146
- CPC H01L24/08
- H01L25/065
- H01L23/48
- CPC H01L25/0657
- H01L27/06
- CPC H01L27/0629
- H01L27/088
- H01L29/417
- CPC H01L27/0886
- CPC H01L27/14621
- CPC H01L27/14634
- H04N25/79
- CPC H01L28/87
- CPC H01L29/0673
- H01L29/49
- CPC H01L29/41733
- H01L21/3065
- CPC H01L29/41775
- CPC H01L29/42376
- CPC H01L29/66545
- CPC H01L29/6656
- CPC H01L29/6681
- H01L29/24
- CPC H01L29/66969
- H01L29/16
- CPC H01L29/785
- H04B10/60
- CPC H04B10/60
- H10B10/00
- H01L29/40
- CPC H10B10/12
- G11C11/412
- H01L29/10
- CPC H10B10/125
- H01L23/525
- CPC H10B20/20
- H10N30/074
- CPC H10N30/50