TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on April 24th, 2025
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. on April 24th, 2025
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 54 patent applications
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. has applied for patents in the areas of H01L29/66 (18), H01L23/00 (13), H01L29/786 (12), H01L29/423 (12), H01L29/06 (12) H01L23/528 (2), H01L23/5226 (2), H01L21/76224 (2), H10D30/024 (1), H01L25/0657 (1)
With keywords such as: layer, structure, semiconductor, dielectric, substrate, gate, metal, disposed, surface, and forming in patent application abstracts.
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s): Hung-Yi TU of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Meng-Hsiu WU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shang-Fu YEH of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chiao-Yi HUANG of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Calvin Yi-Ping CHAO of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01B11/02, G01J3/02, G01J3/10, G01J3/12, G01J3/14, G01J3/28
CPC Code(s): G01B11/026
Abstract: a method includes generating light pulses by an illumination source toward an object; collecting the light pulses reflected from the object by an image sensor; generating a first signal-time plot of a sensor signal by the image sensor; generating a second signal-time plot of an index signal, wherein the second signal-time plot of the index signal comprises pulsed signals corresponding to the light pulses, respectively; collecting data from selected time periods of the first signal-time plot of the sensor signal, wherein the selected time periods of the first signal-time plot of the sensor signal are the same as time periods of the light pulses in the second signal-time plot of the index signal; and generating a third signal-time plot of an output signal based on the collected data.
Inventor(s): Tung-Tsun CHEN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Yi-Hsing HSIAO of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Jui-Cheng HUANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Yu-Jie HUANG of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01N27/414, G01N33/569, H01L21/762
CPC Code(s): G01N27/4148
Abstract: a method includes following steps. a beating pulse of a cardiac cell is monitored by using a biologically sensitive field-effect transistor (biofet) disposed within a semiconductor substrate. a temperature around the cardiac cell is detected by using a temperature-sensing diode disposed within the semiconductor substrate. in response to the detected temperature falling below a predetermined threshold, the cardiac cell is heated by using a heater disposed within the semiconductor substrate. the cardiac cell is placed within a fluid containment region above the biofet, and the temperature-sensing diode occupies a larger area within the fluid containment region than the heater.
Inventor(s): Chih-Tsung Shih of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chi-Yuan Shih of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/122, G02B6/12, G02B6/136, H01L31/0232, H01L31/107, H01L31/18
CPC Code(s): G02B6/122
Abstract: a waveguide photodetector includes a slab over a substrate, first and second contact portions protruding upward from the slab, and a ridge protruding upward from the slab between the first and second contact portions. a first semiconductor layer is over the substrate and includes a first doped region in the first contact portion, a second doped region in the slab between the first contact portion and the ridge, a third doped region and a sixth doped region in the ridge, a fourth doped region in the second contact portion, a fifth doped region in the slab between the second contact portion and the ridge, a first intrinsic region between the sixth and third doped regions, and a second intrinsic region between the sixth and fifth doped regions. a second semiconductor layer is over the first intrinsic region and between the sixth and third doped regions.
Inventor(s): Yu-Hao CHEN of Hsin-Chu City TW for taiwan semiconductor manufacturing company, ltd., Hui-Yu LEE of Hsin-Chu City TW for taiwan semiconductor manufacturing company, ltd., Chung-Ming WENG of Hsin-Chu TW for taiwan semiconductor manufacturing company, ltd., Jui-Feng KUAN of Zhubei City TW for taiwan semiconductor manufacturing company, ltd., Chien-Te WU of Hsin-Chu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42, G02B6/122
CPC Code(s): G02B6/4214
Abstract: disclosed are apparatus and methods for a silicon photonic (siph) structure comprising the integration of an electrical integrated circuit (eic); a photonic integrated circuit (pic) disposed on top of the eic; two or more polymer waveguides (pwgs) disposed on top of the pic and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (info rdl) layer disposed on top of the two or more pwgs. the operation of pwgs is based on the refractive indexes of the cladding and core polymers. inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. a wafer-level system implements a siph structure die and provides inter-die signal optical interconnections among the pwgs.
Inventor(s): Chen-Hua Yu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo Hsia of Jhubei City TW for taiwan semiconductor manufacturing company, ltd., Chih-Wei Tseng of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Jiun Yi Wu of Zhongli City TW for taiwan semiconductor manufacturing company, ltd., Jui Lin Chao of New Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4239
Abstract: optical devices and methods of manufacture are presented in which glass interposers are incorporated with optical devices. in some embodiments a method includes forming a first optical package and then bonding the first optical package to a first glass interposer. the first glass interposer may then be connected to a second interposer.
Inventor(s): Rabiul Islam of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Stefan Rusu of Sunnyvale CA US for taiwan semiconductor manufacturing company, ltd., Nick Samra of Austin TX US for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/43, G02B6/42, H10H20/855
CPC Code(s): G02B6/43
Abstract: an interconnect package integrates a photonic die, an electronic die, and a switch asic into one package. at least some of the components in the electronic die, such as, for example, the serializer/deserializer circuits, transceivers, clocking circuitry, and/or control circuitry are integrated into the switch asic to produce an integrated switch asic. the photonic die is attached and electrically connected to the integrated switch asic.
Inventor(s): Ying-Hui HSIEH of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Boming HSU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsiang-Chien HSU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chien-Hung LAI of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/72, C07F15/00, C23C16/48, G03F1/24, G03F1/54
CPC Code(s): G03F1/72
Abstract: a method for repairing a lithography mask is provided. the method includes receiving a lithography mask having a capping layer that includes a damaged region, identifying a location and a dimension of the damaged region of the capping layer, determining a repairing time duration based on the dimension of the damaged region of the capping layer, and forming a capping patch layer in the damaged region of the capping layer.
Inventor(s): Yen-Yu KUO of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., An-Ren ZI of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/11, C08L43/04, H01L21/027
CPC Code(s): G03F7/11
Abstract: a resist underlayer composition for extreme ultraviolet lithography is provided. the composition includes a first polymer, a second polymer, an acid generator and a solvent. the first polymer includes a first polymer backbone and an etching resistance enhancement unit covalently bonded to the first polymer backbone via a first linker. the etching resistance enhancement unit includes a silicon-containing unit including silicon-oxygen bonds or a metal-containing unit including metal-oxygen bonds. the second polymer includes a second polymer backbone and a crosslinker unit covalently bonded to the second polymer backbone via a second linker. the crosslinker unit includes one or more crosslinkable groups.
Inventor(s): Meng-Sheng Chang of Chubei City TW for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Xinfeng Township TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/24, G06F21/44, G06F21/75, G11C17/16, G11C17/18, H01L23/00, H10B20/25
CPC Code(s): G11C7/24
Abstract: a device includes a memory cell that randomly presents either a first logic state or a second logic state. the memory cell includes: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.
Inventor(s): Ping-Wei Wang of Hsin-Chu TW for taiwan semiconductor manufacturing company, ltd., Jui-Lin Chen of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Feng-Ming Chang of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/412, G11C11/417, H10B10/00
CPC Code(s): G11C11/412
Abstract: one aspect of the present disclosure pertains to a device. the device includes a memory macro having a frontside and a backside along a vertical direction. the memory macro includes edge strap areas extending lengthwise along a first direction at edges of the memory macro, a memory cell area having a plurality of memory cells, where the memory cell area is disposed between the edge strap areas along a second direction perpendicular to the first direction, and a middle strap area extending lengthwise along the first direction and disposed between the edge strap areas along the second direction, where the middle strap area divides the memory cell area into two memory cell domains. the middle strap area includes a feedthrough circuit that routes a power signal line of one of the plurality of memory cells to the backside of the memory macro.
20250131959. MEMORY DEVICE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Cheng Hung LEE of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chien-Yu HUANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-En HUANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yen-Chi CHOU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shao Hsuan HSU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Tzu-Chun LIN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/418, G11C5/06, H01L23/522, H01L23/528, H01L27/092, H01L29/66, H01L29/78, H10B10/00
CPC Code(s): G11C11/418
Abstract: a memory circuit includes a substrate with a front side and a back side opposite the front side. an interconnect structure is situated on or over the substrate and has first and second metal layers and a via electrically connecting the first and second metal layers. a word line driver circuit is configured to output a word line enable signal to a word line of a memory array. the word line driver circuit has an inverter circuit configured to receive a word line signal, and an enable transistor electrically connected to an output of the inverter circuit by a metal line that includes the first metal layer, the second metal layer, and the via.
Inventor(s): Jenn-Gwo HWU of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Sung-Wei HUANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C17/18, G11C17/16, H10B20/25
CPC Code(s): G11C17/18
Abstract: a method for forming a memory device is provided. the method includes forming first and second metal-insulator-semiconductor (mis) structures, wherein each of the first and second mis structures comprises a semiconductor layer, an insulating layer over the semiconductor layer, and a metal electrode layer over the insulating layer; performing a first breakdown process to the first mis structure; performing a second breakdown process to the second mis structure; performing a first read operation by supplying a reading voltage pulse to the metal electrode layer of the first mis structure and detecting a first read current flowing through the first mis structure; and performing a second read operation by supplying the reading voltage pulse to the metal electrode layer of the second mis structure and detecting a second read current flowing through the second mis structure, wherein the second read current is greater than the first read current.
Inventor(s): Chia-Hsi WANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yen-Yu CHEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, C23C14/34, C23C14/35, C23C14/54, H01J37/34, H01L21/66, H01L21/67
CPC Code(s): H01L21/02266
Abstract: a deposition system is provided capable of extending the chamber running time by preventing the target and other components from deformation due to thermal stress from the sputtering process by maintaining the temperature within the predetermined temperature range. the deposition system includes a substrate process chamber, a target within the substrate process chamber, and a plurality of grooves formed on the target in a circular formation. the plurality of grooves includes a first groove on a center portion of the target and a second groove on a periphery portion of the target.
Inventor(s): Che Chi Shih of Taoyuan TW for taiwan semiconductor manufacturing company, ltd., Chun-Yu Liu of New Taipei TW for taiwan semiconductor manufacturing company, ltd., James June Fan Hsu of New Taipei TW for taiwan semiconductor manufacturing company, ltd., Ku-Feng Yang of Baoshan Township TW for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Zhubei TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L21/324, H01L29/66
CPC Code(s): H01L21/02334
Abstract: a method includes forming a first de-bond structure over a first substrate, where forming the first de-bond structure includes depositing a first de-bond layer over the first substrate, depositing a first silicon layer over the first de-bond layer, depositing a second de-bond layer over the first silicon layer, and depositing a second silicon layer over the second de-bond layer, epitaxially growing a first multi-layer stack over the first de-bond structure, bonding the first multi-layer stack to a second multi-layer stack, and performing a first laser annealing process to ablate the first silicon layer and portions of the first de-bond layer and the second de-bond layer in order to de-bond the first substrate from the first multi-layer stack.
Inventor(s): Jiun-Yi Wu of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/48, H01L21/67, H01L23/00
CPC Code(s): H01L21/4853
Abstract: a method of fabrication a package and a stencil structure are provided. the stencil structure includes a first carrier having a groove and stencil units placed in the groove of the first carrier. at least one of the stencil units is slidably disposed along sidewalls of another stencil unit. each of the stencil units has openings.
Inventor(s): Chien-Hsuan LIU of Tainan TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L27/088, H01L29/66
CPC Code(s): H01L21/76224
Abstract: a semiconductor device and a method of fabricating the semiconductor device are disclosed. the method includes forming a fin structure having a first fin portion and a second fin portion, forming a first dielectric layer on the substrate and on sidewalls of the first fin portion, forming a second dielectric layer on the first dielectric layer, performing an oxidation process on the second fin portion to form an oxide layer, depositing a gate dielectric layer on the oxide layer and on the second dielectric layer, depositing a gate conductive layer on the gate dielectric layer, and forming an isolation structure extending through the gate conductive layer, the gate dielectric layer, and the second dielectric layer.
Inventor(s): Tzu-Ging Lin of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L21/76224
Abstract: a method includes forming a plurality of semiconductor regions, forming a plurality of gate stacks, wherein the plurality of gate stacks are on first portions of the plurality of semiconductor regions, and etching the plurality of gate stacks to form a plurality of openings in the plurality of gate stacks. the plurality of openings include a first opening in a first gate stack, and a second opening in a second gate stack. the first opening and the second opening are immediately neighboring each other and have an overlap with an overlap distance equal to or greater than a pitch of the plurality of semiconductor regions. the plurality of semiconductor regions are etched to extend the plurality of openings downwardly to be between dielectric isolation regions, followed by filling the plurality of openings to form fin isolation regions. the gate isolations are spaced part from the fin isolation regions.
Inventor(s): Kai-Feng Cheng of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Chi-Lin Teng of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Hai-Ching Chen of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Hsin-Yen Huang of New Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L21/311, H01L21/3213
CPC Code(s): H01L21/76829
Abstract: a semiconductor device includes a substrate, a first conductive feature disposed in a top portion of the substrate, an etch stop layer formed of a metal oxide composite and disposed on a top surface of the substrate, and a second conductive feature disposed on and through the etch stop layer and in contact with the first conductive feature. the metal oxide composite contains a metal element represented by m, and a top surface of the etch stop layer includes an m—o—x group, o representing oxygen, and x representing an element other than hydrogen.
Inventor(s): Chin-Lung CHUNG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shin-Yi YANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L21/76867
Abstract: a semiconductor structure and a manufacturing method thereof are provided. the manufacturing method includes the following steps. a trench is formed in a first interlayer dielectric (ild) layer. a metal conductor with metal dopants is filled in the trench. planarization is performed on the metal conductor with the metal dopants. a thermal treatment, a photo treatment or a bias-assist treatment is performed on the metal conductor with the metal dopants to form a self-forming metal capping layer on a first metal layer. an etching stop bi-layer structure is formed on the first interlayer dielectric layer and the self-forming metal capping layer. a via, a second interlayer dielectric (ild) layer and a second metal layer are formed on the etching stop bi-layer structure. the via is embedded in the second interlayer dielectric layer and the via is disposed between the first metal layer and the second metal layer.
Inventor(s): Yi-Nien Su of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Jyu-Horng Shieh of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/311
CPC Code(s): H01L21/76897
Abstract: a method includes forming a first mandrel and a second mandrel over a dielectric layer, and forming a first spacer and a second spacer on the first mandrel and the second mandrel, respectively. the first spacer and the second spacer are next to each other with a space in between. the dielectric layer is etched to form an opening in the dielectric layer, with the opening being overlapped by the space, and with the first spacer and the second spacer being used as a part of an etching mask in the etching. a conductive material is filled into the opening. a planarization process is performed on the conductive material.
Inventor(s): Tzu-Ting Liu of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Wen-Chiung Tu of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Ming-Wei Lee of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Chen-Chiu Huang of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, H01L23/00
CPC Code(s): H01L22/32
Abstract: the present disclosure provides a redistribution structure that includes a metal line, a first dielectric layer disposed over the metal line, a first etch stop layer (esl) disposed over the first dielectric layer, a second dielectric layer disposed over the first esl, and a conductive via extending through the second dielectric layer, the first esl and the first dielectric layer to contact the metal line. a lower portion of the second dielectric layer extends downward through the first esl and the first dielectric layer and partially into the metal line.
Inventor(s): Hsien-Wei Chen of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Meng-Liang Lin of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ying-Ju Chen of Yunlin County TW for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/29, H01L23/367, H01L23/48, H01L23/538, H01L25/00, H01L25/10, H01L25/18, H10B80/00
CPC Code(s): H01L23/3135
Abstract: a semiconductor package includes a chiplet, a first underfill surrounding the chiplet, and a first encapsulant laterally covering the first underfill. the chiplet includes a semiconductor substrate and die connectors disposed over the semiconductor substrate. the first underfill includes first fillers, and a portion of the first fillers has a substantially planar surface at a first surface of the first underfill. the first encapsulant includes a first surface and a second surface opposite to the first surface, the first surface is substantially leveled with surfaces of the die connectors, and the second surface is substantially leveled with the first surface of the first underfill.
Inventor(s): Yu-Sheng Lin of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Chin-Hua Wang of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Shu-Shen Yeh of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Chien-Hung Chen of Taipei TW for taiwan semiconductor manufacturing company, ltd., Po-Yao Lin of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L21/78, H01L23/00, H01L23/498, H01L25/00, H01L25/18
CPC Code(s): H01L23/3185
Abstract: an semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. the first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface. the second semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the second semiconductor device has a second bottom surface, a second top surface and a second side surface connecting with the second bottom surface and the second top surface, the second side surface faces toward to the first side surface, the second side surface comprises a third sub-surface and a fourth sub-surface connected with each other, the third sub-surface is connected with the second bottom surface, and a second obtuse angle is between the third sub-surface and the fourth sub-surface. the underfill layer is between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure. the encapsulant encapsulates the first semiconductor device, the second semiconductor device and the underfill layer.
Inventor(s): Wen-Ting LAN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shih-Cheng CHEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-Cheng TSAI of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L23/3192
Abstract: a semiconductor device includes a substrate, an active structure, a first dielectric layer and a second dielectric layer. the active structure is formed on the substrate and includes an active channel sheet, wherein the active channel sheet has a first lateral surface. the first dielectric layer is formed above the active structure and has a recess, wherein the recess is recessed with respect to the first lateral surface of the active channel sheet. the second dielectric layer is formed within the recess and has a dielectric constant, wherein the dielectric constant is less than 3.9.
Inventor(s): Yu-Shiou Tsai of Tainan TW for taiwan semiconductor manufacturing company, ltd., Chang-Jung Hsueh of Taipei TW for taiwan semiconductor manufacturing company, ltd., Chun-Lung Jao of Nantou TW for taiwan semiconductor manufacturing company, ltd., Po-Yao Lin of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Kathy Wei Yan of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/373, H01L23/00, H01L23/367, H01L23/498
CPC Code(s): H01L23/3736
Abstract: provided are devices and methods for forming devices. a device includes a workpiece; a thermal interface material (tim) disposed over the workpiece; and a lid disposed over the workpiece, wherein the lid has an underside formed with a trench, and wherein a vertically extending portion of the tim extends into the trench and a base portion of the tim is located outside of the trench.
Inventor(s): Yi Ling Liu of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Tsung-Chieh Hsiao of Changhua County TW for taiwan semiconductor manufacturing company, ltd., Liang-Wei Wang of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/00, H01L23/48, H01L27/088, H01L29/06, H01L29/40, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L23/5226
Abstract: a semiconductor structure and a method of forming the same are provided. in an embodiment, a method includes receiving a workpiece comprising a first transistor and a second transistor formed over a first side of a substrate, forming a first multi-layer interconnect (mli) structure over the first side of the substrate, wherein the first mli structure comprising a first plurality of metal lines and a first plurality of vias, after the forming of the first mli structure, forming a source/drain contact directly under a source/drain feature of the first transistor, and forming a second mli structure under the source/drain contact and under a second side of the substrate, the second side being opposite the first side, wherein the mli structure comprises a second plurality of metal lines and a second via, a thickness of the second via is greater than a thickness of one of the first plurality of vias.
Inventor(s): Chi-Lin TENG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Gary LIU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ting-Ya LO of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yen-Ju WU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shao-Kuan LEE of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Kuang-Wei YANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsin-Yen HUANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang CHANG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/532
CPC Code(s): H01L23/5226
Abstract: an interconnection structure is provided to include a substrate, a first metal trench, a boron nitride dielectric, a second metal trench, and a metal via. the substrate is formed with a first metal trench. the boron nitride dielectric is disposed over the substrate. the second metal trench is formed in the boron nitride dielectric. the metal via is disposed to interconnect the first metal trench and the second metal trench.
Inventor(s): Zi-Ang Su of Taoyuan County TW for taiwan semiconductor manufacturing company, ltd., Chen-Ming Lee of Taoyuan County TW for taiwan semiconductor manufacturing company, ltd., Ming-Shuan Li of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/768, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786, H01L29/868
CPC Code(s): H01L23/528
Abstract: a diode includes a p-type region, an n-type region, and an undoped intrinsic region. a first conductive contact and a second conductive contact are each disposed over a first side of the diode. the first conductive contact is electrically coupled to the p-type region from the first side. the second conductive contact is electrically coupled to the n-type region from the first side. a first conductive via and a second conductive via are each disposed over a second side of the diode. the second side is different from the first side. the first conductive via is electrically coupled to the p-type region from the second side. the second conductive via is electrically coupled to the n-type region from the second side. the first conductive contact is electrically coupled to the first conductive via. the second conductive contact is electrically coupled to the second conductive via.
Inventor(s): Ping-En CHENG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Wei-Li HUANG of Pingtung City TW for taiwan semiconductor manufacturing company, ltd., Kun-Ming TSAI of Kaohsiung TW for taiwan semiconductor manufacturing company, ltd., Shih-Hao LIN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/768
CPC Code(s): H01L23/528
Abstract: a chip structure is provided. the chip structure includes a substrate. the chip structure includes a conductive pad over the substrate. the chip structure includes a passivation layer covering the substrate and exposing the conductive pad. the chip structure includes a first etch stop layer over the passivation layer. the chip structure includes a first buffer layer over the first etch stop layer. the first etch stop layer and the first buffer layer are made of different materials. the chip structure includes a second etch stop layer over the first buffer layer. the second etch stop layer and the first buffer layer are made of different materials.
Inventor(s): Yung-Shih Cheng of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/3065, H01L27/088, H01L29/06, H01L29/40, H01L29/417, H01L29/423, H01L29/775, H01L29/786, H01L29/861
CPC Code(s): H01L23/5286
Abstract: a method includes attaching a second workpiece to a first workpiece, performing a first plasma etching process to a back side of the first workpiece to form a first trench, and forming a first backside conductive feature in the first trench. the first workpiece includes a first transistor including a source/drain (s/d) feature, a second transistor adjacent to the first transistor and comprising a gate structure, a diode, and an interconnect structure including a plurality of metal lines and vias. a first interconnect layer of the interconnect structure includes a metal line electrically coupled to the gate structure and the s/d feature. the second workpiece includes a first dielectric layer, a metal feature extending through the first dielectric layer, and a carrier substrate disposed over the first dielectric layer. the metal feature is electrically coupled to the gate structure by the diode and the plurality of metal lines and vias.
Inventor(s): Kai-Ming Chiang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chao-wei Li of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Wei-Lun Tsai of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-Min Lin of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yi-Da Tsai of Chiayi Country TW for taiwan semiconductor manufacturing company, ltd., Sheng-Feng Weng of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Yu-Hao Chen of HsinChu City TW for taiwan semiconductor manufacturing company, ltd., Sheng-Hsiang Chiu of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Chih-Wei Lin of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L21/683, H01L23/31, H01L23/538, H01L25/00, H01L25/065
CPC Code(s): H01L23/562
Abstract: a memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. the conductive terminals are disposed on a first surface of the base semiconductor die. the memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. the insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. the buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. a package structure including the above-mentioned memory device is also provided.
Inventor(s): Amram EITAN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hui-Ting LIN of Tainan TW for taiwan semiconductor manufacturing company, ltd., Chih-Yuan CHIU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Kai Jun ZHAN of Taoyuan TW for taiwan semiconductor manufacturing company, ltd., Yi Chen WU of Taichung TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/75
Abstract: embodiments of the present disclosure provide a bond stage for bonding a semiconductor integrated circuit (ic) die. the bond stage includes a bonding platform having a top surface and a bottom surface opposing the top surface, a first actuator operable to tilt the bonding platform about a first rotation axis, and a plurality of contact sensors disposed at the bonding platform.
Inventor(s): Hsien-Wei Chen of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Jie Chen of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L23/00, H01L23/31, H01L23/48, H01L23/528, H01L25/00, H10D1/68
CPC Code(s): H01L25/0657
Abstract: a package includes a first die and a second die. the first die includes a first capacitor. the second die includes a second capacitor. the second die is stacked on the first die and is located within a span of the first die. the first capacitor is electrically connected to the second capacitor.
Inventor(s): Hsien-Wei Chen of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Meng-Liang Lin of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/10, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L25/105
Abstract: a semiconductor package includes an interposer including a first redistribution structure, a first semiconductor die electrically coupled to the first redistribution structure through conductive joints, and a first encapsulant disposed on the first redistribution structure and laterally covering the first semiconductor die. the first semiconductor die includes a semiconductor substrate including a first side facing the first redistribution structure and a second side opposite to the first side, a through substrate via provided within the semiconductor substrate, and a passive device disposed between the second side of the semiconductor substrate and the conductive joints.
Inventor(s): Shih-Yu Liao of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Tsai-Hao Hung of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H02N1/00, B81B7/00, H04N23/68
CPC Code(s): H02N1/006
Abstract: a method comprises: providing a substrate comprising a first trench; forming an etch stop layer on the substrate; forming a silicon sacrificial region in the first trench; forming a first micromechanical arm array in the silicon sacrificial region; forming a second micromechanical arm array in the silicon sacrificial region; patterning and etching a top portion of each micromechanical arm in the first micromechanical arm array to form a protrusion; forming at least one polysilicon sacrificial layer on the micromechanical arms in the second micromechanical arm array and the micromechanical arms in the second micromechanical arm array, wherein the protrusion of each micromechanical arm in the first micromechanical arm array remains exposed; forming a metal layer; and removing the silicon sacrificial region and the at least one polysilicon sacrificial layer to create a cavity.
Inventor(s): Yu-Fang Chiu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Anhao Cheng of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yen-Liang Lin of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ru-Shang Hsiao of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, H01L29/06, H01L29/66, H01L29/78
CPC Code(s): H10B10/12
Abstract: a semiconductor structure includes a first isolation structure and a second isolation structure disposed in a substrate. the semiconductor structure includes a doped region interposed between the first isolation structure and the second isolation structure in the substrate. the semiconductor structure includes a gate structure disposed over the doped region. the semiconductor structure includes a first gate extension protruding from the gate structure into the first isolation structure, where the first gate extension has a first depth measured from a top surface of the substrate. the semiconductor structure further includes a second gate extension protruding from the gate structure into the second isolation structure, where the second gate extension has a second depth that is different from the first depth.
Inventor(s): Wen-Chun Keng of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Kuo-Hsiu Hsu of Taoyuan County TW for taiwan semiconductor manufacturing company, ltd., Chih-Chuan Yang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Lien Jung Hung of Taipei TW for taiwan semiconductor manufacturing company, ltd., Ping-Wei Wang of Hsin-Chu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, H01L21/02, H01L21/764, H10D30/01, H10D30/67, H10D62/10, H10D64/01, H10D84/01, H10D84/03, H10D84/85
CPC Code(s): H10B10/125
Abstract: a method according to the present disclosure includes receiving a structure. the structure includes a substrate, a first fin-shaped structure, a second fin-shaped structure, and a third fin-shaped structure disposed over the substrate, and a first isolation feature between the first fin-shaped structure and the second fin-shaped structure and a second isolation feature between the second fin-shaped structure and the third fin-shaped structure. the method further includes depositing a first dielectric layer over the first isolation feature and the second isolation feature, depositing a second dielectric layer over the first dielectric layer and the first isolation feature, but not over the second isolation feature, performing a first selective etching process to the first dielectric layer and the second dielectric layer, and performing a second selective etching process to the first dielectric layer over the second isolation feature. the second dielectric layer and the first dielectric layer have different etch resistance.
Inventor(s): Wen-Shiang LIAO of Miaoli County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/31, H01L25/16
CPC Code(s): H10D1/042
Abstract: a package structure and a formation method are provided. the method includes receiving a first chip structure, and the first chip structure has multiple conductive bonding structures and a dielectric bonding structure surrounding the conductive bonding structures. top surfaces of the conductive bonding structures and the dielectric bonding structure are coplanar. the method also includes bonding a second chip structure to the dielectric bonding structure and the conductive bonding structures through dielectric-to-dielectric bonding and metal-to-metal bonding. the method further includes forming an insulating layer over the first chip structure, and the insulating layer laterally surrounds the first chip structure. in addition, the method includes forming a capacitor element laterally spaced apart from the second chip structure, and the insulating layer partially surrounds the capacitor element.
Inventor(s): Chen-Ming Lee of Taoyuan County TW for taiwan semiconductor manufacturing company, ltd., Zi-Ang Su of Taoyuan County TW for taiwan semiconductor manufacturing company, ltd., Ming-Shuan Li of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., I-Wen Wu of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/868, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D8/50
Abstract: a diode is formed in an active region. the diode includes a p-type component embedded in a first portion of the active region, an n-type component embedded in a second portion of the active region, and an undoped component disposed between the p-type component and the n-type component. an interconnect structure is formed over a first side of the diode. different portions of the interconnect structure are electrically coupled to the p-type component and the n-type component, respectively. one or more openings are etched through a dielectric structure disposed over a second side of the diode opposite the first side. a dopant material is implanted into the active region through the one or more openings. the one or more openings are filled with a conductive material.
Inventor(s): Chun-Hsiu Chiang of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Pei Ying Lai of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Cheng-Hao Hou of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Shan-Mei Liao of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hung-Chi Wu of Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/78
CPC Code(s): H10D30/0227
Abstract: a method forming a source/drain region based on a first portion of a semiconductor region, forming a high-k dielectric layer based on a second portion of the semiconductor region, forming a dipole film on the high-k dielectric layer, performing a treatment process on the dipole film using a process gas comprising nitrogen and hydrogen, performing a drive-in process to drive a dipole dopant in the dipole film into the high-k dielectric layer, and depositing a work-function layer on the high-k dielectric layer.
Inventor(s): Ching-Pai Hsu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chi-Ruei Yeh of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Tsung-Yu Chiang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H10D30/024
Abstract: a method for manufacturing a semiconductor device includes: forming a dielectric layer on a semiconductor structure which includes a gate structure and a pair of source/drain features disposed at opposite sides of the gate structure; patterning the dielectric layer to form an opening which exposes a corresponding one of the source/drain features; conformally forming an isolation material layer to partially fill the opening, the isolation material layer including an upper portion disposed on a top surface of the patterned dielectric layer, a lower portion disposed on the corresponding one of the source/drain features, and an interconnecting portion connecting the upper portion and the lower portion; removing the upper and lower portions; and partially removing the interconnecting portion, such that the interconnecting portion has a thickness decreasing gradually in a direction from the top surface of the patterned dielectric layer to a bottom surface of the patterned dielectric layer.
Inventor(s): Shih-Hao LIN of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chia-Hung CHOU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chih-Hsuan CHEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Ping-En CHENG of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsin-Wen SU of Yunlin County TW for taiwan semiconductor manufacturing company, ltd., Chien-Chih LIN of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Szu-Chi YANG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D30/01, H10D30/62, H10D64/01, H10D84/01, H10D84/03
CPC Code(s): H10D30/0243
Abstract: a semiconductor structure includes a substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. the semiconductor layers are over the substrate and spaced apart from each other in a z-direction. the source/drain features are over the substrate. the semiconductor layers are between the source/drain features. the metal oxide layers are on top surfaces and bottom surfaces of the semiconductor layers. the gate structure covers and is in contact with center portions of the metal oxide layers on top surfaces and bottom surfaces of the semiconductor layers.
Inventor(s): Sze Hang Poon of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Jun He of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Hsi-Yu Kuo of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/768, H01L23/522, H01L23/528, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D30/6729
Abstract: semiconductor structures and methods of forming the same are provided. in an embodiment, a method includes forming a first antenna coupled to a gate structure of a transistor, the first antenna comprising a first metal line, forming a second antenna coupled to a source/drain feature of the transistor, the second antenna comprising a second metal line, wherein the first metal line and the second metal line are disposed within a same metallization layer, forming a dielectric layer over the metallization layer, performing a plasma etching process to the dielectric layer, thereby forming first trenches exposing the first metal line and second trenches exposing the second metal line, respectively, wherein the first trenches and second trenches are formed in a chronological order, and forming first and second conductive vias in the first trenches and second trenches, respectively.
Inventor(s): Yi-Syuan SIAO of Changhua city TW for taiwan semiconductor manufacturing company, ltd., Yu Tao Sun of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Meng-Han Chou of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Su-Hao Liu of Chiayi County TW for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/02, H01L21/3205, H01L29/06, H01L29/66, H01L29/786
CPC Code(s): H10D30/6735
Abstract: a method of forming a semiconductor device includes the following operations. a substrate is provided with a recess therein. an insulating layer is formed on a bottom of the recess. a seed layer is formed on the insulating layer. an epitaxial layer is grown in the recess from the seed layer.
Inventor(s): Yi-Tse Hung of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chao-Ching Cheng of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Tse-An Chen of Taoyuan City TW for taiwan semiconductor manufacturing company, ltd., Hung-Li Chiang of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Tzu-Chiang Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Lain-Jong Li of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10D48/36, H10D30/01, H10D30/62
CPC Code(s): H10D48/362
Abstract: a method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.
Inventor(s): Jhon-Jhy LIAW of Zhudong Township, Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/116
Abstract: a semiconductor structure includes a substrate; first nanostructures suspended over and vertically arranged over the substrate; a first gate structure wrapped around each of the first nanostructures; and gate spacers formed on opposite sides of the first gate structure and over a topmost one of the first nanostructures. the semiconductor structure further includes first source/drain features attached to opposite sides of the first nanostructures; and a first bottom dielectric layer formed over the substrate and below the first nanostructures. the first bottom dielectric layer is vertically sandwiched between the substrate and the first gate structure.
Inventor(s): Ta-Chun LIN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L27/088, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D62/121
Abstract: semiconductor structures and methods for manufacturing the same are provided. the semiconductor structure includes first nanostructures formed over a substrate along a first direction, and second nanostructures formed over the substrate along the first direction. the semiconductor structure includes a first gate structure formed over the first nanostructures along a second direction, and a first s/d structure formed adjacent to the first gate structure. the semiconductor structure includes a second gate structure formed over the second nanostructures along the second direction, and a second s/d structure formed adjacent to the second gate structure. the semiconductor structure includes a dielectric wall structure formed along the first direction. the dielectric wall structure includes a first portion between the first s/d structure and the second s/d structure and a second portion between the first gate structure and the second gate structure.
Inventor(s): Hwei-Jay CHU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsi-Wen TIEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Wei-Hao LIAO of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yu-Teng DAI of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Hsin-Chieh YAO of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chih-Wei LU of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Cheng-Hao CHEN of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/768, H01L21/8234, H01L23/528, H01L27/088
CPC Code(s): H10D64/021
Abstract: a semiconductor device includes a meol structure and a beol structure. the beol structure is formed over the meol structure and includes a first dielectric layer, a spacer and a conductive portion. the first dielectric layer has a lateral surface and a recess, wherein the recess is recessed with respect to the lateral surface. the spacer is formed the lateral surface and covers an opening of the recess. the conductive portion is formed adjacent to the spacer.
Inventor(s): Shao-Jyun Wu of New Taipei City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/76, H01L27/088, H01L29/06, H01L29/417, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D64/519
Abstract: gate layouts and/or devices implementing gate support structures (e.g., gate bars) to in non-active region areas (e.g., isolation regions), along with methods of fabrication thereof, are described herein. an exemplary gate support structure is connected to at least two gates (e.g., two to six, in some embodiments) that are disposed in a non-active region area. the at least two gates extend lengthwise along a first direction, and the gate support structure extends lengthwise along a second direction that is different than the first direction. the gate support structure and the at least two gates may be disposed on a substrate isolation structure, such as a shallow trench isolation (sti) structure. a composition and/or configuration of the gate support structure may be the same as or different than a composition and/or a configuration of the at least two gates.
Inventor(s): Kuo-Cheng CHING of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd., Kai-Chieh YANG of Kaohsiung City TW for taiwan semiconductor manufacturing company, ltd., Ching-Wei TSAI of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H10D30/01, H10D30/62, H10D64/01, H10D64/66, H10D64/66
CPC Code(s): H10D64/671
Abstract: aspects of the disclosure provide a method for forming a fin field effect transistor (finfet) incorporating a fin top hardmask on top of a channel region of a fin. because of the presence of the fin top hardmask, a gate height of the finfet can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. consequently, parasitic capacitance between a gate stack and source/drain contacts of the finfet can be reduced by lowering the gate height of the finfet.
Inventor(s): I-Che Lee of Taipei City TW for taiwan semiconductor manufacturing company, ltd., Wei-Gang Chiu of New Taipei City TW for taiwan semiconductor manufacturing company, ltd., Pin-Ju Chen of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd., Huai-Ying Huang of Jhonghe City TW for taiwan semiconductor manufacturing company, ltd., Yen-Chieh Huang of Changhua County TW for taiwan semiconductor manufacturing company, ltd., Kai-Wen Cheng of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L29/08, H01L29/66, H01L29/78
CPC Code(s): H10D84/853
Abstract: in some embodiments, the present disclosure relates to an integrated device, including a substrate; a gate overlying the substrate; a channel layer separated from the gate by a dielectric and overlying the gate; source/drain regions on the channel layer, the gate extending between the source/drain regions; an insertion layer conforming to an upper surface of the channel layer and comprising a first material; and a passivation layer conforming to an upper surface of the insertion layer and comprising a second material different from the first material; where the passivation layer has a higher density than the insertion layer, such that the passivation layer mitigates the diffusion of environmental materials towards the channel layer, and where the insertion layer mitigates the diffusion of the second material from the passivation layer into the channel layer.
Inventor(s): Shen-Hui Hong of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Chun-Chieh Chuang of Tainan City TW for taiwan semiconductor manufacturing company, ltd., Feng-Chi Hung of Chu-Bei City TW for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L23/00
CPC Code(s): H10F39/809
Abstract: various embodiments of the present disclosure are directed towards an image sensor including a first integrated circuit (ic) die stacked with a second ic die. the first ic die includes a plurality of photodetectors disposed within a first substrate. the second ic die includes a plurality of pixel transistors and a semiconductor capacitor disposed on a second substrate. the semiconductor capacitor includes a first capacitor electrode, a capacitor dielectric layer, and a doped capacitor region. the first capacitor electrode overlies the second substrate and comprises a protrusion disposed in the second substrate. the capacitor dielectric layer is disposed between the first capacitor electrode and the second substrate. the doped capacitor region is disposed within the second substrate and underlies the first capacitor electrode. the plurality of photodetectors, the plurality of pixel transistors, and the semiconductor capacitor define a pixel.
Inventor(s): Chih-Chiang Chang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chia-Chan Chen of Hsinchu County TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10F77/40, H10F30/221, H10F71/00, H10F77/14
CPC Code(s): H10F77/413
Abstract: disclosed are devices for optical sensing and manufacturing method thereof. in one embodiment, a device for optical sensing includes a substrate, a photodetector and a reflector. the photodetector is disposed in the substrate. the reflector is disposed in the substrate and spaced apart from the photodetector, wherein the reflector has a reflective surface inclined relative to the photodetector that reflects light transmitted thereto to the photodetector.
Inventor(s): Tai-Yen Peng of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Yu-Shu Chen of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Sin-Yi Yang of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Chen-Jung Wang of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Chien Chung Huang of Taichung City TW for taiwan semiconductor manufacturing company, ltd., Han-Ting Lin of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Jyu-Horng Shieh of Hsinchu TW for taiwan semiconductor manufacturing company, ltd., Qiang Fu of Hsinchu TW for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/01, H10N50/80
CPC Code(s): H10N50/01
Abstract: a method includes forming magnetic tunnel junction (mtj) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. the method further includes patterning the mtj stack layers to form a mtj; and performing a passivation process on a sidewall of the mtj to form a protection layer. the passivation process includes reacting sidewall surface portions of the mtj with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on April 24th, 2025
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- G01B11/02
- G01J3/02
- G01J3/10
- G01J3/12
- G01J3/14
- G01J3/28
- CPC G01B11/026
- Taiwan semiconductor manufacturing company, ltd.
- G01N27/414
- G01N33/569
- H01L21/762
- CPC G01N27/4148
- G02B6/122
- G02B6/12
- G02B6/136
- H01L31/0232
- H01L31/107
- H01L31/18
- CPC G02B6/122
- G02B6/42
- CPC G02B6/4214
- CPC G02B6/4239
- G02B6/43
- H10H20/855
- CPC G02B6/43
- G03F1/72
- C07F15/00
- C23C16/48
- G03F1/24
- G03F1/54
- CPC G03F1/72
- G03F7/11
- C08L43/04
- H01L21/027
- CPC G03F7/11
- G11C7/24
- G06F21/44
- G06F21/75
- G11C17/16
- G11C17/18
- H01L23/00
- H10B20/25
- CPC G11C7/24
- G11C11/412
- G11C11/417
- H10B10/00
- CPC G11C11/412
- G11C11/418
- G11C5/06
- H01L23/522
- H01L23/528
- H01L27/092
- H01L29/66
- H01L29/78
- CPC G11C11/418
- CPC G11C17/18
- H01L21/02
- C23C14/34
- C23C14/35
- C23C14/54
- H01J37/34
- H01L21/66
- H01L21/67
- CPC H01L21/02266
- H01L21/324
- CPC H01L21/02334
- H01L21/48
- CPC H01L21/4853
- H01L27/088
- CPC H01L21/76224
- H01L29/06
- H01L29/423
- H01L29/775
- H01L29/786
- H01L21/768
- H01L21/311
- H01L21/3213
- CPC H01L21/76829
- H01L23/532
- CPC H01L21/76867
- CPC H01L21/76897
- CPC H01L22/32
- H01L23/31
- H01L21/56
- H01L23/29
- H01L23/367
- H01L23/48
- H01L23/538
- H01L25/00
- H01L25/10
- H01L25/18
- H10B80/00
- CPC H01L23/3135
- H01L21/78
- H01L23/498
- CPC H01L23/3185
- CPC H01L23/3192
- H01L23/373
- CPC H01L23/3736
- H01L29/40
- H01L29/417
- CPC H01L23/5226
- H01L29/868
- CPC H01L23/528
- H01L21/3065
- H01L29/861
- CPC H01L23/5286
- H01L21/683
- H01L25/065
- CPC H01L23/562
- CPC H01L24/75
- H10D1/68
- CPC H01L25/0657
- CPC H01L25/105
- H02N1/00
- B81B7/00
- H04N23/68
- CPC H02N1/006
- CPC H10B10/12
- H01L21/764
- H10D30/01
- H10D30/67
- H10D62/10
- H10D64/01
- H10D84/01
- H10D84/03
- H10D84/85
- CPC H10B10/125
- H01L25/16
- CPC H10D1/042
- CPC H10D8/50
- CPC H10D30/0227
- H01L21/8238
- CPC H10D30/024
- H10D30/62
- CPC H10D30/0243
- CPC H10D30/6729
- H01L21/3205
- CPC H10D30/6735
- H10D48/36
- CPC H10D48/362
- CPC H10D62/116
- H01L21/8234
- CPC H10D62/121
- CPC H10D64/021
- H01L21/76
- CPC H10D64/519
- H01L21/28
- H10D64/66
- CPC H10D64/671
- H01L29/08
- CPC H10D84/853
- H01L27/146
- CPC H10F39/809
- H10F77/40
- H10F30/221
- H10F71/00
- H10F77/14
- CPC H10F77/413
- H10N50/01
- H10N50/80
- CPC H10N50/01