Stmicroelectronics international n.v. (20250102574). TEST TIME REDUCTION IN CIRCUITS WITH REDUNDANCY FLIP-FLOPS
TEST TIME REDUCTION IN CIRCUITS WITH REDUNDANCY FLIP-FLOPS
Organization Name
stmicroelectronics international n.v.
Inventor(s)
Akshay Kumar Jain of Bhopal IN
Jeena Mary George of Kattappana IN
TEST TIME REDUCTION IN CIRCUITS WITH REDUNDANCY FLIP-FLOPS
This abstract first appeared for US patent application 20250102574 titled 'TEST TIME REDUCTION IN CIRCUITS WITH REDUNDANCY FLIP-FLOPS
Original Abstract Submitted
according to an embodiment, a digital circuit with n number of redundant flip-flops is provided, each having a data input coupled to a common data signal. the digital circuit operates in a functional mode and a test mode. during test mode, a first flip-flop is arranged as part of a test path and n-1 flip-flops are arranged as shadow logic. a test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. at the same cycle, the test output signals of each of the n-1 number of redundant flip-flops is observed through the functional path to determine faults.
