Stmicroelectronics international n.v. (20250006725). FAIL-SAFE AND FAIL-TOLERANT INPUT/OUTPUT INTERFACE IMMUNE FROM LATCHUP
FAIL-SAFE AND FAIL-TOLERANT INPUT/OUTPUT INTERFACE IMMUNE FROM LATCHUP
Organization Name
stmicroelectronics international n.v.
Inventor(s)
FAIL-SAFE AND FAIL-TOLERANT INPUT/OUTPUT INTERFACE IMMUNE FROM LATCHUP
This abstract first appeared for US patent application 20250006725 titled 'FAIL-SAFE AND FAIL-TOLERANT INPUT/OUTPUT INTERFACE IMMUNE FROM LATCHUP
Original Abstract Submitted
the present disclosure is directed to an input/output (i/o) interface that includes a set of complementary metal-oxide semiconductor (cmos) transistors in a p-type substrate. a first n-type region is in the substrate and a second n-type region in the substrate spaced from the first n-type region, the second n-type region being a deep-nwell (dnw). a first heavily doped p-type region is between the first and second n-type regions, the first heavily doped p-type region is coupled to ground. a second heavily doped p-type region in the first n-type region, the second heavily doped p-type region and is coupled to an output terminal. a first heavily doped n-type region is in the first n-type region, the first heavily doped n-type region is coupled to a floating-well (fw) terminal. a second heavily is doped n-type region in the second n-type region. a resistor is coupled to the dnw and the resistor is coupled to a voltage supply terminal.