TEST CIRCUIT AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE TEST CIRCUIT

Organization Name

Inventor(s)

Jong Seok Jung of Icheon-si Gyeonggi-do KR

TEST CIRCUIT AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE TEST CIRCUIT

This abstract first appeared for US patent application 20250006291 titled 'TEST CIRCUIT AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE TEST CIRCUIT

Original Abstract Submitted

a test circuit including a test core configured to set a charging current quantity as a first value and perform charging and discharging on a test node of a test target circuit during a first measurement interval and configured to change the charging current quantity from the first value to a second value and perform charging and discharging on the test node during a second measurement interval, and an operation circuit configured to generate a first counting value by counting a clock signal during the first measurement interval, generate a second counting value by counting the clock signal during the second measurement interval, generate the results of an operation of the first counting value and the second counting value as operation results, and output at least one of the first counting value, the second counting value, and the operation results as test result information.