Sk hynix inc. (20240281321). MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME simplified abstract

MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME

Organization Name

sk hynix inc.

Inventor(s)

Jae Yong Son of Gyeonggi-do (KR)

Dae Sung Kim of Gyeonggi-do (KR)

Min Su Choi of Gyeonggi-do (KR)

MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240281321 titled 'MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME

The abstract describes a memory controller and a memory system that includes error correction capabilities for read retry operations.

• Error correction circuit performs error correction decoding on data read by read retry operations.
• Buffer memory stores decoding history information, including retry fail voltages and syndrome weights.
• Processor determines an optimally estimated read voltage based on the relationship between changes in syndrome weights and retry fail voltages.
• Data is read using the optimally estimated read voltage to the error correction circuit.

Potential Applications: - Data storage systems - Computer memory systems - Error correction technologies

Problems Solved: - Improving data reliability in memory systems - Enhancing error correction capabilities - Optimizing read retry operations

Benefits: - Increased data accuracy - Enhanced system performance - Improved reliability of memory systems

Commercial Applications: Optimizing memory systems for various industries such as data centers, telecommunications, and consumer electronics can lead to more efficient and reliable operations.

Questions about Memory Controller and Memory System: 1. How does the error correction circuit improve data reliability in memory systems? 2. What are the potential commercial applications of this technology?

Frequently Updated Research: Stay updated on advancements in error correction technologies and memory system optimization for the latest developments in the field.

Original Abstract Submitted

provided herein may be a memory controller and a memory system including the same. the memory controller may include an error correction circuit configured to perform error correction decoding on data that is read by read retry operations, a buffer memory configured to store decoding history information including retry fail voltages used for a failure in the read retry operations and syndrome weights respectively corresponding to the retry fail voltages, and a processor configured to, when a number of times that the read retry operations fail reaches a threshold number of times, determine a voltage corresponding to a minimum syndrome weight determined based on a relationship between changes in the syndrome weights relative to magnitudes of the retry fail voltages, to be an optimally estimated read voltage, and provide data that is read using the optimally estimated read voltage to the error correction circuit.