Samsung electronics co., ltd. (20250077370). HBM RAS CACHE ARCHITECTURE
HBM RAS CACHE ARCHITECTURE
Organization Name
Inventor(s)
Dimin Niu of Sunnyvale CA (US)
Krishna Malladi of San Jose CA (US)
Hongzhong Zheng of Los Gatos CA (US)
HBM RAS CACHE ARCHITECTURE
This abstract first appeared for US patent application 20250077370 titled 'HBM RAS CACHE ARCHITECTURE
Original Abstract Submitted
according to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. the memory cell die may be configured to store data at a memory address. the logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. the logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. the reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. the reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.
