SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR DEVICE

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SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR DEVICE

This abstract first appeared for US patent application 20250022798 titled 'SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR DEVICE

Original Abstract Submitted

according to an aspect of the present disclosure, a semiconductor device includes a peripheral structure, and a cell structure stacked on the peripheral structure. the cell structure includes a first substrate including a pad region and a cell region including a cell array region and an extending region, wherein the first substrate includes a first surface and a second surface opposite to the first surface, and wherein second surface faces the peripheral structure, a gate stacking structure including a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked on the second surface of the first substrate, a channel structure disposed on the cell array region and penetrating the plurality of gate electrodes and the plurality of interlayer insulating layers, a plurality of gate contacts disposed on the extending region and connected to the plurality of gate electrodes, respectively, a cell insulation layer positioned over the second surface of the first substrate and covering the gate stacking structure, and an input/output contact disposed on the pad region and penetrating the cell insulation layer. the peripheral structure includes a second substrate electrically connected to the first substrate, a plurality of circuit elements positioned on the second substrate, a first barrier structure positioned over the second substrate and including a plurality of lower barrier layers, a plurality of first via holes disposed on the cell region and the pad region and penetrating at least one of the plurality of lower barrier layers, a plurality of second via holes disposed on the cell region and penetrating at least one of the plurality of lower barrier layers, and a plurality of contact vias positioned within the plurality of first via holes and connected to the plurality of circuit elements. in at least one lower barrier layer of the plurality of lower barrier layers, a sum of areas of at least one of the plurality of first via holes per unit area on the pad region is equal to a sum of areas of at least one of the plurality of first via holes on the cell region and areas of the plurality of second via holes per unit area on the cell region.