SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD FOR THE SAME

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SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD FOR THE SAME

This abstract first appeared for US patent application 20250015049 titled 'SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD FOR THE SAME

Original Abstract Submitted

a semiconductor package includes a redistribution line structure that has a redistribution line layer. a first semiconductor chip is disposed above the redistribution line structure and includes a first region with a first thickness and a second region with a second thickness that is less than the first thickness. a sub-semiconductor package includes a second semiconductor chip and is disposed above the second region of the first semiconductor chip. a silicon through via penetrates the second region of the first semiconductor chip and electrically connects the sub-semiconductor package with the redistribution line structure. a sealant seals at least a portion of each of the first semiconductor chip and the sub-semiconductor package. the sub-semiconductor package is disposed within the second region of the first semiconductor chip.