STATIC CMOS-BASED COMPACT FULL ADDER CIRCUITS

Organization Name

samsung electronics co., ltd.

Inventor(s)

Saurabh Shankar Zond of Bengaluru (IN)

Debojyoti Banerjee of Bengaluru (IN)

Abhishek Ghosh of Bengaluru (IN)

Raghavendra Shirodkar of Bengaluru (IN)

Rakesh Dimri of Bengaluru (IN)

Yashaswini H G of Bengaluru (IN)

STATIC CMOS-BASED COMPACT FULL ADDER CIRCUITS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240311082 titled 'STATIC CMOS-BASED COMPACT FULL ADDER CIRCUITS

The abstract describes an apparatus with an integrated circuit containing a static complementary metal-oxide-semiconductor based full adder (FA) circuit. The FA circuit has a sum generation circuit for generating a sum output and a carry output generation circuit for generating a carry output. The sum generation circuit includes two exclusive-nor gates, while the carry output generation circuit consists of two OAI gates and a NAND gate.

The apparatus features a static complementary metal-oxide-semiconductor based full adder (FA) circuit.
The FA circuit includes a sum generation circuit and a carry output generation circuit.
The sum generation circuit comprises two exclusive-nor gates.
The carry output generation circuit consists of two OAI gates and a NAND gate.
The OAI gates and NAND gate work together to produce the carry output based on the inputs.

Potential Applications: - This technology can be used in digital signal processing applications. - It can be integrated into microprocessors for arithmetic operations. - Suitable for use in high-speed computing systems.

Problems Solved: - Provides an efficient way to perform addition operations in integrated circuits. - Enhances the speed and accuracy of arithmetic calculations. - Reduces power consumption in digital systems.

Benefits: - Improved performance in arithmetic operations. - Enhanced efficiency in digital systems. - Reduced power consumption and heat generation.

Commercial Applications: Title: "Integrated Circuit with Static CMOS Based Full Adder for High-Speed Computing Systems" This technology can be utilized in microprocessors, digital signal processors, and other high-speed computing systems. It can improve the speed and efficiency of arithmetic operations, making it valuable for industries requiring fast and accurate calculations.

Questions about the technology: 1. How does the static complementary metal-oxide-semiconductor based full adder circuit differ from other types of adder circuits? - The static CMOS based full adder circuit offers improved speed and efficiency compared to other adder circuits due to its design and configuration. 2. What are the potential challenges in implementing this technology in large-scale integrated circuits? - Implementing this technology in large-scale integrated circuits may pose challenges related to power consumption, heat dissipation, and signal integrity.

Original Abstract Submitted

provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder (fa) circuit. the fa circuit comprises a sum generation circuit configured to generate a sum output and a carry output generation circuit configured to generate a carry output. the sum generation circuit comprises a first exclusive-nor gate and a second exclusive-nor gate. the carry output generation circuit comprises a first or-and-invert (oai) gate, a second oai gate, and a nand gate. the first oai gate is configured to receive an output of the nand gate to generate one of an exclusive-nor output or a nor output of a first operand and a second operand. the second oai gate is configured to receive the output of the nand gate, an inverse of a carry input, and the generated one of the exclusive-nor output or the nor output to produce the carry output.