Samsung electronics co., ltd. (20240258437). THREE-DIMENSIONAL STACKED FIELD EFFECT TRANSISTOR simplified abstract
THREE-DIMENSIONAL STACKED FIELD EFFECT TRANSISTOR
Organization Name
Inventor(s)
Donghoon Hwang of Suwon-si (KR)
Jaehyoung Lim of Suwon-si (KR)
THREE-DIMENSIONAL STACKED FIELD EFFECT TRANSISTOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240258437 titled 'THREE-DIMENSIONAL STACKED FIELD EFFECT TRANSISTOR
The abstract describes a 3D stacked FET (Field-Effect Transistor) with a unique back-side wiring layer configuration, including multiple power lines and through-electrodes connecting the FETs.
- The 3D stacked FET includes a back-side wiring layer with first and second back-side power lines, a first FET, a second FET stacked over the first FET, and a front-side wiring layer.
- A first through-electrode connects the first FET to the second FET, while a second through-electrode connects the front-side and back-side power lines.
- The front-side wiring layer extends in one direction and includes a front-side power line connected to the second back-side power line.
- The first and second FETs share a gate that extends in another direction, with sources and drains on either side of the gate and a channel surrounded by the gate.
Potential Applications: - Advanced semiconductor devices - Integrated circuits - Power management systems
Problems Solved: - Improved power distribution - Enhanced performance in compact spaces
Benefits: - Higher efficiency - Increased functionality - Space-saving design
Commercial Applications: - Semiconductor industry - Electronics manufacturing - Power electronics market
Questions about the technology: 1. How does the unique back-side wiring layer configuration improve the performance of the 3D stacked FET? 2. What are the specific advantages of having the first and second FETs share a gate in this design?
Frequently Updated Research: - Ongoing studies on optimizing power distribution in 3D stacked FETs - Research on enhancing the integration of multiple FETs in semiconductor devices.
Original Abstract Submitted
a 3d stacked fet may include a back-side wiring layer including a first back-side power line and a second back-side power line, a first fet on the back-side wiring layer, a second fet over the first fet, a front-side wiring layer over the second fet, a first through-electrode connecting the first fet to the second fet, and a second through-electrode connecting the front-side and back-side power lines. the front-side wiring layer may extend in a first direction and may include a front-side power line connected to the second back-side power line. the first fet and the second fet may share a gate extending in a second direction. each of the first fet and the second fet may include a source and a drain respectively on both sides of the gate in the first direction, and a channel between the source and the drain and surrounded by the gate.