Samsung electronics co., ltd. (20240222201). METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE simplified abstract
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Organization Name
Inventor(s)
Seungyoon Lee of Suwon-si (KR)
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240222201 titled 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
The method described in the abstract involves forming photoresist patterns by exposing different field areas of multiple layers, measuring intra-field overlay, and determining correction parameters based on the overlay measurements.
- Formation of photoresist patterns by exposing specific field areas of different layers
- Measurement of intra-field overlay for top and bottom field areas
- Determination of correction parameters based on overlay measurements
Potential Applications: - Semiconductor manufacturing - Nanotechnology - Optoelectronics
Problems Solved: - Improving alignment accuracy in multi-layer patterning processes - Enhancing overall device performance
Benefits: - Increased precision in pattern formation - Higher quality and efficiency in manufacturing processes
Commercial Applications: Title: Advanced Semiconductor Patterning Technology for Enhanced Device Performance Description: This technology can be utilized in the semiconductor industry to improve the accuracy and quality of device manufacturing processes, leading to enhanced performance and reliability in electronic devices.
Questions about the technology: 1. How does this technology improve the alignment accuracy in multi-layer patterning processes? 2. What are the potential benefits of using correction parameters based on overlay measurements in semiconductor manufacturing?
Original Abstract Submitted
the method including forming a first photoresist (pr) pattern by exposing first field areas of a first pr layer, forming a second pr pattern by exposing first top field areas and first bottom field areas of a second pr layer, measuring a first top intra-field overlay for the first top field areas and a first bottom intra-field overlay for the first bottom field areas, and determining a top intra-field correction parameter and a bottom intra-field correction parameter based on the first top intra-field overlay and the first bottom intra-field overlay, respectively, may be provided.