STMicroelectronics International N.V. patent applications on March 6th, 2025
Patent Applications by STMicroelectronics International N.V. on March 6th, 2025
STMicroelectronics International N.V.: 33 patent applications
STMicroelectronics International N.V. has applied for patents in the areas of H02M3/158 (4), H01L23/31 (2), H01L23/00 (2), H02M1/00 (2), G11C13/00 (2) H02M3/1582 (3), A61B5/1118 (1), H01L24/40 (1), H10F39/8037 (1), H10D89/814 (1)
With keywords such as: signal, circuit, voltage, transistor, sensor, between, configured, output, coupled, and control in patent application abstracts.
Patent Applications by STMicroelectronics International N.V.
Inventor(s): Diego CARRERA of Lodi (IT) for stmicroelectronics international n.v., Carlo GHIGLIONE of Genova (IT) for stmicroelectronics international n.v., Beatrice ROSSI of Milano (IT) for stmicroelectronics international n.v., Pasqualina FRAGNETO of Burago di Molgora (IT) for stmicroelectronics international n.v., Giacomo BORACCHI of Buccinasco (IT) for stmicroelectronics international n.v.
IPC Code(s): A61B5/11, A61B5/00
CPC Code(s): A61B5/1118
Abstract: a method of operating an inertial sensor module includes receiving a stream of inertial sensor data representing activity of a user of an electronic device and generating a plurality of wavelet sub-bands by performing a wavelet transform on the inertial sensor data. the method includes identifying a wavelet sub-band of highest energy from the plurality of wavelet sub-bands, generating augmented inertial sensor data by combining the wavelet sub-band of highest energy to the inertial sensor data, and identifying a first transition in the activity of the user based on the augmented inertial sensor data.
Inventor(s): Enrico Rosario Alessi of Catania (IT) for stmicroelectronics international n.v., Daniele Baldacchino of Catania (IT) for stmicroelectronics international n.v., Fabio Passaniti of Siracusa (IT) for stmicroelectronics international n.v., Michele Alessio Dellutri of Catania (IT) for stmicroelectronics international n.v.
IPC Code(s): A61B5/297, A61B3/113, A61B5/256
CPC Code(s): A61B5/297
Abstract: a wearable device for detecting a user's eye movement having a first movement sensor with electrodes aligned with each other along a first movement axis, a second movement sensor with electrodes aligned with each other along a second movement axis transverse to the first movement axis, and a control circuit coupled to the electrodes and configured to acquire electrostatic charge variation signals indicative of differences between the electrostatic charge variations detected by the electrodes of the movement sensors; detect an event indicative of respective displacements of the eyes along the movement axis; and determine the movement of the eyes based on of the event confirmation.
Inventor(s): Björn MAGNUSSON LINDGREN of Norrköping (SE) for stmicroelectronics international n.v., Mathias ISACSON of Linköping (SE) for stmicroelectronics international n.v.
IPC Code(s): C30B29/36, C30B25/18
CPC Code(s): C30B29/36
Abstract: a structure including a base portion (e.g., made of a graphite-based or graphene-based material) with at least one surface that is coated with a homogenous coating layer (e.g., made of silicon-carbide (sic)). the homogenous coating layer prevents contaminants (e.g., carbon) from being released by the base portion into a cavity of a processing tool when heated to process one or more workpieces (e.g., silicon substrate, silicon wafers, etc.) present within the cavity. the homogenous coating layer includes grains and grain boundaries that are relatively the same size and shape as each other, which further prevents propagation of defects (e.g., cracking, peeling, etc.) that could potentially cause exposure of a region of the first surface of the base portion to the cavity of the processing tool contaminating the one or more workpieces present within the cavity of the processing tool.
Inventor(s): Alessandro MAGNANI of Milan (IT) for stmicroelectronics international n.v., Matteo QUARTIROLI of Certosa di Pavia (IT) for stmicroelectronics international n.v., Alessandro MECCHIA of Vimercate (IT) for stmicroelectronics international n.v.
IPC Code(s): G01C19/5712, G01C25/00
CPC Code(s): G01C19/5712
Abstract: a sensor module includes a pattern generator configured to generate a variable frequency self-test signal. the sensor module includes an inertial sensor including a self-test electrode configured to receive the frequency sweep self-test signal. the inertial sensor is configured to generate an analog sensor signal based on the self-test signal. the sensor module includes an analog to digital converter configured to generate a digital sensor signal based on the analog sensor signal and a demodulator including a first input configured to receive the digital sensor signal, a second input configured to receive the self-test signal, and an output configured to output a demodulated signal. the sensor module includes a first low pass filter coupled to the output of the demodulator and configured to generate a baseband signal. the sensor module includes a calibration circuit configured to identify different mems characteristics, like resonance frequency, q-factor, or sensitivity based on the baseband signal.
Inventor(s): Marco Maria Branciforte of Catania (IT) for stmicroelectronics international n.v., Fabrizio La Rosa of San Pietro Clarenza (IT) for stmicroelectronics international n.v.
IPC Code(s): G01N27/60, G01N33/24
CPC Code(s): G01N27/605
Abstract: a soil sensor includes a signal generator, and a transmitter coupled to the signal generator, the transmitter configured to transmit a signal from the signal generator, the signal having a fixed frequency, the transmitter including a transmit electrode embedded within a first dielectric material. the soil sensor includes a receiver, the receiver being configured to electrostatically couple to the transmitter through a channel including soil, the receiver including a charge variation (qvar) electrode embedded within a second dielectric material. the soil sensor includes a charge variation (qvar) sensor coupled to the qvar electrode, the qvar sensor configured to detect a variation in charge detected at the qvar electrode in response to the signal from the signal generator and output a digital signal including the charge detected. and the soil sensor further includes a processing circuit coupled to the qvar sensor and configured to determine a level of moisture in the channel based on the digital signal.
Inventor(s): Giulio RICOTTI of Broni (IT) for stmicroelectronics international n.v., Alessandro SACCA' of Milan (IT) for stmicroelectronics international n.v., Valeria BOTTAREL of Novara (IT) for stmicroelectronics international n.v., Niccolo' BRAMBILLA of San Donato Milanese (IT) for stmicroelectronics international n.v.
IPC Code(s): G01R31/66, H02M3/158
CPC Code(s): G01R31/66
Abstract: provided is a power converter including first, second, third and fourth nodes and a wire bonding test circuit. the wire bonding test circuit includes a multiplexer having a first terminal of a first side coupled to the first node and second and third terminals of a second side. the wire bonding test circuit includes a first switch having a first terminal coupled to the second terminal or the third terminal of the multiplexer and a second terminal coupled to the second node. the wire bonding test circuit includes a second switch having a first terminal coupled to the second terminal or the third terminal of the multiplexer and a second terminal coupled to the third node. the wire bonding test circuit includes a third switch having a first terminal coupled to the second terminal or the third terminal of the multiplexer and a second terminal coupled to the fourth node.
Inventor(s): Wei Liang Keith NGUYEN of Singapore (SG) for stmicroelectronics international n.v., Jelah Nieva CACERES of Singapore (SG) for stmicroelectronics international n.v.
IPC Code(s): G01S7/481, G01S7/487, G01S7/493, G02B5/122, G02B5/126
CPC Code(s): G01S7/4813
Abstract: an example electronic system utilizing an optical ranging, proximity, and/or image sensor configured with retroreflective mechanisms to reduce unwanted optical noise at an optical radiation receiver are provided. the example ranging, proximity, and/or image sensor is configured to include a housing cap having a transmission opening and a receiving opening. the example sensor may further include an optical radiation source positioned to direct ranging optical radiation through the transmission opening toward a target object. an optical radiation receiver is positioned to receive ranging optical radiation reflected off the target object through the receiving opening. a retroreflective mechanism implemented on a surface of the housing cap directs unwanted optical noise back towards an unwanted optical noise source and away from the optical radiation receiver. properties of the target object may be determined based on one or more properties of the ranging optical radiation received at optical radiation receiver.
Inventor(s): John Kevin MOORE of Edinburgh (GB) for stmicroelectronics international n.v.
IPC Code(s): G01S7/4865, G01S7/4863, G01S17/10, G01S17/894
CPC Code(s): G01S7/4865
Abstract: a time-of-flight (tof) sensor includes a timing generator generating a timing reference, a first array of tof-related components including rows of tof-related components, with each row receiving the timing reference, and a dummy row of tof-related components. the tof sensor also includes a second array of tof-related components including rows of tof-related components, with each row receiving the timing reference, and a dummy row of tof-related components. a first path delivers the timing reference to the rows of the first array, the first path passing from the timing generator, through the dummy row of tof-related components in the second array, to the first array of tof-related components. a second path delivers the timing reference to the rows of the second array, the second path passing from the timing generator, through the dummy row of tof-related components in the first array, to the second array of tof-related components.
Inventor(s): Federico RIZZARDINI of Settimo Milanese (IT) for stmicroelectronics international n.v., Lorenzo BRACCO of Chivasso (IT) for stmicroelectronics international n.v.
IPC Code(s): G05B23/02
CPC Code(s): G05B23/024
Abstract: sensor device with a microcontroller unit and a sensor including a transducer, which is coupleable to a device and generates a signal indicative of a physical quantity, and a processing circuit including: a conversion stage which generates samples of the physical quantity; a data generation stage which generates data vectors as a function of the samples, each data vector being formed by programmable quantity values; and a decision stage. the microcontroller unit programs the decision stage so that it classifies the data vectors by executing a decision tree having a structure and thresholds. in a configuration mode, the microcontroller unit programs the data generation stage; in a calibration mode, the microcontroller unit acquires a corresponding set of data vectors, determines, for each programmable quantity, a corresponding range of admissible values and programs the thresholds as a function of the ranges of admissible values; in a detection mode, the decision stage classifies the data vectors, by executing the decision tree on the basis of the programmed thresholds.
20250076914. VOLTAGE REGULATOR_simplified_abstract_(stmicroelectronics international n.v.)
Inventor(s): Marc JOISSON of Brie et Angonnes (FR) for stmicroelectronics international n.v., Mounir BOULEMNAKHER of Coublevie (FR) for stmicroelectronics international n.v.
IPC Code(s): G05F3/16
CPC Code(s): G05F3/16
Abstract: a device includes a first mos transistor connected between first and second nodes, a selectively activatable current source connected between the second node and a third node and a circuit configured to control the first transistor to regulate a voltage at the second node to a first set point value. the device further includes a second mos transistor connected between the first node and a fourth node, and having its gate connected to the gate of the first mos transistor, a third mos transistor connected between the third and fourth nodes, a switch connected between the second and fourth nodes, and another circuit configured to control the third transistor to regulate a voltage at the fourth node to a second set point value.
Inventor(s): Pierre LE CORRE of Liffré (FR) for stmicroelectronics international n.v.
IPC Code(s): G06F8/33, G06F40/109, G06F40/194
CPC Code(s): G06F8/33
Abstract: a method of facilitating live feedback on code generation includes generating first source code based on user configuration, presenting the generated first source code in a live preview user interface, and obtaining a change to the user configuration. the method also includes, responsive to the obtaining of the first change: generating second source code based on the first change; computing differences between the second source code and the first source code; and presenting the second source code in the live preview user interface by: visually signaling a correspondence between the first change and portions of the second source code that are associated with the differences; and visually distinguishing the portions of the second source code from other portions of the second source code.
Inventor(s): Michael GIOVANNINI of Grenoble (FR) for stmicroelectronics international n.v.
IPC Code(s): G06F21/54, G06F21/55, G06F21/85
CPC Code(s): G06F21/54
Abstract: provided is a module for monitoring instructions of a microcontroller. the module is adapted to receive instructions that are received at an input terminal of the microcontroller or that are being processed by a code pointer of the microcontroller. the module verifies the instructions received on the input terminal of the microcontroller or that are being processed by the code pointer of the microcontroller.
Inventor(s): Harsh RAWAT of Faridabad (IN) for stmicroelectronics international n.v., Kedar Janardan DHORI of Ghaziabad (IN) for stmicroelectronics international n.v., Promod KUMAR of Greater Noida (IN) for stmicroelectronics international n.v., Nitin CHAWLA of Noida (IN) for stmicroelectronics international n.v., Manuj AYODHYAWASI of Noida (IN) for stmicroelectronics international n.v.
IPC Code(s): G11C7/10, G11C7/12
CPC Code(s): G11C7/1087
Abstract: a memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. the memory array also includes a plurality of in-memory-compute (imc) cells arranged as a set of rows of imc cells intersecting the plurality of columns of the memory array. each of the imc cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.
Inventor(s): Marcella CARISSIMI of Treviolo (IT) for stmicroelectronics international n.v., Marco PASOTTI of Travaco' Siccomario (PV) (IT) for stmicroelectronics international n.v., Riccardo ZURLA of Binasco (IT) for stmicroelectronics international n.v.
IPC Code(s): G11C13/00, G06F7/523
CPC Code(s): G11C13/003
Abstract: a memory array includes memory cells arranged in a matrix with cell rows coupled to word lines and cell columns coupled to output bit lines. a control circuit maps a first group of memory cells to a first in-memory compute operation producing computation output signals on first output bit lines from a first matrix vector multiplication of a first input vector with a first group of computation weights stored in the first group of memory cells and maps a second group of memory cells to a second in-memory compute operation producing computation output signals on second output bit lines, different from the first output bit lines, from a second matrix vector multiplication of a second input vector, different from the first input vector, with a second group of computation weights stored in the second group of memory cells. the first and second in-memory compute operations are substantially simultaneously executed.
Inventor(s): Davide Manfré of Pandino (CR) (IT) for stmicroelectronics international n.v., Maurizio Francesco Perroni of Messina (IT) for stmicroelectronics international n.v., Massimo Caruso of Messina (IT) for stmicroelectronics international n.v., Fabio Enrico Carlo Disegni of Spino d'adda (IT) for stmicroelectronics international n.v., Cesare Torti of Pavia (IT) for stmicroelectronics international n.v.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/0069
Abstract: a non-volatile memory includes a row decoder comprising, for each word-line, a respective pull-up connected to a first supply voltage and a switching circuit for selectively connecting one of the word-lines to ground. the row decoder comprises a demultiplexer connected to a second supply voltage smaller than the first, and configured to assert an enable signal as a function of an address signal. the switching circuit comprises two n-channel fets connected in series between the word-line and ground, with the gate terminal of one fet connected to a first signal and the gate terminal of the other fet connected to a second voltage. a bias circuit is configured to set the voltage between the two fets to the second voltage when the fets are opened. the switching circuit comprises a p-channel fet connected between the word-line and the second voltage, and a gate terminal connected to a second signal.
Inventor(s): Jerome LOPEZ of Saint Jean De Moirans (FR) for stmicroelectronics international n.v., Luc PETIT of Fontaine (FR) for stmicroelectronics international n.v., Karine SAXOD of Porte de Savoie (FR) for stmicroelectronics international n.v.
IPC Code(s): H01L23/373, H01L21/48, H01L23/00, H01L23/31, H01L23/498
CPC Code(s): H01L23/3736
Abstract: an integrated circuit package includes a support plate having a mounting face. an electronic chip, having a rear face and a front face, is mounted on the mounting face with the front face electrically connected to the mounting face of the support plate. a deformable thermally conductive film covers at least one portion of the rear face of the electronic chip so that the film is in contact with the rear face.
Inventor(s): Mauro MAZZOLA of Calvenzano (BERGAMO) (IT) for stmicroelectronics international n.v., Matteo DE SANTA of Mezzago, Lombardia (MB) (IT) for stmicroelectronics international n.v.
IPC Code(s): H01L23/00, H01L21/56, H01L23/31
CPC Code(s): H01L24/40
Abstract: a substrate includes electrically conductive leads arranged laterally of a die mounting location. a semiconductor die is mounted at the die mounting location. an electrical coupling member electrically couples the semiconductor die with one or more electrically conductive leads. the electrical coupling member includes one or more electrically conductive pads having first and second electrically conductive ribbons protruding therefrom. the first and second electrically conductive ribbons have proximal ends at the electrically conductive pad and distal ends away from the electrically conductive pad. the distal ends of the first and second electrically conductive ribbons are electrically coupled to the semiconductor die and an electrically conductive lead, respectively, to provide electrical coupling therebetween.
Inventor(s): Sandor PETENYI of Lysa nad Labem (CZ) (CZ) for stmicroelectronics international n.v., Lukas MACHACEK of Praha 10 (CZ) for stmicroelectronics international n.v., Salvatore D'ANGELO of San Pietro Clarenza (IT) for stmicroelectronics international n.v.
IPC Code(s): H02H3/20, G01R31/74
CPC Code(s): H02H3/20
Abstract: disclosed herein is method for fault detection and communication in analog power electronic circuits with a multiplicity of electronic fuses (e.g., a primary fuse and at least one secondary fuse). current flow is monitored through each fuse. fault conditions in these electronic fuses are identified. upon detection, the fault signaling line, which is common to all fuses, is driven to a voltage indicative of the detected fault condition. the primary electronic fuse then latches the voltage on this fault signaling line. a detection and communication circuit enables corrective actions to be performed at the fuse level, dictated by the latched voltage.
Inventor(s): Giuseppe CALDERONI of Catania (IT) for stmicroelectronics international n.v., Marco ATTANASIO of Olbia-Tempio (IT) for stmicroelectronics international n.v.
IPC Code(s): H02M3/158, G09G3/3258, H02M1/00
CPC Code(s): H02M3/1582
Abstract: a load is powered between positive and negative rails. a switching converter generates the negative rail voltage based on an input voltage, with a power transistor involved therein. a replica generator produces a replica voltage mirroring the drain-to-source voltage of the power transistor. a buffer buffers the replica voltage. a first switch selectively connects the buffered voltage to an output node, in response to a control signal with a duty-cycle proportional to the input voltage divided by the negative rail voltage. a second switch selectively connects the buffered voltage to ground, according to the inverse of the control signal, resulting in a pwm signal at the output node. an output filter filters the pwm signal to generate a sense voltage indicative of the output current flowing from the load device. a processing circuit determines the input current from the positive rail to the load device based on the sense voltage.
Inventor(s): Ivan Floriani of Milano (IT) for stmicroelectronics international n.v.
IPC Code(s): H02M3/158, H02M3/157
CPC Code(s): H02M3/1582
Abstract: control device for a switching voltage regulator. a control loop circuit generates a control signal indicative of the difference between the output voltage of a switching circuit and a nominal voltage. a drive signal generator is coupled to the control loop circuit and receives a measurement signal indicative of the current flowing in the switching circuit. the drive signal generator also receives a reference signal correlated to the control signal and generates pulse-width modulated switching signals for the switching circuit to maintain the output voltage at a regulated value. the drive signal generator compares the measurement signal with the reference signal at the peaks of the measurement signal in the first measurement mode and at the valleys of the measurement signal in the second. an offset generator generates an offset signal which is added to the control signal at a transition between the first and the second measurement modes.
Inventor(s): Ivan Floriani of Milano (IT) for stmicroelectronics international n.v.
IPC Code(s): H02M3/158, H02M1/00, H02M1/08
CPC Code(s): H02M3/1582
Abstract: the control device for a regulator with a switching circuit. the device includes an oscillator that provides a clock signal having a switching period; a circuit that provides a comparison signal indicative of a comparison between an input voltage and an output voltage; and a circuit that generates a signal to drive the switches of the switching circuit as a function of an error between the output voltage and a nominal voltage. the device controls, within the switching period, a first phase having a current path between the input and output node through the inductive element; a second phase having a current path between the input and common node through the inductive element; and a third phase having a current path between the output and common node through the inductive element. the sequence of the first, second, and third phases is a function of the comparison signal.
Inventor(s): Sebastien SADLO of Paris (FR) for stmicroelectronics international n.v., Nathalie DELTIMPLE of Pessac (FR) for stmicroelectronics international n.v., Andreia CATHELIN of Laval-en-Belledonne (FR) for stmicroelectronics international n.v.
IPC Code(s): H03F3/04, H03F1/56
CPC Code(s): H03F3/04
Abstract: an amplifier including a first amplification stage unit that includes a first transistor configured to modulate a first transistor threshold voltage using a first control voltage on a body of the first transistor, and a first direct current permitting feedback loop electrically coupling a drain of the first transistor with a gate of the first transistor. the amplifier may include a second amplification stage unit that includes a second transistor configured to modulate a second transistor threshold voltage using a second control voltage on a body of the second transistor, and a second direct current permitting feedback loop electrically coupling a drain of the second transistor with a gate of the second transistor.
20250080072. NFC DEMODULATION CIRCUIT_simplified_abstract_(stmicroelectronics international n.v.)
Inventor(s): Franck MONTAUDON of Meylan (FR) for stmicroelectronics international n.v., Mounir BOULEMNAKHER of Coublevie (FR) for stmicroelectronics international n.v., Julien GOULIER of Grenoble (FR) for stmicroelectronics international n.v.
IPC Code(s): H03F3/45
CPC Code(s): H03F3/45475
Abstract: an amplification circuit includes an amplifier circuit (provided by an operational amplifier) that amplifies a signal to be demodulated. a feedback loop of the amplification circuit has a resistance value that is controlled to discretely vary according to a level of an output node of the amplifier circuit. a comparison of the output level with respect to one or a plurality of thresholds, which define out-of-saturation operating ranges of the amplifier circuit, drives selection of the resistance value.
Inventor(s): Philippe GALY of Le Touvet (FR) for stmicroelectronics international n.v., Serge PONTAROLLO of Saint-Egreve (FR) for stmicroelectronics international n.v.
IPC Code(s): H03K17/081
CPC Code(s): H03K17/08104
Abstract: an electrostatic discharge protection circuit protects a first transistor. the circuit includes n diodes in series between conduction terminals of the first transistor. a second transistor and third transistor are connected in series between the conduction terminals of the first transistor. a control terminal of the third transistor is coupled to an anode of the n diodes. a first inverter couples the control terminals of the first and second transistors. a fourth transistor is connected in parallel with the first transistor. a control terminal of the fourth transistor is coupled to the junction point of the second and third transistors. a capacitor is arranged between the control terminal of the fourth transistor and a conduction terminal of the first transistor.
Inventor(s): Sandor PETENYI of Lysa nad Labem (CZ) (CZ) for stmicroelectronics international n.v., Lukas BURYANEC of Trutnov (CZ) for stmicroelectronics international n.v.
IPC Code(s): H03K17/082, H03K5/24
CPC Code(s): H03K17/082
Abstract: a power circuit includes a power transistor coupled between input and output nodes and receiving a control signal. a current sensing current senses a power current provided by the power transistor to the output node and generates a sense voltage. a voltage sensing circuit senses a drain-to-source voltage of the power transistor and generates a vds sense current. a safe operating area (soa) shaping circuit has a gain set by an adjustable resistance that is dynamically adjusted based upon the vds sense current, the soa shaping circuit applying the gain to the sense voltage to produce an adjusted sense voltage. a timing circuit generates an intermediate voltage by comparing the adjusted sense voltage and a first reference. an output comparator asserts a flag in response to the intermediate voltage becoming at least equal to a second reference. the control signal is modified in response to assertion of the flag.
Inventor(s): Marco PASOTTI of Travaco' Siccomario (PV) (IT) for stmicroelectronics international n.v., Riccardo ZURLA of Binasco (IT) for stmicroelectronics international n.v., Marcella CARISSIMI of Treviolo (IT) for stmicroelectronics international n.v., Riccardo VIGNALI of Graffignana (Lodi) (IT) for stmicroelectronics international n.v., Alessandro CABRINI of Pavia (IT) for stmicroelectronics international n.v.
IPC Code(s): H03K21/02
CPC Code(s): H03K21/023
Abstract: an in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. groups of memory cells store computational weights for an in-memory compute (imc) operation that is performed with a first multiply and accumulate (mac) elaboration to produce a first analog signal and a second mac elaboration to produce a second analog signal. an analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.
Inventor(s): Thierry SIMON of Wezembeek-Oppem (BE) for stmicroelectronics international n.v., Ronny VAN KEER of Hoeilaart (BE) for stmicroelectronics international n.v.
IPC Code(s): H04L9/00, H04L9/08
CPC Code(s): H04L9/002
Abstract: various examples in accordance with the present disclosure provide example methods, systems, and apparatuses that may compute hamming weight of a bit string.
Inventor(s): Giampiero BORGONOVO of Giussano (IT) for stmicroelectronics international n.v., Lorenzo RE FIORENTIN of Oulx (IT) for stmicroelectronics international n.v.
IPC Code(s): H04L67/12, G06F9/455
CPC Code(s): H04L67/12
Abstract: the bandwidth of soc interfaces is exploited while minimizing the number of physical ports via a networking accelerator for use on board a vehicle, for instance, that comprises: media access control (mac) controller circuitry configured to provide a mac port layer to control exchange of information, wherein the exchange of information comprises data flow transmission to virtual machine ports (vmps) over a data link; virtual machine transmission (vm tx) bridge circuitry configured to handle transmission data flow to the vmps; transmission router/switch circuitry configured to route/switch data flow from the mac controller circuitry to the vm tx bridge circuitry; and queue handler circuitry configured to provide queue management for data flow between the mac controller circuitry and the vm tx bridge circuitry. the vm tx bridge circuitry comprises virtual destination address circuitry configured to implement router/switch virtualization in the transmission router/switch circuitry with a virtual machine transmission descriptor based on a combination of a virtual machine port (vmp) tag indicative of a physical resource in the queue handler circuitry selectable for data flow transmission, and a virtual machine extended identifier (vmeid).
Inventor(s): Arnaud YVON of Saint-Cyr sur Loire (FR) for stmicroelectronics international n.v.
IPC Code(s): H01L29/66, H01L29/20, H01L29/778
CPC Code(s): H10D30/015
Abstract: a process forms a high electron mobility transistor (hemt) device with a recessed gate without damaging sensitive areas of the hemt device. the process utilizes a first epitaxial growth process to grow a first set of layers of the hemt. the epitaxial growth process is then stopped and a passivation layer is formed on the first set of layers. the passivation layer is then patterned to provide a passivation structure at a desired location of the recessed gate electrode. the channel layer and one or more barrier layers are then formed in a second epitaxial growth process in the presence of the passivation structure. the result is that the channel layer and the barrier layer growth around the passivation structure. the passivation structure is then removed, effectively leaving a recess in the channel layer. the gate electrode is then formed in the recess.
20250081546. VERTICAL POWER COMPONENT_simplified_abstract_(stmicroelectronics international n.v.)
Inventor(s): Frederic LANOIS of Tours (FR) for stmicroelectronics international n.v.
IPC Code(s): H01L29/06, H01L29/16, H01L29/872
CPC Code(s): H10D62/107
Abstract: the present description relates to a vertical power component formed in and on a semiconductor substrate doped with a first conductivity type and coated, on the upper side thereof, with a semiconductor layer doped with the first conductivity type. the component includes: an active region (a); and first and second groups of first concentric field limiting rings surrounding the active region. each first ring includes a first semiconductor region doped with a second conductivity type, opposite to the first conductivity type, extending vertically into the thickness of the semiconductor layer from the upper side thereof; and a second field limiting ring laterally interposed between the first and second groups of first field limiting rings (gr). the second ring includes a second doped semiconductor region of the second conductivity type extending vertically into the thickness of the semiconductor layer from the upper face thereof. the second semiconductor region has a width at least three times larger than the width of the widest first semiconductor region.
Inventor(s): Chloe TROUSSIER of Grenoble (FR) for stmicroelectronics international n.v., Johan BOURGEAT of Crêts En Belledonne (FR) for stmicroelectronics international n.v.
IPC Code(s): H01L27/02
CPC Code(s): H10D89/814
Abstract: an esd protection device includes at least one semiconductor electronic switch electrically coupled in parallel with a diode. the semiconductor electronic switch and the diode each include at least one finger extending substantially parallel to a first direction. the fingers of the semiconductor electronic switch and of the diode are aligned with each other along this first direction.
20250081644. IMAGE SENSOR_simplified_abstract_(stmicroelectronics international n.v.)
Inventor(s): Tarek LULE of Saint-Egreve (FR) for stmicroelectronics international n.v.
IPC Code(s): H01L27/146, H04N25/77, H04N25/78
CPC Code(s): H10F39/8037
Abstract: the present disclosure relates to an image sensor comprising an array of pixels arranged in first rows and in first columns. the pixels are arranged in groups of n*n pixels, with n an integer equal to or higher than 2. in each group, the pixels of the group are distributed into one or more sub-groups of a plurality of pixels. each pixel comprises: a photosensitive element, a first node coupled to the photosensitive element, a second node common to all pixels of a same sub-group, and coupled to a first potential, a first transistor coupling the first and second nodes to each other, a second source-follower transistor having a gate connected to the first node, and a third transistor coupling the source of the third transistor to a reading line.
Inventor(s): Christian VERRENGIA CAPOROSSI of Giugliano in Campania (IT) for stmicroelectronics international n.v., Annachiara ESPOSITO of Napoli (IT) for stmicroelectronics international n.v., Paola Sabrina BARBATO of Pozzuoli (IT) for stmicroelectronics international n.v., Valeria CASUSCELLI of Napoli (IT) for stmicroelectronics international n.v., Rossana SCALDAFERRI of Vibonati (IT) for stmicroelectronics international n.v.
IPC Code(s): H10N30/85, C08K3/22, C09D5/24, C09D7/40, C09D7/61, C09D127/16, H04R17/02, H10N30/092
CPC Code(s): H10N30/852
Abstract: composite material comprising a fluoropolymer matrix and a filler formed of nanoparticles of a ceramic of the bzt-�bxt type wherein x is selected from ca, sn, and mn and a is a molar fraction selected in the range between 0.10-0.90 doped with at least one doping element selected from the group consisting of nb, la, mn, nd and w, wherein when x is mn, the doping element is not mn, wherein said nanoparticles have an average diameter comprised between 10 and 25% by weight on the total weight of the composite. the composite material is used to form a thin film usable as a piezoelectric material with inductive properties in electronic components, for example acoustic sensors such as microphones, and energy harvesting transducers.
STMicroelectronics International N.V. patent applications on March 6th, 2025
- STMicroelectronics International N.V.
- A61B5/11
- A61B5/00
- CPC A61B5/1118
- Stmicroelectronics international n.v.
- A61B5/297
- A61B3/113
- A61B5/256
- CPC A61B5/297
- C30B29/36
- C30B25/18
- CPC C30B29/36
- G01C19/5712
- G01C25/00
- CPC G01C19/5712
- G01N27/60
- G01N33/24
- CPC G01N27/605
- G01R31/66
- H02M3/158
- CPC G01R31/66
- G01S7/481
- G01S7/487
- G01S7/493
- G02B5/122
- G02B5/126
- CPC G01S7/4813
- G01S7/4865
- G01S7/4863
- G01S17/10
- G01S17/894
- CPC G01S7/4865
- G05B23/02
- CPC G05B23/024
- G05F3/16
- CPC G05F3/16
- G06F8/33
- G06F40/109
- G06F40/194
- CPC G06F8/33
- G06F21/54
- G06F21/55
- G06F21/85
- CPC G06F21/54
- G11C7/10
- G11C7/12
- CPC G11C7/1087
- G11C13/00
- G06F7/523
- CPC G11C13/003
- CPC G11C13/0069
- H01L23/373
- H01L21/48
- H01L23/00
- H01L23/31
- H01L23/498
- CPC H01L23/3736
- H01L21/56
- CPC H01L24/40
- H02H3/20
- G01R31/74
- CPC H02H3/20
- G09G3/3258
- H02M1/00
- CPC H02M3/1582
- H02M3/157
- H02M1/08
- H03F3/04
- H03F1/56
- CPC H03F3/04
- H03F3/45
- CPC H03F3/45475
- H03K17/081
- CPC H03K17/08104
- H03K17/082
- H03K5/24
- CPC H03K17/082
- H03K21/02
- CPC H03K21/023
- H04L9/00
- H04L9/08
- CPC H04L9/002
- H04L67/12
- G06F9/455
- CPC H04L67/12
- H01L29/66
- H01L29/20
- H01L29/778
- CPC H10D30/015
- H01L29/06
- H01L29/16
- H01L29/872
- CPC H10D62/107
- H01L27/02
- CPC H10D89/814
- H01L27/146
- H04N25/77
- H04N25/78
- CPC H10F39/8037
- H10N30/85
- C08K3/22
- C09D5/24
- C09D7/40
- C09D7/61
- C09D127/16
- H04R17/02
- H10N30/092
- CPC H10N30/852