STMicroelectronics International N.V. patent applications on January 2nd, 2025
Patent Applications by STMicroelectronics International N.V. on January 2nd, 2025
STMicroelectronics International N.V.: 20 patent applications
STMicroelectronics International N.V. has applied for patents in the areas of B81B7/02 (2), G01L9/00 (2), H01L27/02 (2), H02P5/68 (1), H01L21/3213 (1) H01L27/0262 (2), B81B7/02 (1), G06N3/04 (1), H03K3/037 (1), H03D3/009 (1)
With keywords such as: circuit, coupled, voltage, region, configured, substrate, test, device, signal, and control in patent application abstracts.
Patent Applications by STMicroelectronics International N.V.
Inventor(s): Giorgio ALLEGATO of Monza (IT) for stmicroelectronics international n.v., Paolo FERRARI of Gallarate (IT) for stmicroelectronics international n.v., Laura OGGIONI of Milano (IT) for stmicroelectronics international n.v.
IPC Code(s): B81B7/02, B81C3/00, G01C19/5783, G01L9/00
CPC Code(s): B81B7/02
Abstract: described herein is a microelectromechanical sensor device, comprising: a stack of a first die that integrates a pressure-detection structure and a second die that integrates an inertial detection structure, the first die constituting a cap for the inertial detection structure and being bonded to the second die so as to define a hermetic cavity. the first die has a first substrate, having a front surface and a rear surface that is bonded to said second die, a buried cavity being buried and entirely contained in the first substrate and being arranged in a position corresponding to the front surface, from which it is separated by a membrane. in particular, the aforesaid buried cavity is distinct and separate from the hermetic cavity.
Inventor(s): Eric SAUGIER of Froges (FR) for stmicroelectronics international n.v.
IPC Code(s): B81C1/00, B81B7/02
CPC Code(s): B81C1/00063
Abstract: wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer to form a bonded wafer sandwich, and then selectively thinning the silicon substrate wafer and silicon cap wafer. the silicon substrate wafer is thinned first, and an interconnect structure of through-silicon vias is formed within the thinned silicon substrate wafer. the silicon cap wafer is then thinned to expose openings facing an area of the thinned silicon substrate wafer where a photosensitive region is location and facing an area of the thinned silicon substrate wafer where an emitter die is to be installed. after emitter die installation, the openings in the thinned silicon cap wafer are filled with a transparent material. the thinned silicon cap wafer further includes an opaque light barrier to block light transmission between the openings.
Inventor(s): Massimiliano Pesaturo of Torre de' Roveri (IT) for stmicroelectronics international n.v., Marco Omar Ghidoni of Melzo (IT) for stmicroelectronics international n.v., Mikel Azpeitia Urquia of Milano (IT) for stmicroelectronics international n.v.
IPC Code(s): G01L9/00, G01L19/14
CPC Code(s): G01L9/0048
Abstract: an ultra-compact stacked differential pressure sensor is provided, which includes a differential pressure sensor stacked on an asic stacked on a substrate. the differential pressure sensor is connected to the asic by an inner ring and outer ring. the region between the inner ring and outer ring forms an isolation region. the asic may be connected to the substrate with glue. each of the asic and substrate may have a through hole channel and the differential pressure sensor may have a back channel. the differential pressure sensor is exposed to a first pressure on a first side and a second pressure via the differential pressure back channel, the asic channel, and the substrate channel. the differential pressure sensor may generate an electrical signal based on a difference in pressures between the first environment and the second environment.
Inventor(s): Romeo LETOR of Mascalucia (IT) for stmicroelectronics international n.v., Veronica PUNTORIERI of San Giovanni La Punta (IT) for stmicroelectronics international n.v.
IPC Code(s): G01R19/165, G01R31/26, H03K17/082, H03K17/30
CPC Code(s): G01R19/16519
Abstract: a circuit for monitoring an actual threshold voltage value of a mosfet is provided. the circuit includes a current source configured to be coupled to a source terminal of the mosfet and to generate a test current; a voltage generator configured to be coupled between a gate terminal of the mosfet and the source terminal of the mosfet, and to generate a test voltage, said test voltage being lower than a nominal threshold voltage value of the mosfet; a detection unit configured to sample a plurality of voltage value at the source terminal of the mosfet during time, to compute as a function of said plurality of voltage value at least a value of voltage variation over time, in particular over a given time period, of said voltage value at the source terminal of the mosfet, and to provide said computed at least a value of voltage variation to an alarm generation unit; the alarm generation unit being configured to receive said computed voltage variation from the detection unit, to compare said computed voltage variation with a reference voltage, and to raise an alarm if the output of said comparison does not correspond to a predetermined output condition; and a control unit, configured to receive a test mode signal, indicative of an operation mode. the control unit is further configured to, according to said received test mode signal, select the status of coupling or decoupling of said current source to/from the source terminal of the mosfet, determine the value of said reference voltage, set said output condition of said comparison, and signal to the detection unit to perform a plurality of said sampling operation.
Inventor(s): Marco Casarsa of Milano (IT) for stmicroelectronics international n.v.
IPC Code(s): G01R31/28, H03L7/095
CPC Code(s): G01R31/2882
Abstract: a system for testing a circuit includes a phase-locked loop, a test logic circuit, and a test controller. the test logic circuit is coupled to the phase-locked loop. the test logic circuit is configured to count a number of clock cycles of the phase-locked loop using a reference clock as a reference. the reference clock is coupled to the test logic circuit. the test controller is coupled to the phase-locked loop and to the test logic circuit. the test controller is configured to measure a clock frequency of the phase-locked loop with the counted number of clock cycles received from the test logic circuit.
Inventor(s): Filippo Colombo of Monza (IT) for stmicroelectronics international n.v.
IPC Code(s): G01R31/316
CPC Code(s): G01R31/316
Abstract: an integrated circuit includes a test circuit, and an analog delay circuit and a sampler register, each configured to receive a signal. the delay circuit includes a configuration input and phases with a final phase. the sampler register includes result outputs and delay inputs that are each coupled to a respective delay output of the phases. the sampler register is configured to output a sample signal indicating a relationship between the signal and at least the final phase of the phases. the integrated circuit further includes a test circuit that includes a configuration output coupled to the configuration input of the delay circuit, and result inputs coupled to the result outputs of the sampler register. the test circuit is configured to iterate through selected values to test the delay circuit and determine that the delay circuit passes the test when the relationship matches a predetermined criterion.
Inventor(s): Jiri RYBA of Prague (CZ) for stmicroelectronics international n.v., Vittorio D'ANGELO of Nocera Superiore (IT) for stmicroelectronics international n.v., Salvatore CANNAVACCIUOLO of VILLARICCA (IT) for stmicroelectronics international n.v., Mario DI GUARDO of Sant'Agata li Battiati (IT) for stmicroelectronics international n.v., Piero COLETTA of Paupisi (IT) for stmicroelectronics international n.v.
IPC Code(s): G01R31/389, G01R31/3835, G01R31/392, H02J7/00
CPC Code(s): G01R31/389
Abstract: the present disclosure relates to an eis measuring device comprising: an electrical energy storage circuit; an electronic circuit coupled to the electrical energy storage circuit and configured to be coupled to a battery whose impedance is to be measured by the eis measuring device, a characterization circuit configured to measure an alternative current intended to circulate between the battery and the electronic circuit, and a voltage at terminals of the battery; wherein the electronic circuit is alternately configured in a first mode to pull out electrical energy of the battery and storing the electrical energy pulled-out from the battery in the electrical energy storage circuit, and in a second mode to pull out the stored electrical energy from the electrical energy storage circuit and to re-inject the electrical energy pulled-out from the electrical energy storage circuit in the battery.
Inventor(s): Philippe Bienvenu of Saint-Maximin (FR) for stmicroelectronics international n.v., Antonio Calandra of Saint Maximin (FR) for stmicroelectronics international n.v., Julia Castellan of Trets (FR) for stmicroelectronics international n.v.
IPC Code(s): G01R31/40
CPC Code(s): G01R31/40
Abstract: the present disclosure relates to a device for measuring a power current supplied by a main power fet. the device includes a current measurement power fet coupled with the main fet; first and second fets, the gates of which are coupled with each other, the first fet is coupled with the current measurement fet, in which a source/drain terminal of the second fet is coupled with a source/drain terminal of the first fet, or a source/drain terminal of the second fet is coupled with a source/drain terminal of the main fet or to a voltage source or load external to the device, and source/drain terminals of the first and second fets are coupled with each other.
Inventor(s): Jawad BENHAMMADI of Pont de Claix (FR) for stmicroelectronics international n.v.
IPC Code(s): G06F9/4401
CPC Code(s): G06F9/4408
Abstract: the present description concerns a method of selection of boot programs, each contained in two separate storage memories of a microprocessor wherein an option register read first during a resetting of the microprocessor conditions the selection of one of the boot programs.
Inventor(s): Roberto COLOMBO of Munich (DE) for stmicroelectronics international n.v.
IPC Code(s): G06F21/72
CPC Code(s): G06F21/72
Abstract: in accordance with various embodiments of the present disclosure, a processing system is provided. in some embodiments, the processing system comprises a non-secure processing unit and a cryptographic coprocessing unit. the cryptographic coprocessing unit comprises a data interface and a hardware cryptographic engine. the data interface is configured to receive, from the non-secure processing unit, one or more control blocks and one or more data block. the hardware cryptographic engine is configured to process, as a function of a cryptographic key, the one or more control blocks and the one or more data blocks received by the data interface. the data interface is configured to receive a first control block from the non-secure processing unit, latch the received first control block, receive a first data block from the non-secure processing unit and transfer the latched first control block and the received first data block to the hardware cryptographic engine.
20250005319. NEURAL NETWORK SPLITTER_simplified_abstract_(stmicroelectronics international n.v.)
Inventor(s): Danilo Pietro Pau of Sesto San Giovanni (IT) for stmicroelectronics international n.v., Biagio MONTARULI of Ruvo di Puglia (IT) for stmicroelectronics international n.v., Andrea SANTAMARIA of CAMBIAGO (IT) for stmicroelectronics international n.v.
IPC Code(s): G06N3/04, G06N3/10
CPC Code(s): G06N3/04
Abstract: methods, apparatuses, systems, and/or computer program products for using a neural network splitter to split a neural network into slices are provided. a splitter device may receive a neural network. the splitter devices may be connected to one or more other devices. the neural network may be split the neural network into slices to be deployed to the one or more other devices for execution. the neural network splitter may generate and intermediate representation of the neural network. a profiler of the neural network splitter may extract one or more features from the intermediate representation. a classifier may select one or more heuristics of the neural network features. the neural network may then determine one or more slices based on the features, heuristics, and device characteristics of the connected devices. the slices may be generated and deployed to the connected devices for execution.
Inventor(s): Radouane Habhab of Marseille (FR) for stmicroelectronics international n.v., Vincenzo Della Marca of Marseille (FR) for stmicroelectronics international n.v., Nadia Miridi ép Seroschtanoff of Auriol (FR) for stmicroelectronics international n.v., Pascal Masson of Valbonne (FR) for stmicroelectronics international n.v., Franck Melul of Aubagne (FR) for stmicroelectronics international n.v., Madjid Akbal of Trets (FR) for stmicroelectronics international n.v.
IPC Code(s): G11C16/10, H01L29/423, H10B43/27
CPC Code(s): G11C16/10
Abstract: the non-volatile memory device includes memory cells including a control gate vertically buried in a semiconductor substrate doped with a first type of dopant and a dielectric interface able to trap electrical charges covering sides of the control gate facing the semiconductor substrate. the device furthermore includes a vertical implanted region of a second type of dopant opposite to the first type located along the sides of the control gate in the semiconductor substrate.
Inventor(s): Julien LADROUE of Monnaie (FR) for stmicroelectronics international n.v., Mohamed BOUFNICHEL of Monnaie (FR) for stmicroelectronics international n.v.
IPC Code(s): H01L21/3213, H01L21/027, H01L21/3205, H01L23/498
CPC Code(s): H01L21/32139
Abstract: methods, systems, and devices for semiconductor manufacturing are described. a stack of materials may be formed on a semiconductor substrate. the stack of materials may include a first material, a second material, and a third material. a first etching operation may be performed. the first etching operation may remove a first portion of the first material. a second etching operation may be performed. the second etching operation may remove a first portion of the second material. a third etching operation may be performed. the third etching operation may remove a first portion of the third material. a fourth etching operation may be performed. the fourth etching operation may remove a second portion of the second material. a fifth etching operation may be performed. the fifth etching operation may remove a second portion of the first material.
Inventor(s): Leonardo DI BICCARI of Monza (IT) for stmicroelectronics international n.v.
IPC Code(s): H01L27/02
CPC Code(s): H01L27/0262
Abstract: a two terminal semiconductor controlled rectifier (scr) device has an anode terminal coupled to a first node and a cathode terminal coupled to a second node. neither of the cathode gate or anode gate of the scr device are connected to a triggering circuit for controlling turn on of the scr device. the scr device has an avalanche breakdown voltage for turn on, where that avalanche breakdown voltage is set by a breakdown avalanche of a pn junction of the scr device. a circuit path includes a series connected chain of m zener diodes with a blocking diode that are coupled between the first node and the second node. the circuit path has an activation voltage for turn on, where that activation voltage is dependent on n times a zener diode reverse breakdown voltage. the activation voltage is less than the avalanche breakdown voltage.
Inventor(s): Varun KUMAR of Nurmahal (IN) for stmicroelectronics international n.v.
IPC Code(s): H01L27/02, H01L21/8249
CPC Code(s): H01L27/0262
Abstract: the present disclosure is directed to an input/output (i/o) interface that includes a set of complementary metal-oxide semiconductor (cmos) transistors in a p-type substrate. a first n-type region is in the substrate and a second n-type region in the substrate spaced from the first n-type region, the second n-type region being a deep-nwell (dnw). a first heavily doped p-type region is between the first and second n-type regions, the first heavily doped p-type region is coupled to ground. a second heavily doped p-type region in the first n-type region, the second heavily doped p-type region and is coupled to an output terminal. a first heavily doped n-type region is in the first n-type region, the first heavily doped n-type region is coupled to a floating-well (fw) terminal. a second heavily is doped n-type region in the second n-type region. a resistor is coupled to the dnw and the resistor is coupled to a voltage supply terminal.
20250006782. ELECTRONIC DEVICE_simplified_abstract_(stmicroelectronics international n.v.)
Inventor(s): Mohamed BOUFNICHEL of Monnaie (FR) for stmicroelectronics international n.v.
IPC Code(s): H01G4/10
CPC Code(s): H01L28/92
Abstract: the present description concerns an electronic device comprising at least two three-dimensional capacitors, each capacitor being surrounded with a trench comprising a gas pocket.
20250007430. MOTOR CONTROL DEVICE_simplified_abstract_(stmicroelectronics international n.v.)
Inventor(s): Dietmar MENDEN of Unterfoehring (DE) for stmicroelectronics international n.v., Christian BJOERNSEN of Ingolstadt (DE) for stmicroelectronics international n.v.
IPC Code(s): H02P5/68, B60R16/023, H02K11/215, H02P7/03, H02P7/29
CPC Code(s): H02P5/68
Abstract: the present disclosure relates to a motor control device comprising: a motor driver electronic circuit configured to be electrically coupled to at least one motor and to drive the at least one motor; a control electronic circuit electrically coupled to the motor driver electronic circuit, and configured to control the motor driver electronic circuit and to be electrically coupled to a motor position sensor; wherein the control electronic circuit further comprises a can type transceiver configured to directly communicate with at least one main ecu, which is external to the motor control device, using a commander and responder can type communication protocol, the control electronic circuit being configured to act as a responder node during a communication with the main ecu.
Inventor(s): Raffaele Enrico FURCERI of Legnano (IT) for stmicroelectronics international n.v., Marco ZAMPROGNO of Cesano Maderno (MB) (IT) for stmicroelectronics international n.v.
IPC Code(s): H03D3/00, H03D7/16
CPC Code(s): H03D3/009
Abstract: faults in a periodically oscillating mems mass are detected by processing a position signal, having an amplitude and oscillation frequency, generated as a function of mass position. first and second reference signals formed by samples of quadrature sinusoids at the oscillation frequency are generated. first and second multipliers generate a first product signal and a second product signal, respectively, via multiplication of the position signal by the first and second reference signals. the first and second product signals are low pass filtered to generate first and second filtered signals, respectively. an estimator circuit determines estimates of the amplitude as a function of the first and second filtered signals. a decision circuit detects the presence of faults on the basis of a comparison of the estimates with a range of values.
20250007497. ELECTRONIC CIRCUIT_simplified_abstract_(stmicroelectronics international n.v.)
Inventor(s): Stephane DUCREY of Voiron (FR) for stmicroelectronics international n.v., Jean Claude BINI of Tourrettes-sur-loup (FR) for stmicroelectronics international n.v.
IPC Code(s): H03K3/037, G06F1/08, H03K19/20
CPC Code(s): H03K3/037
Abstract: an electronic circuit includes a reference clock signal generator block and functional blocks. in response to a detected failure on a signal originating from a reference frequency generator of the reference clock signal generator block, only the reference frequency generator of the reference clock signal generator block, but not the functional blocks, is reset.
Inventor(s): Stuart McLeod of Edinburgh (GB) for stmicroelectronics international n.v., Andreas Assmann of Edinburgh (GB) for stmicroelectronics international n.v.
IPC Code(s): H04N25/46
CPC Code(s): H04N25/46
Abstract: a method of operating a time-of-flight (tof) ranging system includes: transmitting, by an emitter, a light signal toward one or more targets; receiving, by a tof sensor, the light signal reflected by the one or more targets; generating a histogram based on the received light signal; estimating gradients of histogram bins of the histogram by computing differences between adjacent histogram bins; identifying one or more pulse regions in the histogram; finding, in a pulse region, a rising edge having a gradient that is larger than a pre-determined threshold or is a maximum gradient in the pulse region, where the rising edge is a leftmost rising edge in the pulse region having the gradient; fine-tuning a location of the rising edge; and computing an estimate of a distance of a target in the pulse region by adding a pre-determined offset to a distance of the rising edge.
STMicroelectronics International N.V. patent applications on January 2nd, 2025
- STMicroelectronics International N.V.
- B81B7/02
- B81C3/00
- G01C19/5783
- G01L9/00
- CPC B81B7/02
- Stmicroelectronics international n.v.
- B81C1/00
- CPC B81C1/00063
- G01L19/14
- CPC G01L9/0048
- G01R19/165
- G01R31/26
- H03K17/082
- H03K17/30
- CPC G01R19/16519
- G01R31/28
- H03L7/095
- CPC G01R31/2882
- G01R31/316
- CPC G01R31/316
- G01R31/389
- G01R31/3835
- G01R31/392
- H02J7/00
- CPC G01R31/389
- G01R31/40
- CPC G01R31/40
- G06F9/4401
- CPC G06F9/4408
- G06F21/72
- CPC G06F21/72
- G06N3/04
- G06N3/10
- CPC G06N3/04
- G11C16/10
- H01L29/423
- H10B43/27
- CPC G11C16/10
- H01L21/3213
- H01L21/027
- H01L21/3205
- H01L23/498
- CPC H01L21/32139
- H01L27/02
- CPC H01L27/0262
- H01L21/8249
- H01G4/10
- CPC H01L28/92
- H02P5/68
- B60R16/023
- H02K11/215
- H02P7/03
- H02P7/29
- CPC H02P5/68
- H03D3/00
- H03D7/16
- CPC H03D3/009
- H03K3/037
- G06F1/08
- H03K19/20
- CPC H03K3/037
- H04N25/46
- CPC H04N25/46
