STMicroelectronics International N.V. patent applications on April 3rd, 2025
Patent Applications by STMicroelectronics International N.V. on April 3rd, 2025
STMicroelectronics International N.V.: 23 patent applications
STMicroelectronics International N.V. has applied for patents in the areas of H02M3/158 (3), H02J7/00 (2), H01L23/367 (2), H03K19/20 (2), H02M1/00 (2) G01J1/0214 (1), H01P1/184 (1), H10D10/021 (1), H10D8/051 (1), H03F3/45636 (1)
With keywords such as: circuit, signal, voltage, surface, device, layer, control, transistor, switch, and phase in patent application abstracts.
Patent Applications by STMicroelectronics International N.V.
Inventor(s): Calum RITCHIE of Glasgow GB for stmicroelectronics international n.v., Colin CAMPBELL of Darvel GB for stmicroelectronics international n.v., Matteo FISSORE of Edinburgh GB for stmicroelectronics international n.v.
IPC Code(s): G01J1/02, G01J1/04, G01J1/16, G01S17/08
CPC Code(s): G01J1/0214
Abstract: various embodiments are directed to an optical sensor configured to transmit and receive optical radiation while minimizing optical noise, such as crosstalk. an example optical sensor includes an optical radiation source configured to direct optical radiation at a target object, an optical radiation receiver configured to receive reflected optical radiation off the target object, and a housing cap. the housing cap includes a transmission opening having a lower portion and an upper portion positioned to direct optical radiation toward the target object, and a receiving opening positioned to received reflected optical radiation. a first portion of the upper portion of the transmission opening includes a vertical surface that is substantially parallel to an optical transmission axis. a second portion of the upper portion of the transmission opening comprises an angled surface, progressing into the transmission opening from an outer surface of the housing cap at a transmission opening angle.
Inventor(s): Gaetano Cosentino of Catania IT for stmicroelectronics international n.v.
IPC Code(s): G01R29/08, G01R17/02, G01R19/02
CPC Code(s): G01R29/0878
Abstract: a radiofrequency detector comprises a squarer circuit comprising first and second branches coupled between a voltage supply and ground, the first branch comprising at least a first squarer transistor receiving a rf sinusoidal input voltage, the first squarer transistor being coupled to the voltage supply through a respective load, the second branch comprising a second reference transistor being coupled to the voltage supply through a respective load, an output voltage being formed at an output node of the first branch and a reference voltage being formed at a respective output node coupled to the load of the second branch, a squared voltage being obtained by a difference voltage of the output voltage and reference voltage, wherein the circuit is configured to feed back to a control electrode of the second reference transistor a feedback signal that is a function of the difference voltage.
Inventor(s): Simon GUILLAUMET of Grenoble FR for stmicroelectronics international n.v., Stephanie AUDRAN of Le Touvet FR for stmicroelectronics international n.v., Benjamin VIANNE of Le Cheylas FR for stmicroelectronics international n.v., James Peter Drummond DOWNING of Doune GB for stmicroelectronics international n.v.
IPC Code(s): G02B1/116, B82Y20/00, B82Y40/00, G02B1/00
CPC Code(s): G02B1/116
Abstract: an optical device includes a metasurface formed by a metasurface substrate having at least a first metasurface layer made of a first material and an array of pillars extending through the first metasurface layer. the pillars are made of a second material different from the first material. the metasurface has a first face and a second face opposite the first face. a first anti-reflection stack is positioned over the first face of the metasurface. the first anti-reflection stack has a third face and a fourth face opposite the third face and positioned over the first face of the metasurface. a metal trace has a portion which is exposed at the third face of the first anti-reflection stack.
Inventor(s): Guozhu FENG of Shenzhen CN for stmicroelectronics international n.v., Allan Rio Valentos LAGASCA of Paranaque PH for stmicroelectronics international n.v.
IPC Code(s): G05B19/042, G05B23/02, H05B45/20, H05B45/325
CPC Code(s): G05B19/0423
Abstract: provided is a multi-channel actuator for driving a low-side device. the actuator includes a controller that receives a first command for driving a low-side device and outputs data representative of the first command. the actuator includes a driving circuit having a plurality of detection and driving stages. the plurality of detection and driving stages are operative to be coupled to a plurality of channels of the low-side device, respectively. the driving circuit receives the data representative of the first command and causes a detection and driving stage of the plurality of detection and driving stages to drive a respective channel of the low-side device in accordance with the first command.
Inventor(s): Lorenzo Francesco GUALNIERA of Carugate IT for stmicroelectronics international n.v., Stefano Paolo RIVOLTA of Desio IT for stmicroelectronics international n.v., Piergiorgio ARRIGONI of Domodossola IT for stmicroelectronics international n.v., Marco BIANCO of Cesano Boscone IT for stmicroelectronics international n.v.
IPC Code(s): G06F1/26
CPC Code(s): G06F1/26
Abstract: the present disclosure is directed to routine recognition for adjusting the power state of a device. human activity recognition is performed to detect various activity states, and create a current sequence of activity states. in response to detecting a new activity state, routine comparison is performed in order to compare the current sequence to a past sequence that ended with the user starting to interact with the device. the device is preemptively turned on in response to finding a match.
Inventor(s): Fabrice ROMAIN of Rians FR for stmicroelectronics international n.v.
IPC Code(s): G06F7/533
CPC Code(s): G06F7/5332
Abstract: a digital multiplicand is received. an initial digital multiplier including logical 0s and 1s is also received. the initial multiplier is processed including at the beginning of each string with at least one logical 1 of the initial multiplier, by applying, or not, in a selective manner, a booth encoding on said string so as to output a final multiplier. the multiplicand is then multiplied by the final multiplier to produce an output.
Inventor(s): Alexandre Tramoni of Le Beausset FR for stmicroelectronics international n.v., Remy Ferroul of Trets FR for stmicroelectronics international n.v.
IPC Code(s): G06K7/10, G06K19/07, G06K19/077
CPC Code(s): G06K7/10237
Abstract: the present description relates to a mobile device comprising a near-field communication router and an antenna, coupled to the router via at least one impedance matching circuit between at least two impedance values. a first impedance value is selected to communicate with a near-field communication device of a first type in the presence of a near-field communication device of a second type, and a second impedance value is selected to communicate with a near-field communication device of the first type in the absence of a near-field communication device of the second type. the presence or the absence of a near-field communication device of the second type is determined based on polling frames transmitted by the antenna.
Inventor(s): Antonio Sismundo of Frattamaggiore (Napoli) IT for stmicroelectronics international n.v., Giuliano Filpi of Caserta IT for stmicroelectronics international n.v., Antonio Amoroso of Recale (Caserta) IT for stmicroelectronics international n.v., Massimo Sena of Marigliano IT for stmicroelectronics international n.v.
IPC Code(s): G06K19/077
CPC Code(s): G06K19/07722
Abstract: a dual interface laminated card having a stack of layers includes at least a first core plastic layer, a second core plastic layer disposed over the first core plastic layer, an antenna inlay disposed between the second core plastic layer and first core plastic layer, and a micromodule disposed over the second core plastic layer. the core plastic layers are recycled plastic layers comprising a major percentage, in particular at least 80%, of low surface energy plastic. the laminated card further comprises at least a first layer of polyurethane heat activatable glue, coupled to a side facing the antenna inlay of at least one of the first and second core plastic layers such that the antenna inlay and the at least one core plastic layer are bonded together.
Inventor(s): Sant Swaroop SHRIVASTAVA of Dayalbagh Agra IN for stmicroelectronics international n.v., Hitesh CHAWLA of Noida IN for stmicroelectronics international n.v., Mohd Javed IKHLAS of Delhi IN for stmicroelectronics international n.v., Sachin GULYANI of Noida IN for stmicroelectronics international n.v.
IPC Code(s): G11C11/419, G11C11/412, G11C11/418
CPC Code(s): G11C11/419
Abstract: a memory system includes a memory array with first dummy read cells that discharge a dummy bit line, each of the first dummy read cells including a transistor coupled between the dummy bit line and a first ground node that is connected to a ground reference. second dummy read cells discharge the dummy bit line, each of the dummy read cells including a transistor coupled between the dummy bit line and a second ground node. the dummy read cells cooperate to discharge the dummy bit line in a dummy read operation to provide a self-timing signal. read circuitry retrieves data from a selected row in the memory array during a read operation, in response to the self-timing signal. ground generation circuitry connects the second ground node to the ground reference or allows the second ground to float, based upon a control signal.
Inventor(s): Fabio Enrico Carlo Disegni of Spino d'adda IT for stmicroelectronics international n.v., Cesare Torti of Pavia IT for stmicroelectronics international n.v., Davide Manfré of Pandino (CR) IT for stmicroelectronics international n.v., Massimo Caruso of Messina IT for stmicroelectronics international n.v., Maurizio Francesco Perroni of Messina IT for stmicroelectronics international n.v.
IPC Code(s): G11C16/08, G11C16/10, G11C16/28
CPC Code(s): G11C16/08
Abstract: a row decoder circuit includes an input node receiving a row selection signal and an output node coupled to a memory device word line. a pull-down circuit couples the word line to ground in response to the row selection signal being asserted. a pull-up circuit couples the word line to a supply node in response to a deselection signal being de-asserted. an inverter circuit receives as input a control signal from a control node and produces the deselection signal. a current generator sources a biasing current to the control node. a further pull-down circuit couples the control node to ground in response to the row selection signal being asserted, and comprises a first cascode n-channel transistor, a cascode p-channel transistor, a second cascode n-channel transistor, and at least one selection transistor controlled by the row selection signal, all having their conductive channels arranged in series.
Inventor(s): Roseanne DUCA of Ghaxaq MT for stmicroelectronics international n.v.
IPC Code(s): H01L23/367, H01L21/48
CPC Code(s): H01L23/367
Abstract: at least one package includes a die including a first surface, a second surface opposite to the first surface, and one or more sidewalls transverse to the first surface and the second surface. the one or more sidewalls extend from the first surface to the second surface. a plurality of separate and distinct heat sinks is on the first surface of the die. each respective separate and distinct heat sink of the plurality of separate and distinct heat sinks is separate and distinct from adjacent separate and distinct heat sinks of the plurality of separate and distinct heat sinks. a plurality of channels separates each respective heat sink of the plurality of heat sinks from adjacent heat sinks of the plurality of heat sinks. in some packages, an elastic thermally conductive material is present within and fills the plurality of channels.
Inventor(s): Florian PERMINJAT of Saint Romans FR for stmicroelectronics international n.v., Fabrice DE MORO of Saint Verand FR for stmicroelectronics international n.v.
IPC Code(s): H01L23/367, H01L21/56, H01L23/00, H01L23/31, H01L23/40
CPC Code(s): H01L23/3675
Abstract: an integrated circuit package includes a support substrate with front connection pads on a front surface thereof and rear connection pads on a rear surface thereof. an integrated circuit device is mounted to the support substrate in flip chip orientation with a front face of the integrated circuit device facing the front surface of the support substrate. a thermally conductive heat spreader is mounted adjacent a rear face of the integrated circuit device. external direct thermal paths thermally couple a top surface of the thermally conductive heat spreader to the rear surface of the support substrate. each external direct thermal path includes a first portion on and in direct contact with thermally conductive heat spreader, a second portion on and in direct contact with an external side surface of the support substrate and a third portion on and in direct contact with the rear surface of the support substrate.
Inventor(s): David OUATTARA of Grenoble FR for stmicroelectronics international n.v., Cedric DURAND of La Terrasse FR for stmicroelectronics international n.v., Frederic PAILLARDET of Tresserve FR for stmicroelectronics international n.v.
IPC Code(s): H01P1/18, H03H7/18, H03H11/20
CPC Code(s): H01P1/184
Abstract: various embodiments of the present disclosure provide a phase shifter including a plurality of digital phase shifters, each digital phase shifter of the plurality of the digital phase shifters configured to vary a phase of a phase shifter input signal by a corresponding phase shift value, and a continuous phase shifter configured to vary the phase of the phase shifter input signal with a variable phase shift value. in various embodiments, the continuous phase shifter comprises a continuous phase shifter load configured to receive a control voltage and vary the variable phase shift value using the control voltage.
Inventor(s): Roberto LA ROSA of Viagrande IT for stmicroelectronics international n.v.
IPC Code(s): H02J7/34, H02J7/00
CPC Code(s): H02J7/345
Abstract: disclosed is an energy autonomous system including an energy transducer, a first capacitor, a second capacitor having greater capacitance than the first capacitor, and a microprocessor. the microprocessor includes a first terminal electrically coupled to the energy transducer and the first capacitor; a second terminal electrically coupled to the second capacitor; a switch that is in a conductive state in which the switch electrically couples the first terminal and second terminals together, or a nonconductive state in which the switch does not electrically couple first terminal and second terminals together; a voltage detector that detects a voltage at the first terminal; and a processor coupled to the voltage detector and the switch. the processor controls charging of the second capacitor by controlling the switch to be in the conductive state or the nonconductive state based on the voltage at the first terminal detected by the voltage detector.
Inventor(s): Sandro Rossi of Pavia IT for stmicroelectronics international n.v., Alessandro Saccà of Milan IT for stmicroelectronics international n.v., Niccolò Brambilla of San Donato Milanese IT for stmicroelectronics international n.v., Valeria Bottarel of Novara IT for stmicroelectronics international n.v.
IPC Code(s): H02M1/08, H02M3/157, H02M3/158, H03K17/687, H03K19/20
CPC Code(s): H02M1/08
Abstract: according to an embodiment, a bootstrap drive circuit for driving a bootstrap switch in a dc-dc converter is proposed. the bootstrap drive circuit includes a non-overlapping circuit, a first and a second capacitor, and a first and a second n-channel transistor. the non-overlapping circuit is configured to receive an input signal, the input signal being a function of a pulse width modulated (pwm) signal, wherein the input signal and the pwm signal are characterized by a first logic level, generate a first control signal from the input signal at a first output terminal of the non-overlapping circuit, the first control signal having the first logic level, and generate a second control signal from the input signal at a second output terminal of the non-overlapping circuit, the second control signal being characterized by a second logic level different from the first logic level.
Inventor(s): Claudio Bona of Pieve del Cairo IT for stmicroelectronics international n.v., Kien Beng Tan of Singapore SG for stmicroelectronics international n.v.
IPC Code(s): H02M3/158, H02J7/00, H02M1/00
CPC Code(s): H02M3/158
Abstract: according to an embodiment, a method of operating an m-level buck converter in a battery charging circuit is provided. the m-level buck converter includes 2�n�(m−1) number of transistors. m and n are greater than one. the method includes operating the m-level buck converter in a first mode of the battery charging circuit corresponding to a high-current charge mode. the method further includes operating the m-level buck converter in a second mode of the battery charging circuit corresponding to a low-current charge mode. in the first mode, 2�n�(m−1) number of transistors are switched on and off. in the second mode, 2�(m−1) number of transistors are switched on and off and 2�n�(m−1)−2�(m−1) number of transistors are fully deactivated.
Inventor(s): Alessandro BERTOLINI of Vermiglio IT for stmicroelectronics international n.v., Alessandro GASPARINI of Cusano Milanino IT for stmicroelectronics international n.v.
IPC Code(s): H02M3/158, H02M1/00, H02M1/14
CPC Code(s): H02M3/1582
Abstract: a non-inverting buck boost dc-dc converter operates with a ripple-hysteretic-current-mode-control including: a first state where control signals close a first high side switch and a second low side switch; a second state where control signals close the first high side switch and a second high side switch; a third state where control signals close a first low side switch and the second high side switch; and a fourth state where control signals close the first low side switch and the second low side switch. control signal peak voltage and valley voltage are detected. passing between the first, second, third and fourth states is dependent on peak voltage detection, valley voltage detection, expiration of a variable first time interval following entering the second state, and expiration of a fixed second time interval following entering the third state.
Inventor(s): Harsha ADEMANE of Chicago IL US for stmicroelectronics international n.v., Rosario ATTANASIO of Barrington IL US for stmicroelectronics international n.v., Dino COSTANZO of Catania IT for stmicroelectronics international n.v.
IPC Code(s): H02P1/46, H02P6/182
CPC Code(s): H02P1/46
Abstract: systems, apparatuses, and methods to perform startup step detection in an internal permanent magnet synchronous machine are provided. startup step detection may providing a motor comprising a rotor and stator, wherein the rotor may be positioned in one of six rotor step positions. the startup step detection may include determining which of the six rotor step positions the rotor is in. this may be performed by determining, prior to starting the motor, a sequence of voltage signals while taking current measurements for each voltage signal. the current measurements may be a change in current over time. of the current measurements a largest maximum current measurement may be determined, which may be used to identify the current rotor step position.
Inventor(s): Alessio Emanuele Vergani of Milano IT for stmicroelectronics international n.v., Francesco Piscitelli of Milano IT for stmicroelectronics international n.v., Michele Bartolini of Carpiano IT for stmicroelectronics international n.v.
IPC Code(s): H03F1/02, H03K5/24, H03K19/20
CPC Code(s): H03F1/0233
Abstract: according to an embodiment, an envelope detector circuit for detecting an envelope of a signal from a sensor in a pre-amplifier circuit of a hard disk drive is provided. the circuit includes a half-wave rectifier, a low-pass filter, and a differential full-wave rectifier. the half-wave rectifier receives a differential voltage from the sensor indicating a fly height of the hard disk drive and generates a pair of single-ended output waveforms based on the differential voltage. each pair of single-ended output waveforms has a positive polarity for a half-cycle it passes through. the low-pass filter includes a first and a second low-pass filter. the low-pass filter allows low-frequency signals from the pair of single-ended output waveforms to pass through while attenuating or blocking higher-frequency signals. the differential full-wave rectifier reconstructs a differential signal from the low-pass filter while removing dc rectified components.
Inventor(s): Luv PANDEY of Aligarh IN for stmicroelectronics international n.v.
IPC Code(s): H03F3/45
CPC Code(s): H03F3/45636
Abstract: in accordance with various embodiments of the present disclosure, an amplifier is provided. in some embodiments, the amplifier comprises a first amplifier stage, a second amplifier stage, a common mode sense amplifier stage, a first common mode feedback (cmfb) loop involving the first amplifier stage, the second amplifier stage, and the common mode sense amplifier stage, and a second cmfb loop involving only the first amplifier stage.
Inventor(s): Simone RASCUNA' of Catania IT for stmicroelectronics international n.v., Gabriele BELLOCCHI of Catania IT for stmicroelectronics international n.v., Paolo BADALA' of Acireale (CT) IT for stmicroelectronics international n.v., Marilena VIVONA of Calatafimi Segesta (TP) IT for stmicroelectronics international n.v., Fabrizio ROCCAFORTE of Mascalucia (CT) IT for stmicroelectronics international n.v.
IPC Code(s): H01L29/66, H01L21/04, H01L29/16, H01L29/45, H01L29/47, H01L29/872
CPC Code(s): H10D8/051
Abstract: methods, systems, and apparatuses for one step formation of ohmic contacts and schottky contacts for sic power devices by using laser annealing are provided. an sic power device may include a back-side ohmic contact, a n+ substrate, a n− epitaxial layer, one or more p+ regions, one or more carbon layers, one or more ohmic contacts, and a schottky contact. the one or more ohmic contacts and schottky contact may be formed in a one step operation that may include laser annealing. during manufacturing, a metallization layer applied above the carbon layers and n-epitaxial layer may form the ohmic contacts and schottky contacts when the annealing is performed.
Inventor(s): Edoardo BREZZA of Leuven BE for stmicroelectronics international n.v., Alexis GAUTHIER of Meylan FR for stmicroelectronics international n.v.
IPC Code(s): H01L29/66, H01L21/764, H01L29/06, H01L29/08, H01L29/10, H01L29/737
CPC Code(s): H10D10/021
Abstract: to manufacture a bipolar transistor, a first stack of layers including a first layer made of the material of the base of the bipolar transistor is formed between second and third insulating layers. a first cavity is then formed crossing the first stack in such a way as to reach the substrate. the forming of the first cavity includes an etching of no layer covering the first layer other than the third layer. a first portion of the collector of the bipolar transistor and a second portion of the base of the bipolar transistor are then formed in the first cavity.
20250113701. OPTOELECTRONIC DEVICE_simplified_abstract_(stmicroelectronics international n.v.)
Inventor(s): Arthur ARNAUD of La Tronche FR for stmicroelectronics international n.v.
IPC Code(s): H10K39/00, H10K39/32
CPC Code(s): H10K39/621
Abstract: a device includes an assembly of pixels with a first pixel generating an event-based data element and a second pixel generating a light intensity data element. each first and second pixel includes a portion of a layer that forms a photodiode. a first integrated circuit chip includes a first substrate and a first interconnection network, and a second integrated circuit chip includes a second substrate and a second interconnection network. the first and second integrated circuit chips are attached to each other by the first and second interconnection networks. the layer with the photodiodes is located on a first surface of the second substrate opposite to a second surface of the second substrate having the second interconnection network located thereon.
STMicroelectronics International N.V. patent applications on April 3rd, 2025
- STMicroelectronics International N.V.
- G01J1/02
- G01J1/04
- G01J1/16
- G01S17/08
- CPC G01J1/0214
- Stmicroelectronics international n.v.
- G01R29/08
- G01R17/02
- G01R19/02
- CPC G01R29/0878
- G02B1/116
- B82Y20/00
- B82Y40/00
- G02B1/00
- CPC G02B1/116
- G05B19/042
- G05B23/02
- H05B45/20
- H05B45/325
- CPC G05B19/0423
- G06F1/26
- CPC G06F1/26
- G06F7/533
- CPC G06F7/5332
- G06K7/10
- G06K19/07
- G06K19/077
- CPC G06K7/10237
- CPC G06K19/07722
- G11C11/419
- G11C11/412
- G11C11/418
- CPC G11C11/419
- G11C16/08
- G11C16/10
- G11C16/28
- CPC G11C16/08
- H01L23/367
- H01L21/48
- CPC H01L23/367
- H01L21/56
- H01L23/00
- H01L23/31
- H01L23/40
- CPC H01L23/3675
- H01P1/18
- H03H7/18
- H03H11/20
- CPC H01P1/184
- H02J7/34
- H02J7/00
- CPC H02J7/345
- H02M1/08
- H02M3/157
- H02M3/158
- H03K17/687
- H03K19/20
- CPC H02M1/08
- H02M1/00
- CPC H02M3/158
- H02M1/14
- CPC H02M3/1582
- H02P1/46
- H02P6/182
- CPC H02P1/46
- H03F1/02
- H03K5/24
- CPC H03F1/0233
- H03F3/45
- CPC H03F3/45636
- H01L29/66
- H01L21/04
- H01L29/16
- H01L29/45
- H01L29/47
- H01L29/872
- CPC H10D8/051
- H01L21/764
- H01L29/06
- H01L29/08
- H01L29/10
- H01L29/737
- CPC H10D10/021
- H10K39/00
- H10K39/32
- CPC H10K39/621
