SONY SEMICONDUCTOR SOLUTIONS CORPORATION patent applications on September 26th, 2024
Patent Applications by SONY SEMICONDUCTOR SOLUTIONS CORPORATION on September 26th, 2024
SONY SEMICONDUCTOR SOLUTIONS CORPORATION: 20 patent applications
SONY SEMICONDUCTOR SOLUTIONS CORPORATION has applied for patents in the areas of H01L27/146 (6), H04N25/79 (2), H04N25/616 (2), H04N25/77 (2), B62D6/00 (1) H01L27/14627 (2), B62D6/001 (1), H04L9/3236 (1), H10K50/858 (1), H04N25/768 (1)
With keywords such as: light, unit, conversion, layer, section, photoelectric, circuit, information, device, and processing in patent application abstracts.
Patent Applications by SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Inventor(s): EIJI OBA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): B62D6/00, B60W30/02, B60W50/10, B60W50/14, B60W60/00
CPC Code(s): B62D6/001
Abstract: provided is an information processing device () for performing automatic steering of a traveling body, the information processing device including: an option presentation unit () that presents a plurality of options of steering content in a second section when the traveling body moves from a first section in which automatic steering based on determination by the information processing device is allowed to the second section in which automatic steering based on determination by the information processing device is not allowed; an input unit () that receives, from a passenger of the traveling body, input of the option selected by the passenger's own determination; and a control unit () that performs steering control of the traveling body on the basis of the option that has been received.
Inventor(s): RYOHEI KAZAMA of KANAGAWA (JP) for sony semiconductor solutions corporation, NOBUAKI KAJI of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): G01S7/484, G01S17/58
CPC Code(s): G01S7/484
Abstract: a distance measuring device (a, b) includes a plurality of light sources (a to d), a light source controller (b), a light receiving section (), a distance measurement processing section (b), a prediction section (), and a determination section (). the plurality of light sources (a to d) each have mutually different irradiation regions, and apply light to a target object in the irradiation region. the light source controller (b) controls the plurality of light sources (a to d). the light receiving section () has a light receiving region corresponding to the irradiation region, and receives the reflected light from the target object for each light receiving region. the distance measurement processing section (b) performs distance measurement processing for calculating a distance to the target object based on the reflected light. the prediction section () predicts a motion of the target object within a distance measurement target range. the determination section () determines a light source to be turned on to perform light emission among the plurality of light sources (a to d) based on the predicted motion of the target object.
Inventor(s): TOSHIHISA MIYAKE of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): G01S17/894, G01S7/481, G01S7/4911, G01S7/4915
CPC Code(s): G01S17/894
Abstract: the present technology relates to a signal processing apparatus, a signal processing method, and a program that enable highly accurate distance measurement over a wide range. a signal processing apparatus calculates a distance to a subject on the basis of the amount of electric charge acquired from a light receiving unit that accumulates, as the amount of electric charge, the amount of reflected light received, the reflected light being modulated light reflected off the subject at the time of measuring the distance by use of the modulated light at a predetermined frequency, the modulated light being emitted from a light emitting unit, and on the basis of the predetermined frequency, and generates a distance image, sets a target area targeted for exposure control for measuring a distance by use of modulated light at a second frequency, on the basis of a first distance image generated at the time of measuring a distance by use of modulated light at a first frequency, and calculates the second frequency on the basis of the target area. the present technology can be applied to a distance measuring apparatus that measures distances by use of a sensor.
Inventor(s): Hiromasa DOI of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): G06T17/20, G06T7/50, G06T7/62, G06T7/90
CPC Code(s): G06T17/20
Abstract: the present disclosure relates to an information processing device, an information processing method, and a program that are capable of extending the range of video expression. the information processing device includes a processing unit that performs processing for replacing an area corresponding to a real space with associated contents on the basis of a scan result obtained by a 3d scan of the real space, wherein the processing unit associates the contents with the area corresponding to the real space, on the basis of information about at least one of an object, a shape, a size, a color, and a material in the real space. the present disclosure is applicable to, for example, an electronic device including various sensors.
Inventor(s): Kiyotaka TABUCHI of Kumamoto (JP) for sony semiconductor solutions corporation, Kazunori NAGAHATA of Kumamoto (JP) for sony semiconductor solutions corporation, Yuji MIYATA of Kumamoto (JP) for sony semiconductor solutions corporation, Yuya MIZOKAMI of Kumamoto (JP) for sony semiconductor solutions corporation, Masaharu SHIRATANI of Fukuoka (JP) for sony semiconductor solutions corporation, Kunihiro KAMATAKI of Fukuoka (JP) for sony semiconductor solutions corporation
IPC Code(s): H01J37/32, H01L21/02
CPC Code(s): H01J37/32128
Abstract: provided are a semiconductor device manufacturing method and a film forming apparatus that are capable of improving coverage in a film formation process while suppressing a decrease in productivity. the semiconductor device manufacturing method includes a film formation process of forming a film on a side toward one surface of a substrate disposed in a chamber by using a plasma cvd method. the film formation process changes plasma density in the chamber according to a preset waveform while forming the film.
Inventor(s): KAITO YOKOCHI of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14621
Abstract: the present disclosure relates to a solid-state imaging element, a manufacturing method, and electronic equipment capable of further improving performance. the solid-state imaging element includes a semiconductor substrate having a photoelectric conversion section provided for each pixel and a filter layer provided on a light-receiving side of the semiconductor substrate. in the filter layer, a filter whose surface shape is formed in a convex shape is provided for each pixel, and an inter-pixel light shielding section including a low-refractive index material having the refractive index lower than that of the filter is provided between the pixels. then, the surfaces of the filters are formed in a convex shape by forming the filters on base materials that are provided in a pattern smaller than a pixel pitch by coating such that the filters are convex relative to an insulating film formed on the surface of the semiconductor substrate. the present technology is applicable, for example, to cmos image sensors.
20240321917. IMAGING DEVICE_simplified_abstract_(sony semiconductor solutions corporation)
Inventor(s): KAITO YOKOCHI of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14625
Abstract: an imaging device according to one embodiment of the present disclosure includes a first filter having a first refractive index for entering light, a first photoelectric conversion section that performs photoelectric conversion on light transmitted through the first filter, a second filter that has a second refractive index lower than the first refractive index for entering light and is adjacent to the first filter, a second photoelectric conversion section that performs photoelectric conversion on light transmitted through the second filter, a first medium that is provided on an opposite side of the first photoelectric conversion section as viewed from the first filter and has a third refractive index for entering light, and a second medium that is provided on an opposite side of the second photoelectric conversion section as viewed from the second filter and has a fourth refractive index higher than the third refractive index for entering light.
Inventor(s): MASAYUKI SUZUKI of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14627
Abstract: a solid-state imaging element () according to the present disclosure includes a plurality of photoelectric conversion units, an on-chip lens, a prism portion (p), and a plurality of color splitters cs. the plurality of photoelectric conversion units is disposed side by side in a matrix form in a semiconductor layer (). the on-chip lens is disposed further on a light incident side than the semiconductor layer () to be shared by the plurality of photoelectric conversion units. the prism portion (p) is disposed between the on-chip lens and the plurality of photoelectric conversion units. the plurality of color splitters (cs) are disposed between the prism portion (p) and the plurality of photoelectric conversion units.
Inventor(s): HIRONORI HOSHI of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14627
Abstract: a solid-state imaging element () includes a first photoelectric conversion unit that includes a photoelectric conversion layer () made of an organic material and photoelectrically converts light in a first wavelength region, a second photoelectric conversion unit and a third photoelectric conversion unit that are disposed on an opposite side of a light incident side with respect to the first photoelectric conversion unit and photoelectrically convert light in a second wavelength region and a third wavelength region different from the first wavelength region, and a first color splitter and a second color splitter that are disposed between the first photoelectric conversion unit and the second photoelectric conversion unit and the third photoelectric conversion unit and disperse light transmitted through the first photoelectric conversion unit. the first color splitter makes the light in the second wavelength region incident on the second photoelectric conversion unit near the first color splitter and bends the light in the third wavelength region toward the third photoelectric conversion unit adjacent to the first color splitter, and the second color splitter makes the light in the third wavelength region incident on the third photoelectric conversion unit near the second color splitter and bends the light in the second wavelength region toward the second photoelectric conversion unit adjacent to the second color splitter.
Inventor(s): MASASHI BANDO of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146, H04N25/77, H04N25/79
CPC Code(s): H01L27/14636
Abstract: the present disclosure suppresses a charge-voltage conversion gain decrease due to fd wiring capacitive coupling.
Inventor(s): MASASHI BANDO of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146, H04N25/77, H04N25/79
CPC Code(s): H01L27/14636
Abstract: [solving means] provided is a solid-state imaging device including a photoelectric conversion section, a first transistor, a floating diffusion layer, a second transistor, a conductive layer, and a wiring layer. the photoelectric conversion section photoelectrically converts incident light and accumulates electric charge. the first transistor transfers the electric charge accumulated in the photoelectric conversion section. the floating diffusion layer retains the electric charge transferred by the first transistor. the second transistor amplifies the electric charge retained in the floating diffusion layer. the conductive layer conducts to the floating diffusion layer. the wiring layer causes capacitive coupling with the conductive layer and conducts to a source of the second transistor.
Inventor(s): KATSUJI MATSUMOTO of KANAGAWA (JP) for sony semiconductor solutions corporation, NAOKI KAKOIYAMA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L29/778, H01L23/36, H01L27/085, H01L29/20, H01L29/205, H01L29/66
CPC Code(s): H01L29/7786
Abstract: provided is a semiconductor device () having high heat dissipation and high operation reliability. this semiconductor device includes: a semiconductor substrate (); a first semiconductor layer () that is provided on the semiconductor substrate, has a first aperture (k), and has a first thermal conductivity; a transistor (tr) provided on the first semiconductor layer; and a heat dissipation unit () that is in contact with the semiconductor substrate via the first aperture and has a second thermal conductivity higher than the first thermal conductivity.
20240322765. AMPLIFIER CIRCUIT_simplified_abstract_(sony semiconductor solutions corporation)
Inventor(s): Eiichi NAKAMOTO of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H03F3/183
CPC Code(s): H03F3/183
Abstract: an amplifier circuit of the present disclosure includes: an input circuit that is configured to generate a differential current including a first current and a second current on the basis of an input signal; a first loop filter including a first former-stage integration circuit, a first inverter circuit, and a first latter-stage integration circuit, the first former-stage integration circuit configured to perform an integral action on the basis of the first current and a current corresponding to a first output signal, and the first latter-stage integration circuit that is configured to generate a first signal by receiving an output signal of the first inverter circuit and the first output signal and performing an integral action; a first modulation circuit; a first output circuit; a second loop filter including a second former-stage integration circuit, a second inverter circuit, and a second latter-stage integration circuit, the second former-stage integration circuit that receives the second current and a current corresponding to a second output signal and is configured to perform an integral action, and the second latter-stage integration circuit configured to generate a second signal by performing an integral action on the basis of an output signal of the second inverter circuit and the second output signal; a second modulation circuit; and a second output circuit.
Inventor(s): Toshiki Itagaki of Kanagawa (JP) for sony semiconductor solutions corporation, Nobuo Nakamura of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H04L9/32
CPC Code(s): H04L9/3236
Abstract: detection capability of falsification of data is improved. a hash generation device includes a reference hash information generation unit and a reference hash generation unit. the reference hash information generation unit included in the hash generation device generates a plurality of pieces of reference hash information by a common process according to data, the plurality of pieces of reference hash information being information of a reference hash that is a hash generated from the data and is for use in determination of falsification of the data. the reference hash generation unit included in the hash generation device generates the reference hash on a basis of the generated reference hash information.
Inventor(s): Diederik Paul MOEYS of Stuttgart (DE) for sony semiconductor solutions corporation
IPC Code(s): H04N25/47, H04N25/773, H04N25/79
CPC Code(s): H04N25/47
Abstract: a solid state imaging device comprises a pixel array comprising a plurality of imaging pixels, each of which being capable to detect as a positive polarity event a rise of intensity of light falling on the imaging pixel which rise is larger than a respective first predetermined threshold or as a negative polarity event a fall of the intensity which fall is larger than a respective second predetermined threshold, and a control unit that is configured to receive a time series of the events of both polarities detected in the pixel array, to deduce from the time series of events information on the absolute light intensity received from objects whose movements caused the events, and to reconstruct a time series of images of the objects.
Inventor(s): RYO TAMAKI of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/616, H04N25/709, H04N25/78
CPC Code(s): H04N25/616
Abstract: image quality is improved by a solid-state imaging element that performs exposure at the same time with all pixels. a previous-stage circuit generates a predetermined reset level and a signal level in accordance with the amount of exposure in order and causes each of first and second capacitance elements to hold the predetermined reset level and the signal level. a selection circuit performs control of connecting one of the first and second capacitance elements to a predetermined next stage node, control of disconnecting both the first and second capacitance elements from the next stage node, and control of connecting the other one of the first and second capacitance elements to the next-stage node in order. a next-stage reset transistor initializes a level of the next-stage node when both the first and second capacitance elements are disconnected from the next-stage node. a next-stage circuit reads and outputs the reset level and the signal level from the first and second capacitance elements in order via the next-stage node.
Inventor(s): JUMPEI KAWANO of KANAGAWA (JP) for sony semiconductor solutions corporation, TOSHIAKI NAKANO of KANAGAWA (JP) for sony semiconductor solutions corporation, KIYOSHIGE TSUJI of KANAGAWA (JP) for sony semiconductor solutions corporation, KENICHI HARUYAMA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/63, H01L23/38, H01L27/146, H04N23/52, H04N25/77
CPC Code(s): H04N25/63
Abstract: the present disclosure relates to a solid-state imaging device, a package, and an imaging system capable of curbing degradation of image quality.
Inventor(s): JUMPEI KAWANO of KANAGAWA (JP) for sony semiconductor solutions corporation, TOSHIAKI NAKANO of KANAGAWA (JP) for sony semiconductor solutions corporation, KIYOSHIGE TSUJI of KANAGAWA (JP) for sony semiconductor solutions corporation, KENICHI HARUYAMA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/63, H01L23/38, H01L27/146, H04N23/52, H04N25/77
CPC Code(s): H04N25/63
Abstract: a solid-state imaging device according to an aspect of the present technology includes: a photoelectric conversion unit that is configured by using a material with lower band gap energy than silicon; and a circuit substrate that is joined to the photoelectric conversion unit, in which the circuit substrate includes a pixel signal generation circuit that generates a pixel signal of a voltage value in accordance with a charge generated by the photoelectric conversion unit, a thermometer circuit that detects a temperature of the circuit substrate, and a temperature control signal generation circuit that acquires temperature information indicating the temperature detected by the thermometer circuit and generates a temperature control signal on the basis of the acquired temperature information.
Inventor(s): Yohta Origuchi of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/75, H04N25/51
CPC Code(s): H04N25/75
Abstract: an image processing device of an embodiment according to the present disclosure includes: an obtaining section (b) that sequentially obtains images based on pixel signals respectively for a plurality of pixels which pixel signals are output from a pixel array section including the plurality of pixels; a setting section (c) that assigns the same identification information to the plurality of images having the same imaging condition and assigns different pieces of identification information to the plurality of images having different imaging conditions; and an output section (d) that outputs the plurality of images to which the identification information is assigned.
Inventor(s): TAKAFUMI TAKATSUKA of KANAGAWA (JP) for sony semiconductor solutions corporation, JUN OGI of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/768, H04N25/616
CPC Code(s): H04N25/768
Abstract: an imaging unit according to one aspect of the present disclosure includes a plurality of pixels disposed in a matrix form, and a controller that performs tdi control on the plurality of pixels. each of the pixels includes a light pulse responder and a counter section. the light pulse responder generates a light pulse in response to incidence of light. the counter section includes a rewrite circuit and an adder circuit. the rewrite circuit rewrites an initial value. the adder circuit adds information corresponding to the light pulse to the initial value. the controller causes information held in the counter section to be written as the initial value into the counter section included in the pixel of a next stage in a column direction, and thereafter causes the information corresponding to the light pulse obtained from the light pulse responder to be added to the initial value.
Inventor(s): Yosuke Motoyama of Kanagawa (JP) for sony semiconductor solutions corporation, Reo Asaki of Tokyo (JP) for sony semiconductor solutions corporation
IPC Code(s): H10K50/858, G02F1/1335, G02F1/1362, H10K50/844, H10K59/121, H10K59/30, H10K59/38
CPC Code(s): H10K50/858
Abstract: a light emission element of an embodiment of the present disclosure includes at least: a base; a recessed portion provided at a surface of the base; a first electrode layer formed at least partially along a shape of a top surface of the recessed portion; an organic layer formed on the first electrode layer at least partially along a shape of a top surface of the first electrode layer; a second electrode layer formed on the organic layer along a shape of a top surface of the organic layer; and a planarization layer formed on the second electrode layer, in which light from the organic layer is emitted to an outside via the second electrode layer and the planarization layer.
Inventor(s): MINORU IKARASHI of TOKYO (JP) for sony semiconductor solutions corporation, SEIJI NONOGUCHI of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H10N70/00, H10B63/00, H10N70/20
CPC Code(s): H10N70/882
Abstract: a switch device of one embodiment of the present disclosure includes a first electrode, a second electrode disposed to be opposed to the first electrode, and a switch layer provided between the first electrode and the second electrode and including a first element selected from germanium and silicon, a second element selected from arsenic, phosphorus, and antimony, and a third element selected from selenium and tellurium. the switch layer includes at least one first layer and at least one second layer that are stacked. the first layer includes at least one kind of the second element and at least one kind of the third element, includes the third element in a range of 50 atomic % or more and 80 atomic % or less in composition ratio, and is negative in temperature dependence of a threshold voltage. the second layer includes at least one kind of the first element and at least one kind of the third element, includes the first element in a range of 20 atomic % or more and 50 atomic % or less in composition ratio, and is positive in temperature dependence of the threshold voltage.
SONY SEMICONDUCTOR SOLUTIONS CORPORATION patent applications on September 26th, 2024
- SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- B62D6/00
- B60W30/02
- B60W50/10
- B60W50/14
- B60W60/00
- CPC B62D6/001
- Sony semiconductor solutions corporation
- G01S7/484
- G01S17/58
- CPC G01S7/484
- G01S17/894
- G01S7/481
- G01S7/4911
- G01S7/4915
- CPC G01S17/894
- G06T17/20
- G06T7/50
- G06T7/62
- G06T7/90
- CPC G06T17/20
- H01J37/32
- H01L21/02
- CPC H01J37/32128
- H01L27/146
- CPC H01L27/14621
- CPC H01L27/14625
- CPC H01L27/14627
- H04N25/77
- H04N25/79
- CPC H01L27/14636
- H01L29/778
- H01L23/36
- H01L27/085
- H01L29/20
- H01L29/205
- H01L29/66
- CPC H01L29/7786
- H03F3/183
- CPC H03F3/183
- H04L9/32
- CPC H04L9/3236
- H04N25/47
- H04N25/773
- CPC H04N25/47
- H04N25/616
- H04N25/709
- H04N25/78
- CPC H04N25/616
- H04N25/63
- H01L23/38
- H04N23/52
- CPC H04N25/63
- H04N25/75
- H04N25/51
- CPC H04N25/75
- H04N25/768
- CPC H04N25/768
- H10K50/858
- G02F1/1335
- G02F1/1362
- H10K50/844
- H10K59/121
- H10K59/30
- H10K59/38
- CPC H10K50/858
- H10N70/00
- H10B63/00
- H10N70/20
- CPC H10N70/882
