SONY SEMICONDUCTOR SOLUTIONS CORPORATION patent applications on October 10th, 2024
Patent Applications by SONY SEMICONDUCTOR SOLUTIONS CORPORATION on October 10th, 2024
SONY SEMICONDUCTOR SOLUTIONS CORPORATION: 18 patent applications
SONY SEMICONDUCTOR SOLUTIONS CORPORATION has applied for patents in the areas of H01L27/146 (5), H04N25/78 (2), H04N25/772 (2), H04N25/77 (2), H04N25/79 (2) H01L27/14621 (2), G01S7/4815 (1), H03L7/0814 (1), H04N25/778 (1), H04N25/772 (1)
With keywords such as: light, signal, element, unit, device, photoelectric, conversion, circuit, image, and pixel in patent application abstracts.
Patent Applications by SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Inventor(s): TAKUYA YOKOYAMA of KANAGAWA (JP) for sony semiconductor solutions corporation, SHUNPEI SUZUKI of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): G01S7/481, G01S7/4865, G01S17/931
CPC Code(s): G01S7/4815
Abstract: the light source device includes a light emitting unit, a scanning unit, and a controller. in the light emitting unit, a plurality of light emitting elements is arranged along a first direction. the scanning unit scans light emitted from the plurality of light emitting elements along the second direction orthogonal to the first direction. the controller performs control to make the number of times of light emission of the first light emitting element group included in the plurality of light emitting elements larger than the number of times of light emission of the second light emitting element group not included in the first light emitting element group.
20240337830. DISPLAY APPARATUS_simplified_abstract_(sony semiconductor solutions corporation)
Inventor(s): KAZUMA AIKI of KANAGAWA (JP) for sony semiconductor solutions corporation, SATOSHI IMAI of KANAGAWA (JP) for sony semiconductor solutions corporation, HIROSHI MUKAWA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): G02B27/00, G02B6/42, G02B27/01
CPC Code(s): G02B27/0018
Abstract: to provide a display apparatus capable of preventing unwanted images from being visually recognized by an observer and others. a display apparatus according to the present technology includes: an image light generation apparatus that generates image light; and a light guide plate that guides the image light from the image light generation apparatus to an eyeball, in which the light guide plate includes a light guide plate main body including a light incident surface upon which the image light enters, and an optical surface group including a plurality of optical surfaces that guides the image light via the light incident surface, at least one reflection surface that is provided inside the light guide plate main body and reflects the image light via the optical surface group to a side of the eyeball, and at least one light-shielding portion that is provided in the light guide plate main body and shields a stray light component of the image light. in accordance with a display apparatus according to the present technology, a display apparatus capable of preventing unwanted images from being visually recognized by an observer and other people can be provided.
Inventor(s): YUJI HANADA of KANAGAWA (JP) for sony semiconductor solutions corporation, MASAHIKO NAGUMO of KANAGAWA (JP) for sony semiconductor solutions corporation, KIMIHARU SATO of TOKYO (JP) for sony semiconductor solutions corporation
IPC Code(s): G06T7/90, G06T7/00
CPC Code(s): G06T7/90
Abstract: provided is a color discrimination device capable of accurately discriminating a color of a subject and having excellent robustness and expandability. the color discrimination device includes: an image acquisition unit that acquires two or more types of images among a visible image including a visible light component obtained by imaging a subject, a reflection suppressing image in which a reflected light component is suppressed, and a reflection component image from which the reflected light component is extracted; and a color discrimination unit that discriminates a color of the subject on the basis of the two or more types of images acquired by the image acquisition unit.
Inventor(s): Kazuki Yokoyama of Kanagawa (JP) for sony semiconductor solutions corporation, Takashi Toyoda of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): G09G3/3266, G09G3/3233, G09G3/3275
CPC Code(s): G09G3/3266
Abstract: [problem] the present disclosure provides a display device, an electronic device, and a display control method capable of independently controlling the display of images in a high-resolution region and a low-resolution region.
Inventor(s): Kazuki Yokoyama of Kanagawa (JP) for sony semiconductor solutions corporation, Takashi Toyoda of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): G09G3/3266, G09G3/3233, G09G3/3275
CPC Code(s): G09G3/3266
Abstract: [solution] the present disclosure provides a display device including a pixel section having a plurality of first pixels and a plurality of second pixels, and a driving unit that drives the pixel section. the plurality of first pixels are provided corresponding to respective intersections between a plurality of first scanning lines and a plurality of first data lines. the plurality of second pixels are provided corresponding to respective intersections between a plurality of second scanning lines and a plurality of second data lines. n of the plurality of second pixels (where n is any integer) are provided in a region where m of the plurality of first pixels (where m is any integer) are provided.
Inventor(s): TARO TATSUNO of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): G11C11/16
CPC Code(s): G11C11/1675
Abstract: a semiconductor storage apparatus according to one embodiment of the present disclosure includes a plurality of memory cells and a control circuit. each of the memory cells includes a magnetization reversal memory device and a first switch device that controls a current to flow to the magnetization reversal memory device. the control circuit performs a writing control based on an asymmetric property of a writing error rate curve line with respect to a writing voltage of the magnetization reversal memory device.
Inventor(s): ATSUSHI TODA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14621
Abstract: provided is an optical detector in which the sensitivity can be enhanced, occurrence of crosstalk can be suppressed, and good color reproduction property can be attained. the optical detector includes a photoelectric conversion layer in which a plurality of photoelectric conversion elements that generate electric charges by photoelectric conversion based on incident light are formed in a matrix shape, a filter layer including a plurality of complementary color filters that are arranged on an incident surface of the photoelectric conversion layer in a manner corresponding to the plurality of photoelectric conversion elements and that each block a specific wavelength in the incident light, and a metasurface layer including a plurality of metasurface elements that are arranged between the photoelectric conversion layer and the filter layer in a manner corresponding to the plurality of photoelectric conversion elements and that each include a plurality of refractive index materials varying according to wavelengths and having a pitch smaller than a target light wavelength. each of the plurality of metasurface elements separates, by wavelengths, light having passed through the complementary color filters, into components through the plurality of refractive index materials, and guides the components of the light separated by wavelengths toward the corresponding photoelectric conversion elements.
Inventor(s): Michiko SAKAMOTO of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14621
Abstract: provided is a solid-state imaging device capable of enhancing pixel sensitivity and preventing color mixture. a solid-state imaging device includes: a plurality of microlenses that condenses incident light; a plurality of color filters that transmits light of a specific wavelength included in the condensed incident light; a plurality of photoelectric conversion parts on which light having a specific wavelength transmitted through the color filter is incident; and a plurality of waveguide wall parts arranged between the color filters and surrounding the color filter. then, each of the plurality of waveguide wall parts is formed in a position subjected to pupil correction.
Inventor(s): TAKAHIRO MAYUMI of KANAGAWA (JP) for sony semiconductor solutions corporation, TOSHIAKI ONO of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14634
Abstract: the present disclosure relates to a light detection device and an electronic apparatus that are configured to be able to increase the circuit occupancy area within a substrate. provided is a light detection device including: a first semiconductor substrate that includes a pixel portion in which a plurality of pixels each including a photoelectric conversion element are arranged; a second semiconductor substrate that includes a logic portion including a signal processing circuit required for processing a signal from the pixel portion; and a support substrate in which wiring is formed, the first semiconductor substrate, the second semiconductor substrate, and the support substrate being stacked, wherein electrical connection between wiring in the second semiconductor substrate and the support substrate is performed using a through via, a first through via is formed in the second semiconductor substrate, a second through-via is formed in the support substrate, and the first through via having a diameter smaller than that of the second through-via. the present disclosure can be applied to, for example, solid state imaging devices.
Inventor(s): Kyosuke YAMADA of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146, H04N25/79
CPC Code(s): H01L27/14636
Abstract: the present disclosure relates to a solid-state imaging element, an imaging apparatus, and an electronic device that can reduce the effects caused by a pad electrode being formed. when laminating a logic substrate smaller than an image sensor, a through hole is formed in the image sensor in such a manner as to form a pad electrode in an embedded member embedded around the logic substrate. the present disclosure can be applied to an imaging apparatus.
Inventor(s): Tomohiko KAWAMURA of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14643
Abstract: a transfer speed (pixel driving speed) at which a signal charge photoelectrically converted by a photoelectric conversion unit is transferred to a charge accumulation region is improved. a solid-state imaging device includes: a semiconductor layer having an active region defined by an isolation region on a first surface side; a charge accumulation region in the active region; a photoelectric conversion unit in the semiconductor layer and separated from the charge accumulation region in a depth direction; and a transfer transistor with a gate electrode in an isolation region that transfers a signal charge from the photoelectric conversion unit to the charge accumulation region. the isolation region includes an isolation insulating film on the first surface side of the semiconductor layer, and the gate electrode includes a first portion adjacent to the active region with a gate insulating film interposed therebetween and a second portion adjacent to the isolation insulating film.
Inventor(s): SUGURU KAMADA of KUMAMOTO (JP) for sony semiconductor solutions corporation, KOUJI MORI of KUMAMOTO (JP) for sony semiconductor solutions corporation
IPC Code(s): H01S5/0683, H05B45/12
CPC Code(s): H01S5/0683
Abstract: the present invention stabilizes a control signal for an element that supplies a drive current to a light-emitting element. according to the present invention, a drive device includes a switch element, a current-limiting element, a current-limiting element control unit, and a detection unit. the switch element is connected in series with a light-emitting element and transmits a drive current during a light-emitting period. the current-limiting element is connected in series with the switch element and limits the drive current to a set current value. the current-limiting element control unit generates a current control signal corresponding to the set current value and supplies the current control signal to a control terminal of the current limiting element. the detection unit detects a change in the current control signal during the light-emitting period and causes the current-limiting element control unit to adjust the current control signal.
Inventor(s): Zhong GAO of Delft (NL) for sony semiconductor solutions corporation, Masoud BABAIE of Delft (NL) for sony semiconductor solutions corporation, Martin FRITZ of Stuttgart (DE) for sony semiconductor solutions corporation, Jingchu HE of Delft (NL) for sony semiconductor solutions corporation, Morteza ALAVI of Delft (NL) for sony semiconductor solutions corporation, Bogdan STASZEWSKI of Delft (NL) for sony semiconductor solutions corporation
IPC Code(s): H03L7/081, H03L7/089, H03L7/093
CPC Code(s): H03L7/0814
Abstract: examples relate to a circuit arrangement, a time-mode arithmetic unit circuit arrangement, an all-digital phase-locked loop, and corresponding methods. a circuit arrangement is configured to discard charges from a capacitive circuit element of the circuit arrangement based on a width of one or more signal pulses of an input signal being provided to the circuit arrangement, with the rate at which the charges are discarded being dependent on at least one control signal being provided to the circuit arrangement. the circuit arrangement is configured to provide an output signal flank having a delay relative to a readout signal flank being provided to the circuit arrangement, with the delay being based on the charges stored in the capacitive circuit element at the time the readout signal flank is provided to the circuit arrangement.
Inventor(s): TAKEFUMI NAGUMO of KANAGAWA (JP) for sony semiconductor solutions corporation, TAKUYA KITAMURA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N19/11, H04N19/124, H04N19/182
CPC Code(s): H04N19/11
Abstract: the present disclosure relates to an image processing device and method capable of suppressing a drop in encoding efficiency. one of spatial prediction and phase prediction is set as a prediction method for a pixel to be processed in image data generated by a pixel array in which blocks, each including a plurality of pixels adjacent to each other, are arranged in a predetermined pattern. a prediction value for the pixel to be processed is then derived by applying the prediction method set, and a prediction residual obtained by subtracting the prediction value from each of pixel values in the image data is encoded. the present disclosure can be applied in, for example, an image processing device, an encoding device, a decoding device, an electronic device, an image processing method, a program, or the like.
Inventor(s): Kumiko Mahara of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/40, H04N25/585, H04N25/772
CPC Code(s): H04N25/40
Abstract: [problem] to improve the framerate of hdr compositing.
Inventor(s): Kumiko Mahara of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/40, H04N25/585, H04N25/772
CPC Code(s): H04N25/40
Abstract: [solution] a solid-state imaging device includes a region classification circuit, an exposure time determination circuit, and an exposure control circuit. the region classification circuit divides pixels arranged in an array into each of predetermined regions and classifies each of the predetermined regions obtained by the dividing into a long accumulation region for a long exposure and a short accumulation region for a short exposure. the exposure time determination circuit determines an exposure time of the long accumulation region and an exposure time of the short accumulation region classified. the exposure control circuit controls exposure times of the pixels for each of the predetermined regions based on the exposure times determined.
Inventor(s): Luonghung Asakura of Kanagawa (JP) for sony semiconductor solutions corporation, Yoshiaki Inada of Tokyo (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/77, H04N25/616, H04N25/65, H04N25/78, H04N25/79
CPC Code(s): H04N25/77
Abstract: solid-state imaging elements are disclosed. in one example, an upstream circuit sequentially generates a predetermined reset level and a signal level corresponding to an exposure amount, and causes first and second capacitive elements to hold the reset level and the signal level. a selection circuit sequentially connects one of the capacitive elements to a predetermined downstream node, disconnects both capacitive elements from the downstream node, and connects the other capacitive element to the downstream node. a downstream reset transistor initializes a level of the downstream node when both capacitive elements are disconnected from the downstream node. a downstream circuit sequentially reads the reset level and the signal level from the first and second capacitive elements via the downstream node and outputs the reset level and the signal level.
Inventor(s): Atsumi Niwa of Kanagawa (JP) for sony semiconductor solutions corporation, Yusuke Oike of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/772, H04N25/443, H04N25/445, H04N25/47, H04N25/53, H04N25/707
CPC Code(s): H04N25/772
Abstract: an object is to reduce a circuit scale in a solid-state imaging element that detects an address event. the solid-state imaging element is provided with a plurality of photoelectric conversion elements, a signal supply unit, and a detection unit. in this solid-state imaging element, each of the plurality of photoelectric conversion elements photoelectrically converts incident light to generate a first electric signal. furthermore, in the solid-state imaging element, the detection unit detects whether or not a change amount of the first electric signal of each of the plurality of photoelectric conversion elements exceeds a predetermined threshold and outputs a detection signal indicating a result of the detection result.
20240340554. IMAGING DEVICE_simplified_abstract_(sony semiconductor solutions corporation)
Inventor(s): Kyosuke Ito of Kanagawa (JP) for sony semiconductor solutions corporation, Toshihisa Makihira of Fukuoka (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/778, H04N25/13, H04N25/627, H04N25/704
CPC Code(s): H04N25/778
Abstract: [problem] to provide an imaging device capable of increasing pixel density and changing an imaging magnification.
20240340554. IMAGING DEVICE_simplified_abstract_(sony semiconductor solutions corporation)
Inventor(s): Kyosuke Ito of Kanagawa (JP) for sony semiconductor solutions corporation, Toshihisa Makihira of Fukuoka (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/778, H04N25/13, H04N25/627, H04N25/704
CPC Code(s): H04N25/778
Abstract: [solution] an imaging device includes: a photoelectric converter; a pixel region having a plurality of combinations of transfer transistors having one set of ends connected to the photoelectric converter; a first floating diffusion connected to the other set of ends of the plurality of transfer transistors; a separation transistor having one end connected to the first floating diffusion; a second floating diffusion connected to the other end of the separation transistor; and a reset transistor having one end connected to the other end of the separation transistor and the other end supplied with a predetermined potential. the separation transistor is put into a disconnected state and the reset transistor is put into a connected state.
Inventor(s): KOUJI MATSUURA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/78, H04N25/59, H04N25/77
CPC Code(s): H04N25/78
Abstract: to increase the frame rate and reduce power consumption with a wide dynamic range for photoelectric conversion. an imaging device includes: a first photoelectric conversion unit; a first read-out circuit that outputs to a first signal line a first pixel signal corresponding to charges photoelectrically converted by the first photoelectric conversion unit; a second photoelectric conversion unit that has a smaller light-receiving area than the first photoelectric conversion unit; a second read-out circuit that outputs to a second signal line a second pixel signal corresponding to charges photoelectrically converted by the second photoelectric conversion unit; a pixel signal selector that selects the first pixel signal or the second pixel signal based on a result of comparing the second pixel signal with a reference signal; and an analog-to-digital converter that converts the pixel signal selected by the pixel signal selector into a digital pixel signal by comparing the pixel signal with a reference signal whose potential level changes over time.
SONY SEMICONDUCTOR SOLUTIONS CORPORATION patent applications on October 10th, 2024
- SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- G01S7/481
- G01S7/4865
- G01S17/931
- CPC G01S7/4815
- Sony semiconductor solutions corporation
- G02B27/00
- G02B6/42
- G02B27/01
- CPC G02B27/0018
- G06T7/90
- G06T7/00
- CPC G06T7/90
- G09G3/3266
- G09G3/3233
- G09G3/3275
- CPC G09G3/3266
- G11C11/16
- CPC G11C11/1675
- H01L27/146
- CPC H01L27/14621
- CPC H01L27/14634
- H04N25/79
- CPC H01L27/14636
- CPC H01L27/14643
- H01S5/0683
- H05B45/12
- CPC H01S5/0683
- H03L7/081
- H03L7/089
- H03L7/093
- CPC H03L7/0814
- H04N19/11
- H04N19/124
- H04N19/182
- CPC H04N19/11
- H04N25/40
- H04N25/585
- H04N25/772
- CPC H04N25/40
- H04N25/77
- H04N25/616
- H04N25/65
- H04N25/78
- CPC H04N25/77
- H04N25/443
- H04N25/445
- H04N25/47
- H04N25/53
- H04N25/707
- CPC H04N25/772
- H04N25/778
- H04N25/13
- H04N25/627
- H04N25/704
- CPC H04N25/778
- H04N25/59
- CPC H04N25/78
