SONY SEMICONDUCTOR SOLUTIONS CORPORATION patent applications on January 2nd, 2025
Patent Applications by SONY SEMICONDUCTOR SOLUTIONS CORPORATION on January 2nd, 2025
SONY SEMICONDUCTOR SOLUTIONS CORPORATION: 20 patent applications
SONY SEMICONDUCTOR SOLUTIONS CORPORATION has applied for patents in the areas of H01L27/146 (8), G11C11/16 (2), G11C13/00 (2), H10K71/00 (2), G01S7/4865 (2) H01L27/14614 (2), B60W30/06 (1), H01L27/1463 (1), H10K50/818 (1), H10K50/125 (1)
With keywords such as: light, layer, semiconductor, substrate, element, provided, electrode, region, pixels, and emitting in patent application abstracts.
Patent Applications by SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Inventor(s): YUI NAKAMURA of KANAGAWA (JP) for sony semiconductor solutions corporation, KAZUHIRO YAMANAKA of KANAGAWA (JP) for sony semiconductor solutions corporation, DAI MATSUNAGA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): B60W30/06, G06V10/82, G06V20/58, G08G1/14
CPC Code(s): B60W30/06
Abstract: a learning model is applied to estimate a parking spot definition rectangle (polygon), a parking spot entrance direction, and a vacancy state of a parking spot. a top surface image generated by combining individual images captured by front, rear, left, and right cameras mounted on a vehicle is analyzed, and analysis processing is performed on a parking spot in the image. a parking spot analysis unit uses a learning model to estimate a vertex of a parking spot definition rectangle (polygon) indicating a parking spot region in the image and an entrance direction of the parking spot. furthermore, estimation is performed as to whether the parking spot is a vacant parking spot or an occupied parking spot in which a parked vehicle is present. the parking spot analysis unit uses centernet as a learning model to execute, for example, estimation processing on a spot center and a vertex of a parking spot definition rectangle (polygon).
Inventor(s): Ryutaro Homma of Tokyo (JP) for sony semiconductor solutions corporation, Yasuhiro Shinozuka of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): G01C3/08, G01J1/02, G01J1/42, G01J1/44
CPC Code(s): G01C3/08
Abstract: a photodetection device according to the present disclosure includes: a light-receiving section including a light-receiving element, a first switch, a second switch, and a signal generator, the first switch that couples the light-receiving element to a first node by being turned on, the second switch that applies a predetermined voltage to the first node by being turned on, and the signal generator that generates a pulse signal on the basis of a voltage at the first node; a controller that controls operations of the first switch and the second switch; a detector that detects a timing at which the pulse signal is changed, on the basis of the pulse signal; and an output section that outputs a detection signal corresponding to a detection result by the detector when the second switch is turned on.
20250004111. LIGHT DETECTION ELEMENT_simplified_abstract_(sony semiconductor solutions corporation)
Inventor(s): YASUNORI TSUKUDA of KANAGAWA (JP) for sony semiconductor solutions corporation, KAZUTOSHI TOMITA of KANAGAWA (JP) for sony semiconductor solutions corporation, HIDEKI OZAWA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): G01S7/4865, G01S17/10, G01S17/931
CPC Code(s): G01S7/4865
Abstract: power consumption is reduced. a light detection element () includes: a pixel () including a light receiving element () that receives reflected light obtained by reflecting emission light emitted from a light source device by a target object, and generates a light reception signal based on reception of the reflected light; a reflected light signal generation section () that generates a reflected light signal that is a signal having a predetermined pulse width on the basis of the light reception signal; a time code generation section () that generates a time code that is a time-series code according to an elapsed time from emission of the emission light for each specific cycle; and a time code holding section () that includes a latch circuit (d latch ) that has a data input terminal to which the time code generated is input and an enable terminal to which the reflected light signal is input and holds the time code input, outputs the time code input from an output terminal during a period in which the reflected light signal is input, and holds the time code input when input of the reflected light signal is stopped.
Inventor(s): Salvatore FINATTI of Basingstoke (GB) for sony semiconductor solutions corporation, Antonio AVITABILE of Basingstoke (GB) for sony semiconductor solutions corporation, Michele LAPRESA of Basingstoke (GB) for sony semiconductor solutions corporation
IPC Code(s): G08G1/01, G06V20/10, G08G1/04
CPC Code(s): G08G1/0133
Abstract: described is a method of determining a risk value at a real-world location, the method comprising: receiving data from an image of the location captured by a camera; determining, from the data, the presence of one or more objects in the image; determining a plurality of parameters for each of the objects in the image; and determining the risk value based upon the plurality of parameters.
Inventor(s): LUI SAKAI of KANAGAWA (JP) for sony semiconductor solutions corporation, MASANORI HOSOMI of KANAGAWA (JP) for sony semiconductor solutions corporation, YUTAKA HIGO of KANAGAWA (JP) for sony semiconductor solutions corporation, KEIZO HIRAGA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): G11C11/16, H01F10/32, H10B61/00, H10N50/10, H10N50/85
CPC Code(s): G11C11/161
Abstract: to achieve simplification of writing to magnetoresistive effect memory. the magnetoresistive effect memory includes a magnetoresistive effect element (). the magnetoresistive effect element () provided in the magnetoresistive effect memory includes: a voltage-controlled magnetic anisotropy effect layer (first magnetization free layer ) that is a magnetization free layer having a variable magnetization direction and has a voltage-controlled magnetic anisotropy effect; a non-voltage-controlled magnetic anisotropy effect layer (second magnetization free layer ) that is a magnetization free layer having a variable magnetization direction and has no voltage-controlled magnetic anisotropy effect; and a magnetization fixed layer () that has a magnetic anisotropy and has an invariable magnetization direction.
20250006238. SEMICONDUCTOR CIRCUIT_simplified_abstract_(sony semiconductor solutions corporation)
Inventor(s): DAISHI ISOGAI of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): G11C11/16, G11C5/06, G11C13/00
CPC Code(s): G11C11/1673
Abstract: a semiconductor circuit according to the present disclosure includes first and second memory cells, first and second signal lines, a sense amplifier, a first switch, and a second switch. the sense amplifier includes a latch circuit, a first transistor, a second transistor, and a third transistor. the latch circuit is configured to apply, to a second node, a voltage inverted with respect to a voltage at a first node and apply, to the first node, a voltage inverted with respect to a voltage at the second node. the first transistor includes a source, and includes a gate and a drain that are coupled to the first node. the second transistor includes a source, and includes a gate and a drain that are coupled to the second node. the third transistor includes a source, a gate to which a control voltage is applicable, and a drain coupled to the source of the first transistor, the source of the second transistor, or both. the first switch is configured to couple the first signal line and the first node to each other. the second switch is configured to couple the second signal line and the second node to each other.
Inventor(s): ISAO NARITAKE of KANAGAWA (JP) for sony semiconductor solutions corporation, NOBUYUKI ISHIKAWA of KANAGAWA (JP) for sony semiconductor solutions corporation, YOSHIHIKO KINOSHITA of KANAGAWA (JP) for sony semiconductor solutions corporation, TETSUO MOTOMURA of KANAGAWA (JP) for sony semiconductor solutions corporation, KAZUFUMI IKEDA of KANAGAWA (JP) for sony semiconductor solutions corporation, TSUKASA OJIRO of KANAGAWA (JP) for sony semiconductor solutions corporation, TOMOKO SHIMADA of KANAGAWA (JP) for sony semiconductor solutions corporation, KENICHI NAGAMATSU of KANAGAWA (JP) for sony semiconductor solutions corporation, KOJI WATANABE of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): G11C13/00
CPC Code(s): G11C13/004
Abstract: [problem] to perform more appropriate reading operation.
Inventor(s): ISAO NARITAKE of KANAGAWA (JP) for sony semiconductor solutions corporation, NOBUYUKI ISHIKAWA of KANAGAWA (JP) for sony semiconductor solutions corporation, YOSHIHIKO KINOSHITA of KANAGAWA (JP) for sony semiconductor solutions corporation, TETSUO MOTOMURA of KANAGAWA (JP) for sony semiconductor solutions corporation, KAZUFUMI IKEDA of KANAGAWA (JP) for sony semiconductor solutions corporation, TSUKASA OJIRO of KANAGAWA (JP) for sony semiconductor solutions corporation, TOMOKO SHIMADA of KANAGAWA (JP) for sony semiconductor solutions corporation, KENICHI NAGAMATSU of KANAGAWA (JP) for sony semiconductor solutions corporation, KOJI WATANABE of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): G11C13/00
CPC Code(s): G11C13/004
Abstract: [solution] a semiconductor storage device includes: one or more first memory cells connected in parallel between a first voltage supply line supplying a first voltage and a second voltage supply line supplying a second voltage different from the first voltage; and one or more second memory cells connected in parallel between the second voltage supply line and a third voltage supply line supplying the first voltage, wherein each of the first memory cells includes: a first storage element having a resistance value corresponding to a first status or a second status; and a first cell transistor connected between the first storage element and the first voltage supply line, and each of the second memory cells includes: a second storage element having a resistance value corresponding to a first status or a second status; and a second cell transistor connected between the second storage element and the third voltage supply line.
Inventor(s): YOSHIMITSU NAKASHIMA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14607
Abstract: an imaging device of an embodiment of the present disclosure includes a semiconductor substrate, multiple first pixels, and multiple second pixels. the semiconductor substrate includes a first surface and a second surface that are opposed to each other, and includes a pixel array unit in which multiple unit pixels are arranged in a matrix. the multiple first pixels are each provided in corresponding one of the multiple unit pixels. the multiple second pixels are each provided in corresponding one of the multiple unit pixels and convert a smaller amount of charge per unit time than the multiple first pixels. the multiple second pixels are each disposed in corresponding one of the unit pixels to allow the multiple second pixels to be equal to each other in distance from a center of the pixel array unit, on the basis of respective positions, in the pixel array unit, of the multiple unit pixels in which the respective second pixels are provided, in a planar view.
Inventor(s): AKITO SHIMIZU of KANAGAWA (JP) for sony semiconductor solutions corporation, AKIKO HONJO of KANAGAWA (JP) for sony semiconductor solutions corporation, TOSHIKI HAYASHI of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146, H01L29/423, H01L31/112
CPC Code(s): H01L27/14614
Abstract: to provide a semiconductor device and an imaging apparatus capable of improving performance of a transistor. the semiconductor device includes a semiconductor substrate and a transistor provided on the semiconductor substrate. a gate electrode of the transistor includes a first part disposed at a position opposing the semiconductor substrate via a gate insulating film of the transistor and configured to form a channel on the semiconductor substrate and a second part positioned on top of the first part and configured to have a smaller contribution toward the formation of the channel than the first part. the first part includes a gate end which is positioned on a side of one region of a drain region and a source region of the transistor and in which an electric field concentrates with respect to the one region. the gate end is positioned above or below a surface of the one region via a stepped portion provided on a side of a first surface of the semiconductor substrate and is flush with a side surface of the second part.
Inventor(s): KEN TOMITA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14614
Abstract: an imaging device and a semiconductor device that can reduce the capacitance of a gate electrode are provided. the imaging device includes a photoelectric conversion element and a semiconductor device that reads charge generated by the photoelectric conversion element. the semiconductor device includes a semiconductor substrate and a field-effect transistor provided on the first surface side of the semiconductor substrate. the field-effect transistor includes a gate electrode including a buried gate portion buried from the first surface of the semiconductor substrate toward an inside of the semiconductor substrate, a gate insulating film disposed between the semiconductor substrate and the gate electrode, a source region provided on the semiconductor substrate and connected to one side of the gate electrode in a gate length direction of the gate electrode, and a drain region connected to the other side of the gate electrode in the gate length direction. the buried gate portion includes a first site, and a second site located between at least one of the source region and the drain region and the first region, and having a thickness from the first surface smaller than that of the first region.
Inventor(s): KOSUKE HAREYAMA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14618
Abstract: according to a semiconductor device, it is possible to obtain a favorable heat dissipation property, prevent falling of a material from a side surface of a substrate, and prevent generation of noise such as a flare caused by light reflected from members being present around a semiconductor element. the semiconductor device includes a substrate, a semiconductor element which is electrically connected to the substrate, a connecting member which electrically connects the substrate with the semiconductor element, a support portion which is provided on the substrate and supports a transparent member being located above the semiconductor element with respect to the substrate, a first resin portion provided on the semiconductor element, and a second resin portion which fills a space between the support portion and the first resin portion and covers the connecting member.
Inventor(s): YUMA ONO of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14623
Abstract: the present technology relates to an imaging element and an electronic apparatus that can suppress color mixture. the imaging element includes a first photoelectric converter that generates a charge corresponding to an amount of light, a second photoelectric converter that has a smaller light-receiving area than the first photoelectric converter, and a light-blocking wall provided between adjacent pixels. the light-blocking wall is provided in a shape having a spaced-apart region. the region is a region where light-blocking walls intersect in a case where the light-blocking walls are provided. the light-blocking wall is provided on each side of the first photoelectric converter, one end of the light-blocking wall serves as a region, and the other end is connected to another light-blocking wall. the present technology can be applied to an imaging element that acquires an image having an expanded dynamic range by using large pixels and small pixels.
Inventor(s): Kyohei MIZUTA of Kanagawa (JP) for sony semiconductor solutions corporation, Yoshiki EBIKO of Kanagawa (JP) for sony semiconductor solutions corporation, Yasufumi MIYOSHI of Kanagawa (JP) for sony semiconductor solutions corporation, Kenji TAKEO of Kanagawa (JP) for sony semiconductor solutions corporation, Tokihisa KANEGUCHI of Kanagawa (JP) for sony semiconductor solutions corporation, Hokuto MIKI of Kanagawa (JP) for sony semiconductor solutions corporation, Yoshiki SHIRASU of Kanagawa (JP) for sony semiconductor solutions corporation, Tadamasa SHIOYAMA of Kanagawa (JP) for sony semiconductor solutions corporation, Toshihiko HAYASHI of Kanagawa (JP) for sony semiconductor solutions corporation, Naoyuki SATO of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146, G01S7/4865, G01S17/10
CPC Code(s): H01L27/1463
Abstract: improvement of pixel characteristics is achieved. a light detecting device includes a semiconductor layer and first and second separation areas disposed in the semiconductor layer. the first separation area includes an insulating film that fills a first dug part extending in a thickness direction of the semiconductor layer and of which a refractive index is lower than that of the semiconductor layer, and the second separation area includes a conductive film filling a second dug part extending in the thickness direction of the semiconductor layer.
Inventor(s): Hiroaki ISHIWATA of Kanagawa (JP) for sony semiconductor solutions corporation, Chihiro ARAI of Kanagawa (JP) for sony semiconductor solutions corporation, Hikaru IWATA of Kanagawa (JP) for sony semiconductor solutions corporation, Takaki HATSUI of Saitama (JP) for sony semiconductor solutions corporation, Takahiro KAWAMURA of Kanagawa (JP) for sony semiconductor solutions corporation, Kazunobu OTA of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14636
Abstract: a light-receiving device of an embodiment of the disclosure includes: a semiconductor substrate including a light-receiving region with light-receiving elements arranged two-dimensionally in matrix, and a peripheral region provided therearound; a first first electrically-conductive region provided at an interface of a first surface of the semiconductor substrate for each element and coupled to a first electrode, in the light-receiving region; a second first electrically-conductive region provided around the first first region provided for each element and coupled to a second electrode, at the interface; a third first electrically-conductive region provided around the second first region provided for each element and having electrically floating state, at the interface;
Inventor(s): Hiroaki ISHIWATA of Kanagawa (JP) for sony semiconductor solutions corporation, Chihiro ARAI of Kanagawa (JP) for sony semiconductor solutions corporation, Hikaru IWATA of Kanagawa (JP) for sony semiconductor solutions corporation, Takaki HATSUI of Saitama (JP) for sony semiconductor solutions corporation, Takahiro KAWAMURA of Kanagawa (JP) for sony semiconductor solutions corporation, Kazunobu OTA of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14636
Abstract: a fourth first electrically-conductive region provided at the interface around the light-receiving region and having electrically floating state, in the peripheral region; and a first second electrically-conductive region embeddedly formed in the semiconductor substrate and facing the second, third, and fourth first regions.
Inventor(s): Masaya Ogura of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L33/58, H01L25/075, H01L33/42, H01L33/50, H01L33/62
CPC Code(s): H01L33/58
Abstract: there is provided a light emitting device () including a plurality of pixels () arranged on a substrate, in which a pixel of the plurality of pixels includes a plurality of subpixels (), at least one subpixel of the plurality of subpixels includes a plurality of light emitting elements (), each light emitting element includes: a first electrode () provided on the substrate (); a light emitting layer () that is laminated on the first electrode and emits light; a second electrode () that is laminated on the light emitting layer and transmits light from the light emitting layer; and a first protective film () that is laminated on the second electrode and transmits light from the light emitting layer, and a second protective film () constituting an interface for guiding the light immediately above the light emitting element is embedded between the light emitting elements adjacent.
Inventor(s): MASAYA NAGATA of KANAGAWA (JP) for sony semiconductor solutions corporation, HIROSHI ISOBE of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01S5/02, H01S5/0233, H01S5/0237, H01S5/042, H01S5/183
CPC Code(s): H01S5/0216
Abstract: to prevent peeling of a bonding portion between a first substrate having a light emitting element and a second substrate such as an ldd substrate. a light emitting device includes: a first substrate having a light emitting element; and a second substrate bonded to a surface side opposite to a light emitting surface of the light emitting element, in which the first substrate includes: a first conductive layer laminated on the opposite surface side of the light emitting element; a second conductive layer that is laminated on the first conductive layer and reflects light emitted from the light emitting element to the opposite surface side; a third conductive layer laminated on the second conductive layer and bonded to the second substrate via a bonding member; and an insulating layer laminated on the third conductive layer so as to cover at least end portions of the second conductive layer and the third conductive layer laminated.
Inventor(s): Masahiro JOEI of Kanagawa (JP) for sony semiconductor solutions corporation, Kenichi MURATA of Kanagawa (JP) for sony semiconductor solutions corporation, Shintarou HIRATA of Kanagawa (JP) for sony semiconductor solutions corporation, Toshihiko HAYASHI of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H10K19/20, H01L27/146, H10K30/65, H10K39/32
CPC Code(s): H10K19/20
Abstract: an image pickup element includes a photoelectric conversion section including a first electrode, a photoelectric conversion layer including an organic material, and a second electrode stacked on one another. between the first electrode and the photoelectric conversion layer, an oxide semiconductor layer and an oxide film are formed from the first electrode side.
Inventor(s): Masaaki Sekine of Saitama (JP) for sony semiconductor solutions corporation
IPC Code(s): H10K50/125, H10K50/813
CPC Code(s): H10K50/125
Abstract: a light emitting element (px) according to an aspect of the present disclosure includes a light emitting unit (elp), an intermediate layer (e.g., protection layer ()) that is provided on the light emitting unit (elp), and a color filter layer () that is provided on the intermediate layer (e.g., protection layer ()), and the color filter layer () includes protrusion parts () that protrude toward the intermediate layer (e.g., protection layer ()).
Inventor(s): Shinichi Arakawa of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H10K50/818, H10K50/828, H10K50/856, H10K71/00
CPC Code(s): H10K50/818
Abstract: provided is a display device in which pixels each configured by layering a first electrode, an organic layer, and a second electrode are formed in a two-dimensional matrix arrangement on a substrate; the first electrode is arranged for each pixel and includes a conductive light reflecting film formed on an insulating layer provided on the substrate, and a transparent electrode formed on the light reflecting film; vias conductive with the light reflecting films are formed in portions of the insulating layer positioned under the light reflecting films; and a voltage is applied to the first electrodes through the vias.
Inventor(s): Yu KATO of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H10K59/35, H10K50/844, H10K59/12, H10K59/122, H10K59/80, H10K71/00, H10K102/00
CPC Code(s): H10K59/353
Abstract: an organic el (light-emitting) device is provided that includes at least two subpixels, including a first subpixel and a second subpixel. the first subpixel includes a first electrode, a first organic compound layer with first side surfaces, a first light-emitting layer that emits light of a first color, a second electrode, and a first film covering the first side surfaces with a specified thickness. the second subpixel includes a third electrode, a second organic compound layer with second side surfaces, a second light-emitting layer that emits light of a second color different from the first, a fourth electrode, and a second film covering the second side surfaces with a different thickness from the first film. the first electrode, the first organic compound layer, and the second electrode are stacked in a direction. the first subpixel is spaced apart from the second subpixel on a plane perpendicular to the direction.
SONY SEMICONDUCTOR SOLUTIONS CORPORATION patent applications on January 2nd, 2025
- SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- B60W30/06
- G06V10/82
- G06V20/58
- G08G1/14
- CPC B60W30/06
- Sony semiconductor solutions corporation
- G01C3/08
- G01J1/02
- G01J1/42
- G01J1/44
- CPC G01C3/08
- G01S7/4865
- G01S17/10
- G01S17/931
- CPC G01S7/4865
- G08G1/01
- G06V20/10
- G08G1/04
- CPC G08G1/0133
- G11C11/16
- H01F10/32
- H10B61/00
- H10N50/10
- H10N50/85
- CPC G11C11/161
- G11C5/06
- G11C13/00
- CPC G11C11/1673
- CPC G11C13/004
- H01L27/146
- CPC H01L27/14607
- H01L29/423
- H01L31/112
- CPC H01L27/14614
- CPC H01L27/14618
- CPC H01L27/14623
- CPC H01L27/1463
- CPC H01L27/14636
- H01L33/58
- H01L25/075
- H01L33/42
- H01L33/50
- H01L33/62
- CPC H01L33/58
- H01S5/02
- H01S5/0233
- H01S5/0237
- H01S5/042
- H01S5/183
- CPC H01S5/0216
- H10K19/20
- H10K30/65
- H10K39/32
- CPC H10K19/20
- H10K50/125
- H10K50/813
- CPC H10K50/125
- H10K50/818
- H10K50/828
- H10K50/856
- H10K71/00
- CPC H10K50/818
- H10K59/35
- H10K50/844
- H10K59/12
- H10K59/122
- H10K59/80
- H10K102/00
- CPC H10K59/353
