SONY SEMICONDUCTOR SOLUTIONS CORPORATION patent applications on December 12th, 2024
Patent Applications by SONY SEMICONDUCTOR SOLUTIONS CORPORATION on December 12th, 2024
SONY SEMICONDUCTOR SOLUTIONS CORPORATION: 20 patent applications
SONY SEMICONDUCTOR SOLUTIONS CORPORATION has applied for patents in the areas of H01L27/146 (6), H04N25/78 (4), H04N25/65 (3), H01L31/107 (3), H01S5/042 (2) H04N25/65 (3), H01L27/14636 (2), H01L31/02027 (1), H10N50/10 (1), H10K59/122 (1)
With keywords such as: layer, circuit, surface, substrate, element, unit, semiconductor, light, conversion, and pixels in patent application abstracts.
Patent Applications by SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Inventor(s): YASUNORI TSUKUDA of KANAGAWA (JP) for sony semiconductor solutions corporation, YUKI MORIKAWA of KANAGAWA (JP) for sony semiconductor solutions corporation, KAZUTOSHI TOMITA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): G01S7/4861, G01S7/4865, H01L31/02, H01L31/107, H04N25/773
CPC Code(s): G01S7/4861
Abstract: in a light detection device and a distance measuring system that obtain a distance from a round-trip time of light, a distance measurement error is reduced while a dead time is shortened. a logic gate outputs an output signal on the basis of a result of comparison between an input voltage depending on a voltage of one terminal of the cathode or the anode of an avalanche photodiode and a predetermined threshold voltage. a voltage limiting transistor limits the input voltage. a rapid charging transistor, in which a film thickness of a gate oxide film is less than that of the voltage limiting transistor, supplies a charging current to the avalanche photodiode in accordance with a predetermined pulse signal. a pulse generation unit generates the pulse signal on the basis of the output signal and supplies the pulse signal to the rapid charging transistor.
Inventor(s): Renato FERRACINI ALVES of Stuttgart (DE) for sony semiconductor solutions corporation, Valerio CAMBARERI of Stuttgart (DE) for sony semiconductor solutions corporation
IPC Code(s): G01S17/894, G01S7/497, G01S17/36
CPC Code(s): G01S17/894
Abstract: an electronic device comprising circuitry configured to update a camera configuration based on camera mode feedback information obtained by relating depth information obtained from tof measurements with a reconstructed model of a scene.
Inventor(s): TAKANORI OKAMURA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L23/522, G01S17/10, H01L23/538, H01L25/16, H01L31/107, H01S5/183
CPC Code(s): H01L23/5227
Abstract: provided are a semiconductor device and a distance measuring device capable of reducing parasitic inductance between a plurality of substrates. the semiconductor device of the present disclosure includes: a first substrate including a semiconductor element, a first electrode provided on the semiconductor element, and a second electrode extending in a first direction in plan view; a second substrate including a wiring extending in a second direction parallel to the first direction in plan view, a transistor electrically connected to the wiring, and a capacitor electrically connected to the wiring; a first connection portion electrically connecting the first electrode and the second substrate; and a second connection portion electrically connecting the second electrode and the second substrate.
20240413176. IMAGING DEVICE_simplified_abstract_(sony semiconductor solutions corporation)
Inventor(s): NAOYUKI OSAWA of KANAGAWA (JP) for sony semiconductor solutions corporation, YOSHIMICHI KUMAGAI of KANAGAWA (JP) for sony semiconductor solutions corporation, MASASHI BANDO of KANAGAWA (JP) for sony semiconductor solutions corporation, TORU SHIRAKATA of KANAGAWA (JP) for sony semiconductor solutions corporation, SHUNYA AKIYAMA of KANAGAWA (JP) for sony semiconductor solutions corporation, TAKASHI ABE of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146, H04N25/778, H04N25/78
CPC Code(s): H01L27/14603
Abstract: in order to solve the foregoing problem, the present disclosure provides an imaging device composed of a plurality of pixels, wherein a first pixel among the plurality of pixels includes: a first photoelectric conversion element; a first power storage unit; a first transfer element that enables a conductive state or a non-conductive state between the first photoelectric conversion element and the first power storage unit; and a first amplifying element that amplifies an image signal on the basis of a charge stored by photoelectric conversion in at least any of adjacent pixels, including a second pixel, that are adjacent to the first pixel, the second pixel including: a second amplifying element that amplifies an image signal based on a charge stored in the first power storage unit by photoelectric conversion of the first photoelectric conversion element, and a second distance between the first power storage unit and the second amplifying element is shorter than a first distance between the first power storage unit and the first amplifying element.
20240413179. IMAGING DEVICE_simplified_abstract_(sony semiconductor solutions corporation)
Inventor(s): YUKA OHKUBO of KANAGAWA (JP) for sony semiconductor solutions corporation, KAZUHIRO GOI of KANAGAWA (JP) for sony semiconductor solutions corporation, TAICHI NATORI of KANAGAWA (JP) for sony semiconductor solutions corporation, YUSUKE MORIYA of KANAGAWA (JP) for sony semiconductor solutions corporation, SHINGO TAKAHASHI of KANAGAWA (JP) for sony semiconductor solutions corporation, KEN YAHATA of KANAGAWA (JP) for sony semiconductor solutions corporation, HIROSHI KATO of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146, G02B19/00
CPC Code(s): H01L27/14621
Abstract: an imaging device according to an embodiment of the present disclosure includes: a semiconductor substrate having a first surface and a second surface opposed to each other, the semiconductor substrate including a plurality of pixels disposed in a matrix, and a plurality of photoelectric converters that each generates, through photoelectric conversion, electric charge corresponding to an amount of received light for each of the pixels; a plurality of color filters provided on a side of the first surface in respective ones of the plurality of pixels; a plurality of condensing lenses provided on a light incident side of the plurality of color filters in the respective ones of the plurality of pixels; and a separation wall provided between the plurality of color filters adjacent to each other on the side of the first surface, the separation wall having a line width on the light incident side narrower than the line width of the separation wall on the side of the first surface.
Inventor(s): IPPEI YOSHIBA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14623
Abstract: provided is a solid-state image capturing apparatus that can, between an image height center and positions where the image height becomes higher, align the impact of incident light with respect to light-blocking films. the solid-state image capturing apparatus is provided with a semiconductor substrate in which multiple pixels are disposed in a matrix. each of the multiple pixels is provided with a photoelectric conversion unit that generates charge according to photoelectric conversion based on light incident on a light-receiving surface of the semiconductor substrate, a charge accumulating unit that accumulates the charge generated by the photoelectric conversion unit, a transfer transistor that transfers charge from the photoelectric conversion unit to the charge accumulating unit and has a vertical gate electrode that reaches the photoelectric conversion unit, and a light-blocking section that is formed by a trench disposed within a layer between the light-receiving surface and the charge accumulating unit and blocks light that is incident via the light-receiving surface from being incident on the charge accumulating unit. an amount of cover by the light-blocking section with respect to the charge accumulating unit is corrected according to an image height of a position where the pixel is disposed.
Inventor(s): TOSHIFUMI YASUI of TOKYO (JP) for sony semiconductor solutions corporation, KOUHEI ANJU of TOKYO (JP) for sony semiconductor solutions corporation, YOHTARO YASU of KANAGAWA (JP) for sony semiconductor solutions corporation, YOSHIKI EBIKO of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146, G01S7/481, H01L23/00
CPC Code(s): H01L27/14625
Abstract: a light deflecting device and a distance measuring device in which spread of emission light is suppressed and an effective opening for light reception is enlarged are provided.
Inventor(s): TOSHIFUMI YASUI of TOKYO (JP) for sony semiconductor solutions corporation, KOUHEI ANJU of TOKYO (JP) for sony semiconductor solutions corporation, YOHTARO YASU of KANAGAWA (JP) for sony semiconductor solutions corporation, YOSHIKI EBIKO of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146, G01S7/481, H01L23/00
CPC Code(s): H01L27/14625
Abstract: a light deflecting device including a plurality of waveguides that extends in a first direction in parallel to each other and is provided in a semiconductor layer, and is capable of emitting light to an external space of the semiconductor layer and receiving light from the external space, and an optical system that is provided on a substrate including the semiconductor layer and converts light deflected and emitted from the plurality of waveguides in the first direction into a light beam substantially parallel to a second direction orthogonal to the first direction.
Inventor(s): Tetsuo GOCHO of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146, H01L21/768, H01L23/00
CPC Code(s): H01L27/14636
Abstract: to reduce an impact due to dry etching performed when a via is formed in a substrate. a first base substrate includes first and second semiconductor substrates. a pixel region is formed on the first semiconductor substrate. a logic circuit that processes a pixel signal output from the pixel region is formed on the second semiconductor substrate. the first base substrate includes a first via that passes through a wiring layer of the logic circuit to a back surface of the first base substrate. a second base substrate includes a connection portion and a second via. the connection portion is connected to the first via of the first base substrate on a front surface of the second base substrate. the connection portion and an electrode situated in a lowest surface of the second base substrate are electrically connected to each other through the second via using a conductive material.
20240413187. SEMICONDUCTOR APPARATUS_simplified_abstract_(sony semiconductor solutions corporation)
Inventor(s): Chihiro ARAI of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14636
Abstract: to improve characteristics in a semiconductor apparatus manufactured from a wafer shared in a plurality of manufacturing processes. a semiconductor apparatus includes an opening for a pad, a wiring layer, and a dummy pattern. in the semiconductor apparatus, the opening for a pad is formed on a front surface of a substrate. in addition, in the semiconductor apparatus, a predetermined electrode pad is provided in the opening for a pad. in the semiconductor apparatus, a front surface-side wiring layer is formed in the substrate. in the semiconductor apparatus, a dummy pattern is formed around a dummy non-forming region penetrating up to the front surface-side wiring layer from a rear surface relative to the front surface.
Inventor(s): Dan LUO of Kanagawa (JP) for sony semiconductor solutions corporation, Tatsuki NISHINO of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H01L31/02, G01J1/44, G01S7/4865, H01L31/107
CPC Code(s): H01L31/02027
Abstract: a light detecting device includes first pixel circuitry including a first avalanche photodiode, and second pixel circuitry including a second avalanche photodiode, a first delay circuit including an input coupled to a cathode of the second avalanche photodiode, a first circuit including a first input coupled to the cathode of the second avalanche photodiode, and a second input coupled to an output of the first delay circuit. the light detecting device includes a control circuit coupled to an output of the first circuit and configured to control a potential of an anode of the first avalanche photodiode based on the output of the first circuit. the control circuit is configured to control a potential of an anode of the second avalanche photodiode based on the output of the first circuit.
Inventor(s): Yukihisa IGARASHI of Kumamoto (JP) for sony semiconductor solutions corporation, Takashi SUGIYAMA of Kumamoto (JP) for sony semiconductor solutions corporation, Motoi KIMURA of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H01S5/042, H01S5/42
CPC Code(s): H01S5/04256
Abstract: [object] to provide a light-emitting element array having a wiring structure that enables an increase in response speed of a light-emitting element.
Inventor(s): Yukihisa IGARASHI of Kumamoto (JP) for sony semiconductor solutions corporation, Takashi SUGIYAMA of Kumamoto (JP) for sony semiconductor solutions corporation, Motoi KIMURA of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H01S5/042, H01S5/42
CPC Code(s): H01S5/04256
Abstract: [solving means] a light-emitting element array according to the present technology includes: a light-emitting element group; a first wire; and a second wire. the light-emitting element group forms a light-emitting element surface on which a plurality of light-emitting elements is arranged in a planar shape and includes first light-emitting element columns, first light-emitting elements included in the plurality of light-emitting elements being arranged along a first direction parallel to the light-emitting element surface in each of the first light-emitting element columns. the first wire extends along the first direction and is electrically connected to each of the first light-emitting elements in each of the first light-emitting element columns, a current flowing through the first wire in a first orientation parallel to the first direction. the second wire extends along the first direction and is electrically connected to each of the first light-emitting elements in each of the first light-emitting element columns, a current flowing through the second wire in a second orientation parallel to the first direction and opposite to the first orientation.
Inventor(s): YOSHITERU TACHIKAWA of KUMAMOTO (JP) for sony semiconductor solutions corporation
IPC Code(s): H01S5/183, H01S5/042
CPC Code(s): H01S5/18377
Abstract: provided is a surface emitting laser capable of reducing resistance while suppressing a decrease in reliability. the present technology provides a surface emitting laser including: a first structure including a first multilayer film reflector; a second structure including a second multilayer film reflector; and an active layer disposed between the first and second structures, in which the second structure includes a high-concentration impurity region having a relatively high impurity concentration in at least a part in a thickness direction including a first surface between the first surface, which is a surface on a side opposite to a side of the active layer, and a second surface which is a surface on the side of the active layer, and includes at least one impurity diffusion suppression layer between the first surface and the second surface. according to the present technology, it is possible to provide the surface emitting laser capable of reducing the resistance while suppressing the decrease in reliability.
Inventor(s): Yuki TSUJI of Kanagawa (JP) for sony semiconductor solutions corporation, Ryoji EKI of Kanagawa (JP) for sony semiconductor solutions corporation, Shinichi NAGAO of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H04L9/32, H04L9/08
CPC Code(s): H04L9/3247
Abstract: the present technology is intended to protect a camera system using an imaging device from being abused, the imaging device being configured to perform image processing using an artificial intelligence model.
Inventor(s): Yuki TSUJI of Kanagawa (JP) for sony semiconductor solutions corporation, Ryoji EKI of Kanagawa (JP) for sony semiconductor solutions corporation, Shinichi NAGAO of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H04L9/32, H04L9/08
CPC Code(s): H04L9/3247
Abstract: an information processing device according to the present technology includes a control unit configured to determine whether or not a use state of an imaging device corresponds to a specific use state, the imaging device being configured to perform, using an artificial intelligence model, image processing on a captured image obtained by capturing an image of a subject, and perform, in a case where the use state is determined to correspond to the specific use state, disabling processing of making the imaging device unable to use the artificial intelligence model.
Inventor(s): Ryoto YOSHITA of Kanagawa (JP) for sony semiconductor solutions corporation, Takashi MACHIDA of Kanagawa (JP) for sony semiconductor solutions corporation, Luonghung ASAKURA of Kanagawa (JP) for sony semiconductor solutions corporation, Yoshiaki INADA of Kanagawa (JP) for sony semiconductor solutions corporation, Yoshimichi KUMAGAI of Kanagawa (JP) for sony semiconductor solutions corporation, Toru SHIRAKATA of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/65, H04N25/532, H04N25/57, H04N25/627, H04N25/671, H04N25/771, H04N25/78, H04N25/79
CPC Code(s): H04N25/65
Abstract: in a solid-state imaging element that performs exposure in all pixels at the same time, image quality is improved. a solid-state imaging element includes a previous-stage circuit, a plurality of capacitive elements, a selection circuit, and a subsequent-stage circuit. in the solid-state imaging element, the previous-stage circuit converts charges into a voltage using each of a plurality of conversion efficiencies and outputs it to the previous-stage node. one ends of the plurality of capacitive elements are connected to the previous-stage node in common. the selection circuit connects the other end of one of the plurality of capacitive elements to a subsequent-stage node. the subsequent-stage circuit reads the voltage via the subsequent-stage node.
Inventor(s): RYOTO YOSHITA of KANAGAWA (JP) for sony semiconductor solutions corporation, LUONGHUNG ASAKURA of KANAGAWA (JP) for sony semiconductor solutions corporation, YOSHIAKI INADA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/65, H04N25/532, H04N25/703, H04N25/771, H04N25/78, H04N25/79
CPC Code(s): H04N25/65
Abstract: the present invention improves image quality while preventing a decrease in frame rate in a solid-state imaging element in which all pixels are exposed simultaneously. the solid-state imaging element includes a comparison unit, a pre-stage circuit, a capacitor unit, and a post-stage circuit. the comparison unit compares a signal level corresponding to an exposure amount with a predetermined threshold and outputs a comparison result. the pre-stage circuit converts charges into a voltage at a conversion efficiency selected from among a plurality of different conversion efficiencies on the basis of the comparison result and outputs the voltage. the capacitor unit holds the voltage. the post-stage circuit reads the voltage thus held and outputs the voltage to a vertical signal line.
Inventor(s): LUONGHUNG ASAKURA of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H04N25/65, H04N25/616, H04N25/77, H04N25/78
CPC Code(s): H04N25/65
Abstract: the solid-state imaging element includes a photoelectric conversion film, an upstream circuit, and a sample-hold circuit. the photoelectric conversion film converts incident light into a charge. the upstream circuit sequentially generates a reset level according to an amount of the charge at a time of a start of exposure and a signal level according to an amount of the charge at a time of an end of exposure, and outputs the reset level and the signal level to an upstream node. the sample-hold circuit causes the reset level and the signal level to be held at mutually different capacitive elements.
Inventor(s): Hiroshi Fujimaki of Kanagawa (JP) for sony semiconductor solutions corporation, Hiroshi Nishikawa of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H10K59/122, G09G3/3233, H10K59/80
CPC Code(s): H10K59/122
Abstract: a semiconductor device according to an embodiment includes: a plurality of pixels arrayed in a two-dimensional matrix shape; and a partition wall disposed between the pixels, the partition wall partitioning each of the pixels, in which each of the pixels includes: a first electrode provided on a substrate; an antireflection film provided on at least a part of a peripheral portion of the first electrode; a light emitting layer provided on the first electrode; and a second electrode provided on the light emitting layer.
Inventor(s): YUITO KAGEYAMA of KANAGAWA (JP) for sony semiconductor solutions corporation, YO SATO of KANAGAWA (JP) for sony semiconductor solutions corporation, EIJI KARIYADA of KANAGAWA (JP) for sony semiconductor solutions corporation, MASAKI ENDO of KANAGAWA (JP) for sony semiconductor solutions corporation, MASANORI HOSOMI of KANAGAWA (JP) for sony semiconductor solutions corporation
IPC Code(s): H10N50/10, H01F10/32, H10B61/00, H10N50/85
CPC Code(s): H10N50/10
Abstract: a storage element according to an embodiment includes: a fixed layer that has a fixed magnetization direction; an insulation layer that is disposed on the fixed layer; a storage layer that is disposed on the insulation layer and changes a magnetization direction according to an applied current; and a cap layer that is disposed on the storage layer and made of an oxide, and the cap layer includes a plurality of conductive regions having higher conductivity than conductivity of the oxide.
Inventor(s): Tetsuya Mizuguchi of Kanagawa (JP) for sony semiconductor solutions corporation, Katsuhisa Aratani of Kanagawa (JP) for sony semiconductor solutions corporation, Kazuhiro Ohba of Tokyo (JP) for sony semiconductor solutions corporation, Tetsuo Nakayama of Kanagawa (JP) for sony semiconductor solutions corporation, Hiroaki Sei of Kanagawa (JP) for sony semiconductor solutions corporation
IPC Code(s): H10N70/00, H10B63/00, H10B63/10, H10N70/20
CPC Code(s): H10N70/8616
Abstract: a storage element includes a first electrode, a resistance change layer, a first interface layer, and a first heat shield layer. the resistance change layer is formed on the first electrode, contains at least tellurium, antimony, and germanium, and is changeable in a resistance value. the first interface layer is formed between the first electrode and the resistance change layer. the first heat shield layer is formed between the first electrode and the first interface layer, has electrical conductivity, contains boron, and blocks heat transfer from the resistance change layer.
SONY SEMICONDUCTOR SOLUTIONS CORPORATION patent applications on December 12th, 2024
- SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- G01S7/4861
- G01S7/4865
- H01L31/02
- H01L31/107
- H04N25/773
- CPC G01S7/4861
- Sony semiconductor solutions corporation
- G01S17/894
- G01S7/497
- G01S17/36
- CPC G01S17/894
- H01L23/522
- G01S17/10
- H01L23/538
- H01L25/16
- H01S5/183
- CPC H01L23/5227
- H01L27/146
- H04N25/778
- H04N25/78
- CPC H01L27/14603
- G02B19/00
- CPC H01L27/14621
- CPC H01L27/14623
- G01S7/481
- H01L23/00
- CPC H01L27/14625
- H01L21/768
- CPC H01L27/14636
- G01J1/44
- CPC H01L31/02027
- H01S5/042
- H01S5/42
- CPC H01S5/04256
- CPC H01S5/18377
- H04L9/32
- H04L9/08
- CPC H04L9/3247
- H04N25/65
- H04N25/532
- H04N25/57
- H04N25/627
- H04N25/671
- H04N25/771
- H04N25/79
- CPC H04N25/65
- H04N25/703
- H04N25/616
- H04N25/77
- H10K59/122
- G09G3/3233
- H10K59/80
- CPC H10K59/122
- H10N50/10
- H01F10/32
- H10B61/00
- H10N50/85
- CPC H10N50/10
- H10N70/00
- H10B63/00
- H10B63/10
- H10N70/20
- CPC H10N70/8616
