SK hynix Inc. patent applications on March 20th, 2025
Patent Applications by SK hynix Inc. on March 20th, 2025
SK hynix Inc.: 27 patent applications
SK hynix Inc. has applied for patents in the areas of G11C7/10 (4), G06F3/06 (3), H10B43/27 (3), G11C29/00 (2), H01L23/00 (2) G06F3/0659 (2), G06F1/04 (1), G11C29/52 (1), H10N50/80 (1), H10F39/813 (1)
With keywords such as: memory, data, configured, circuit, device, layer, structure, including, transistor, and voltage in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): Young Ouk KIM of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G06F1/04
CPC Code(s): G06F1/04
Abstract: a duty correction circuit includes a first delay circuit, a second delay circuit, a dividing circuit, a duty detection circuit, and a delay control signal generation circuit. the first delay circuit is configured to delay a clock signal to generate a first delayed clock signal. the second delay circuit is configured to delay the clock signal based on a delay control signal to generate a second delayed clock signal. the dividing circuit is configured to divide the first and second delayed clock signals to generate a first to fourth phase clock signals. the duty detection circuit is configured to detect phases of the first to fourth phase clock signals to generate a duty detection signal. the delay control signal generation circuit generates the delay control signal based on the duty detection signal.
20250094081. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Dong Sop LEE of Icheon-si KR for sk hynix inc.
IPC Code(s): G06F3/06, G06F13/38, G06F13/42
CPC Code(s): G06F3/0658
Abstract: the present disclosure relates to a semiconductor memory device including various types of memories to which a host is connected. the semiconductor memory device in one implementation includes a storage memory comprising a nonvolatile memory and a nonvolatile memory controller configured to control the nonvolatile memory; a main memory comprising a volatile memory and a volatile memory controller configured to control the volatile memory; and an access controller communicatively coupled to the storage memory and the main memory and configured to perform data communication with an external device based on a first protocol, perform data communication with the storage memory based on a second protocol, perform data communication with the main memory based on a third protocol, and control access from the external device to the storage memory and the main memory.
20250094088. DATA STORAGE DEVICE AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Hyun Tae KIM of Icheon-si KR for sk hynix inc., So Yoon JUNG of Icheon-si KR for sk hynix inc.
IPC Code(s): G06F3/06, G06F12/0871, G06F12/0873
CPC Code(s): G06F3/0659
Abstract: a data processing system is provided to include a storage unit and a controller in communication with the storage unit and configured to program write data to a first area as at least one of the plurality of storage areas with a priority over a second area as at least one of the plurality of storage areas and transfer data of the first area to the second area. the controller is further configured to adjust a size of the first area based on 1) a number of times saturated by the write data for the first area, a saturation occurring due to a size of the write data written to the first area being greater than a certain size and 2) an overflow size of the write data corresponding to a difference between the size of the write data and the certain size.
Inventor(s): Hoe Seung JUNG of Icheon-si KR for sk hynix inc., Do Hyung KIM of Icheon-si KR for sk hynix inc., Joo Young LEE of Icheon-si KR for sk hynix inc., Sung Kwan HONG of Icheon-si KR for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a storage device may determine write throughput based on a plurality of write commands received from the outside of the storage device, and write target data write-requested from the outside to a first memory area including one or more of a plurality of first type memory blocks or a second memory area including one or more of a second type memory blocks according to whether the write throughput is greater than or equal to a threshold throughput. the first type memory blocks may operate at a higher speed than the second type memory blocks.
Inventor(s): Choung Ki SONG of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G06F7/544, G06F7/487, G06F7/501, G11C7/10
CPC Code(s): G06F7/5443
Abstract: a processing-in-memory (pim) device includes a first memory region, a second memory region, a third memory region, and a multiplication-and-accumulation mac circuit. the first memory region is configured to store weight data comprised of elements of a weight matrix. the second memory region is configured to store vector data comprised of elements of a vector matrix. the third memory region is configured to store constant data. the mac circuit is configured to selectively perform a mac arithmetic operation of the weight data and the vector data or an element-wise multiplication (ewm) arithmetic operation of the weight data and the constant data.
Inventor(s): You Min JI of Icheon-si KR for sk hynix inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: a memory system is provided to include a memory device including a first memory block and a second memory block, and a memory controller configured, in response to a read request from a host, to control the memory device to read data stored in a first page corresponding to a first logical address included in the read request, update a read count of the first memory block including the first page, and perform a refresh operation of copying data stored in pages of the first memory block to the second memory block based on the read count of the first memory block. the memory controller is further configured to control a priority of the refresh operation on any page based on the number of times logical addresses corresponding to the pages of the first memory block that are received from the host.
Inventor(s): Hoe Seung JUNG of Icheon-si KR for sk hynix inc., Do Hyung KIM of Icheon-si KR for sk hynix inc., Chi Heon KIM of Icheon-si KR for sk hynix inc., Joo Young LEE of Icheon-si KR for sk hynix inc.
IPC Code(s): G06F12/10, G11C16/06
CPC Code(s): G06F12/10
Abstract: a storage device may load, between a first time point at which information on candidate memory regions among a plurality of memory regions is started to be sent to an external device and a second time point at which a command requesting a map segment for a target memory region among the plurality of memory regions is received from the external device, all or a part of map segments corresponding to the candidate memory regions into a buffer.
Inventor(s): Joon Seop SIM of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G06F13/28
CPC Code(s): G06F13/28
Abstract: the present disclosure relates to a computing system. the computing system may include a memory system including a plurality of memory devices configured to store raw data and a near data processor (ndp) configured to receive the raw data by a first bandwidth from the plurality of memory devices and generate intermediate data by performing a first operation on the raw data, and a host device coupled to the memory system by a second bandwidth and determining a resource to perform a second operation on the intermediate data based on a bandwidth ratio and a data size ratio.
Inventor(s): Yuuki ADACHI of Tokyo JP for sk hynix inc.
IPC Code(s): G06T5/20
CPC Code(s): G06T5/20
Abstract: an image signal processor includes a directional component extractor configured to extract directional components of a target kernel by performing a convolution operation between the target kernel including a target pixel and each of a plurality of directional kernels, an interpolation kernel determiner configured to determine an interpolation kernel based on the directional components, and a pixel interpolator configured to interpolate the target pixel using data included in the interpolation kernel.
20250095119. IMAGE PROCESSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Daiki NAKAGAWA of Tokyo JP for sk hynix inc., Kazuhiro YAHATA of Tokyo JP for sk hynix inc.
IPC Code(s): G06T5/70, G06T5/20, G06T5/50
CPC Code(s): G06T5/70
Abstract: an image processing device includes a bit length determiner configured to determine a bit length which indicates a number of at least one bit from among all bits of image data, an upper bit extractor configured to extract, from the image data, at least one upper bit corresponding to the bit length, and a noise processing unit configured to perform noise reduction processing for a target pixel using the at least one upper bit of the image data.
20250095694. MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Jin Ha KIM of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C5/06, G11C16/04, H10B43/10, H10B43/27
CPC Code(s): G11C5/063
Abstract: a memory device, and a method of manufacturing the same, includes interlayer insulation layers spaced apart from each other and stacked, gate lines formed between the interlayer insulation layers, and a plug vertically passing through the interlayer insulation layers and the gate lines. each of the gate lines includes a barrier layer formed along an inner wall of the interlayer insulation layer and the plug, a first conductive layer surrounded by the barrier layer, and a second conductive layer surrounded by the first conductive layer and having a grain size different from a grain size of the first conductive layer. a volume of the second conductive layer is variable along a direction in which the gate lines extend.
Inventor(s): Min Hye KANG of Icheon-si Gyeonggi-do KR for sk hynix inc., Chang Won YANG of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C7/04, G11C7/10, G11C16/30
CPC Code(s): G11C7/04
Abstract: a memory device includes a memory cell array including a plurality of memory cells, a temperature sensor configured to measure an internal temperature and generate a temperature compensation code corresponding to the internal temperature, a voltage control circuit configured to generate a conversion temperature code converted from the temperature compensation code, and a voltage generation circuit configured to output a compensation voltage obtained by compensating for a level of a voltage used in an operation on the memory cell array responsive to the conversion temperature code. the temperature sensor and the voltage control circuit are may be located at different positions responsive to the memory cell array.
Inventor(s): Ji Hyo KANG of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C7/10
CPC Code(s): G11C7/1048
Abstract: a data receiving circuit includes a first inductor, a second inductor, and a t-coil equalization circuit. the first inductor is coupled between a first node coupled with a data input/output pad and a second node. the second inductor is coupled between the second node and an internal circuit. the t-coil equalization circuit includes a t-coil with at least one capacitor coupled with the second node. the t-coil equalization circuit is configured to adjust inductive peaking of the t-coil in response to a control signal.
20250095709. MEMORY WITH ROW HAMMER MITIGATION TECHNIQUE_simplified_abstract_(sk hynix inc.)
Inventor(s): Woongrae KIM of Gyeonggi-do KR for sk hynix inc., Hoiju CHUNG of San Jose CA US for sk hynix inc.
IPC Code(s): G11C11/406, G11C11/4076
CPC Code(s): G11C11/40615
Abstract: a memory includes: a memory core; a list storage circuit suitable for storing a weak row list of rows that are vulnerable to a row hammer attack in the memory core; and a row hammer attack detection circuit suitable for selecting rows that are row-hammer-attacked among rows in the memory core as hammered rows, and increasing a probability that the rows stored in the list storage circuit are selected as the hammered rows.
Inventor(s): Nam Cheol JEON of Icheon-si Gyeonggi-do KR for sk hynix inc., Chang Beom WOO of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C16/14, G11C16/04, G11C16/24
CPC Code(s): G11C16/14
Abstract: an embodiment of the present disclosure relates to a memory device configured to: apply an erase voltage and a first pass voltage at a first time, apply a turn-on voltage at a second time before a level of the erase voltage increases to a target level, maintain the erase voltage, the first pass voltage, and the turn-on voltage at a third time when the level of the erase voltage equals the target level, and reduce a voltage difference between a memory cell and a word line at a fourth time after the third time.
20250095765. ERROR CONDITION MONITORING IN MEMORY SYSTEMS_simplified_abstract_(sk hynix inc.)
Inventor(s): Pengfei HUANG of San Jose CA US for sk hynix inc., Zion KWOK of Burnaby CA for sk hynix inc., Fan ZHANG of San Jose CA US for sk hynix inc.
IPC Code(s): G11C29/52, G11C7/14, G11C29/00
CPC Code(s): G11C29/52
Abstract: this application is directed to data validation in an electronic device having a memory device. the memory device receives an inquiry for a validity condition of a page of the memory device from a memory controller that is coupled to the memory device in a memory system. in response to the inquiry, the memory device selects a subset of the page of the memory device to represent the page. the subset of the page stores a set of memory data. the memory device obtains integrity data corresponding to the set of memory data, applies a plurality of validation operations on the set of memory data and the integrity data corresponding to the set of memory data to generate a plurality of validity results. the memory device determines an error parameter of the page locally based on the plurality of validity results and provides the error parameter to the memory controller.
Inventor(s): Byung Wook BAE of Icheon-si Gyeonggi-do KR for sk hynix inc., Jung Ryul AHN of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C29/54
CPC Code(s): G11C29/54
Abstract: a memory device, and a method of testing the memory device for failure, includes a first chip including a memory cell array and a second chip overlapping with the first chip. the second chip includes: a semiconductor substrate including a peripheral circuit area and a lower test area; a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other; a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.
20250095769. MEMORY AND OPERATION METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Seung Chan KIM of Gyeonggi-do KR for sk hynix inc., Keon Ho LEE of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C29/00, G11C7/10, G11C7/20, G11C29/18, G11C29/44
CPC Code(s): G11C29/76
Abstract: a memory includes: first to nregister circuits each suitable for receiving and storing a failure address transferred from a memory controller when a corresponding selection signal of first to nselection signals is activated, where n is an integer equal to or greater than 2; first to nresource latch circuits suitable for storing first to nresource signals indicating availability of the first to nregister circuits, respectively; and a priority selection circuit suitable for activating, when two or more of the first to nresource signals are activated, one of selection signals respectively corresponding to the activated resource signals among the first to nselection signals.
Inventor(s): Rho Gyu KWAK of Gyeonggi-do KR for sk hynix inc., In Su PARK of Gyeonggi-do KR for sk hynix inc., Jung Shik JANG of Gyeonggi-do KR for sk hynix inc., Seok Min CHOI of Gyeonggi-do KR for sk hynix inc., Won Geun CHOI of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H01L23/00, H01L25/00, H01L25/065, H01L25/18, H10B41/27, H10B43/27, H10B80/00
CPC Code(s): H01L23/562
Abstract: a semiconductor device may include a source structure, a support structure positioned on the source structure and including a first inclined surface extending in a second direction crossing the first direction, a gate structure positioned on the source structure and the support structure and including conductive layers and insulating layers alternately stacked, channel structures extending through the gate structure and connected to the source structure, and a slit structure extending in the first direction through the gate structure, wherein each of the conductive layers includes a second inclined surface extending in the second direction.
Inventor(s): Byung Ho LEE of Gyeonggi-do KR for sk hynix inc., Jin Won PARK of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H01L23/00, H01L25/065
CPC Code(s): H01L24/08
Abstract: a bonding structure may include a non-conductive layer and at least one conductive pad. the non-conductive layer may have a first surface and a second surface opposite to the first surface. the conductive pad may be arranged in the non-conductive pad. the conductive pad may include a vertical pattern portion and at least one volume compensation portion. the vertical pattern portion may extend from the first surface to the second surface in the non-conductive layer. the volume compensation portion may be formed on a sidewall of the vertical pattern portion.
Inventor(s): Gyu Nam KIM of Icheon-si KR for sk hynix inc.
IPC Code(s): H02H9/04, H03K17/687
CPC Code(s): H02H9/046
Abstract: a power clamp circuit includes an electro-static discharge (esd) current discharge circuit including a first mos transistor, a second mos transistor, and a third mos transistor that are coupled in series between a first power rail coupled to a supply voltage and a second power rail coupled to a ground voltage, a first triggering circuit including a first resistor, a first capacitor, and a fourth mos transistor and configured to trigger the first mos transistor, a second triggering circuit including a second resistor, a second capacitor, and a fifth mos transistor and configured to trigger the second mos transistor, and a third triggering circuit including a third resistor and a third capacitor, and configured to turn off the third mos transistor during a normal operation and turn on the third mos transistor when an esd event occurs.
20250098161. MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Yun Cheol HAN of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B43/20, H01L21/027, H10B43/40
CPC Code(s): H10B43/20
Abstract: provided herein is a method of manufacturing a memory device. the method may include forming an ion implantation region in a portion of an outer portion of an underlying structure by implanting ions into the underlying structure, transforming the ion implantation region into an etch stop pattern, forming a target structure on the underlying structure including the etch stop pattern, and performing an etching process to form first holes and second holes in the target structure, wherein the first width of the first holes is different than the second width of the second holes. the etching process is performed until the etch stop pattern is exposed through the first holes and the second holes.
Inventor(s): Jae Young OH of Icheon-si Gyeonggi-do KR for sk hynix inc., Dong Hwan LEE of Icheon-si Gyeonggi-do KR for sk hynix inc., Eun Seok CHOI of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/27, H10B41/30, H10B43/30
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device, and a method of manufacturing the same, includes a gate stack including an interlayer insulating layers and conductive patterns alternately stacked in a vertical direction on a substrate, a channel structure passing through the gate stack and having an upper end protruding above the gate stack, a memory layer surrounding a sidewall of the channel structure, and a source layer formed on the gate stack. the channel structure includes a core insulating layer extending in a central region of the channel structure in the vertical direction, and a channel layer surrounding a sidewall of the core insulating layer, the channel layer formed to be lower in the vertical direction than the core insulating layer and the memory layer.
Inventor(s): Gyu Nam KIM of Icheon-si KR for sk hynix inc.
IPC Code(s): H01L27/02
CPC Code(s): H10D89/819
Abstract: a power clamp circuit includes an electro-static discharge (esd) current discharge circuit including a first mos transistor, a second mos transistor, and a third mos transistor that are coupled in series between a first power rail coupled to a supply voltage and a second power rail coupled to a ground voltage, a first triggering circuit including a first resistor, a first capacitor, and a fourth mos transistor and configured to trigger the first mos transistor, a second triggering circuit including a second resistor, a second capacitor, and a fifth mos transistor and configured to trigger the second mos transistor, and a third triggering circuit configured to turn off the third mos transistor during a normal operation and turn on the third mos transistor when an esd event occurs.
Inventor(s): Young Gyu YOU of Icheon-si KR for sk hynix inc., Dong Joo YANG of Icheon-si KR for sk hynix inc.
IPC Code(s): H01L27/146, H04N25/77
CPC Code(s): H10F39/813
Abstract: an image sensing device including a source follower transistor is disclosed. the image sensing device includes first and second photoelectric conversion elements that supported by the semiconductor substrate and are spaced apart from each other, a first pixel isolation structure recessed from the second surface and configured to surround the first and second photoelectric conversion elements; second and third pixel isolation structures disposed between the first photoelectric conversion element and the second photoelectric conversion element and spaced apart from each other; and a source follower transistor supported by the semiconductor substrate and configured to include a gate disposed on the second surface in at least a portion of a gap region between the second pixel isolation structure and the third pixel isolation structure.
Inventor(s): Cha Deok DONG of Icheon-si KR for sk hynix inc.
IPC Code(s): H10N50/80, H10B61/00, H10N50/01, H10N50/10
CPC Code(s): H10N50/80
Abstract: semiconductor devices and methods for fabricating semiconductor memory devices are disclosed. in an embodiment, a semiconductor device includes: a selector pattern configured to exhibit a threshold switching behavior; an insulating layer structured to a sidewall of the selector pattern and include an opening disposed within the insulating layer over the selector pattern; and an electrode formed in the opening to a thickness that blocks an entrance of the opening and does not completely fill the opening.
20250098554. SEMICONDUCTOR DEVICE INCLUDING SELECTOR_simplified_abstract_(sk hynix inc.)
Inventor(s): Tae Jung HA of Icheon-si KR for sk hynix inc.
IPC Code(s): H10N70/00, H10B63/00
CPC Code(s): H10N70/043
Abstract: a semiconductor device includes: a selector pattern including an insulating material having dopants implanted to the insulating material along an implantation direction and having a first sidewall and a second sidewall facing the first sidewall, the selector pattern configured to exhibit different electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage; and a first electrode layer and a second electrode layer respectively formed over the first sidewall and the second sidewall of the selector pattern, wherein the implantation direction of the dopants is different from a direction of a current flowing through the selector pattern between the first electrode layer and the second electrode layer when the selector pattern is turned on.
- SK hynix Inc.
- G06F1/04
- CPC G06F1/04
- Sk hynix inc.
- G06F3/06
- G06F13/38
- G06F13/42
- CPC G06F3/0658
- G06F12/0871
- G06F12/0873
- CPC G06F3/0659
- G06F7/544
- G06F7/487
- G06F7/501
- G11C7/10
- CPC G06F7/5443
- G06F12/02
- CPC G06F12/0246
- G06F12/10
- G11C16/06
- CPC G06F12/10
- G06F13/28
- CPC G06F13/28
- G06T5/20
- CPC G06T5/20
- G06T5/70
- G06T5/50
- CPC G06T5/70
- G11C5/06
- G11C16/04
- H10B43/10
- H10B43/27
- CPC G11C5/063
- G11C7/04
- G11C16/30
- CPC G11C7/04
- CPC G11C7/1048
- G11C11/406
- G11C11/4076
- CPC G11C11/40615
- G11C16/14
- G11C16/24
- CPC G11C16/14
- G11C29/52
- G11C7/14
- G11C29/00
- CPC G11C29/52
- G11C29/54
- CPC G11C29/54
- G11C7/20
- G11C29/18
- G11C29/44
- CPC G11C29/76
- H01L23/00
- H01L25/00
- H01L25/065
- H01L25/18
- H10B41/27
- H10B80/00
- CPC H01L23/562
- CPC H01L24/08
- H02H9/04
- H03K17/687
- CPC H02H9/046
- H10B43/20
- H01L21/027
- H10B43/40
- CPC H10B43/20
- H10B41/30
- H10B43/30
- CPC H10B43/27
- H01L27/02
- CPC H10D89/819
- H01L27/146
- H04N25/77
- CPC H10F39/813
- H10N50/80
- H10B61/00
- H10N50/01
- H10N50/10
- CPC H10N50/80
- H10N70/00
- H10B63/00
- CPC H10N70/043