SK hynix Inc. patent applications on January 30th, 2025
Patent Applications by SK hynix Inc. on January 30th, 2025
SK hynix Inc.: 24 patent applications
SK hynix Inc. has applied for patents in the areas of H10B43/27 (5), H10B12/00 (4), G06F3/06 (3), H10B41/27 (3), H10B43/10 (3) H10B43/27 (3), G11C16/3459 (2), H10B12/03 (2), H01L23/5386 (1), H10B41/27 (1)
With keywords such as: layer, memory, device, semiconductor, configured, including, information, voltage, insulating, and chip in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): Jeong Ho JEON of Icheon-si (KR) for sk hynix inc., Seok Ho SEO of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0634
Abstract: a memory module may include a first storage device, and a second storage device configured to receive information about a first temperature indicating an internal temperature of the first storage device and to change a threshold temperature from a first threshold temperature to a second threshold temperature different from the first threshold temperature based on the information, to enter a mode in which an internal temperature of the second storage device is controlled when the temperature of the second storage device is higher than the threshold temperature.
Inventor(s): Soon Hyun KWON of Icheon-si (KR) for sk hynix inc., Jin Sub KIM of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: a storage device comprises a nonvolatile memory including a plurality of memory blocks, and a controller configured to control an operation of the nonvolatile memory, generate a mapping table that maps physical addresses and logical addresses for the plurality of memory blocks in a test mode, and set a fake block bitmap indicating whether each of the plurality of memory blocks included in the mapping table is a fake block to which data is not written.
20250036301. MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): In Jong JANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: provided herein are a memory controller and a method of operating the same. the memory controller may include a background condition storage and a background controller. the background condition storage may be configured to store a trigger condition for each background operation for a memory device in each of a non-charging mode and a charging mode associated with a battery for the memory controller. the background controller may be configured to change the trigger condition from a non-charging condition to a charging condition depending on charging information indicating whether the battery for the memory controller is in a charging state. the trigger condition is mitigated in the charging condition compared to the non-charging condition.
Inventor(s): Fan ZHANG of San Jose CA (US) for sk hynix inc., Hongwei DUAN of San Jose CA (US) for sk hynix inc., Haobo WANG of San Jose CA (US) for sk hynix inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: a scheme for encoding and decoding a codeword into which address information is embedded. a write operation for this scheme includes generating tagging information including address information; encoding user information, meta information, the tagging information and additional shortened bits to generate parity information; generating a codeword including the user information, the meta information and the parity information; and storing the codeword in a memory device.
Inventor(s): Jung Hyun KWON of Gyeonggi-do (KR) for sk hynix inc., Min Seob LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F30/3312, G06F30/3947, G06F119/12
CPC Code(s): G06F30/3312
Abstract: disclosed is a semiconductor device and a semiconductor system including the same, the semiconductor device includes a plurality of pads, a data pattern analysis circuit configured to generate analysis signals by analyzing a data pattern of each of data mapped to each of the plurality of pads, a data remapping circuit configured to re-determine a relationship between the data and the plurality of pads based on the analysis signals, and remap the data to the plurality of pads based on the re-determined relationship, and an output circuit configured to output the remapped data through the plurality of pads.
Inventor(s): Seok Min LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06N3/0495
CPC Code(s): G06N3/0495
Abstract: provided herein may be a computing system and method of operating the same. the computing system may include an operating component including at least one convolution block, and a controller configured to control the operating component to perform convolution operations, wherein the at least one convolution block includes a first convolution layer configured to perform a first convolution operation on input data based on a 1�1 kernel to generate first result data, a second convolution layer configured to perform second convolution operations on 10 respective channels of first result data based on an n�n kernel, where n is a natural number of 2 or greater, and sum result values of the convolution operations to generate second result data, and a third convolution layer configured to perform a third convolution operation on the second result data based on the 1�1 kernel to generate final result data.
Inventor(s): Nam Jae LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C5/06, H10B41/20, H10B41/40, H10B43/20, H10B43/40
CPC Code(s): G11C5/063
Abstract: a memory device, and a method of manufacturing the memory device, includes a lower structure including a first pad exposed through a top surface of the lower structure. the memory device also includes an upper structure including a second pad exposed through a bottom surface of the upper structure. the first and second pads are bonded to each other, and an interface at which the first and second pads are bonded to each other forms a curved surface.
Inventor(s): Young Seung YOO of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Ji Seong MUN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hyeon Cheon SEOL of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Sung Hwa OK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jae Hoon JUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C8/18
CPC Code(s): G11C8/18
Abstract: a column address generation circuit including: a command set conversion section configured to generate column address information on the basis of sector information included in a first command set synchronized with a first clock signal, and to output a second command set from the first command set by replacing information on column address cycles of the first clock signal with the column address information in response to a conversion signal; and a column address output section configured to output a column address on the basis of the second command set.
Inventor(s): Joon Hong PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jeong Je PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Sang Sic YOON of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jong Hyuck CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/4076
CPC Code(s): G11C11/4076
Abstract: a semiconductor device includes a frequency division circuit configured to generate a first division clock and a second division clock by dividing a frequency of a clock, and an internal command generation circuit configured to generate an internal command based on a command in synchronization with the first division clock and the second division clock, configured to latch, in a pipe latch, a phase detection signal that is generated based on the timing at which the command is received, and configured to compensate for generation timing of the internal command based on the phase detection signal that has been latched in the pipe latch.
Inventor(s): Seung-Hwan KIM of Seoul (KR) for sk hynix inc., Su-Ock CHUNG of Seoul (KR) for sk hynix inc., Seon-Yong CHA of Chungcheongbuk-do (KR) for sk hynix inc.
IPC Code(s): G11C11/4097, G11C7/18, G11C11/401, H10B12/00
CPC Code(s): G11C11/4097
Abstract: a memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.
Inventor(s): Hyung Jin CHOI of Gyeonggi-do (KR) for sk hynix inc., Se Chun PARK of Gyeonggi-do (KR) for sk hynix inc., In Gon YANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/08, G11C16/10
CPC Code(s): G11C16/3459
Abstract: a memory device including: a memory device may include: a memory cell array, and a controller configured to perform program loops each comprising a voltage application operation, a word line holding operation, and a verification operation until a program operation for selected memory cells is successful, during the word line holding operation, apply a holding pass voltage having a higher level than a ground voltage to each of first word lines having a program state and second word lines having an erase state, which belong to unselected word lines among a plurality of word lines, during the verification operation, apply a verification pass voltage having a higher level than the holding pass voltage to k word lines that belong to the first word lines and the second word lines, and apply the holding pass voltage to remaining word lines except the k word lines, among the second word lines.
Inventor(s): Hee Youl LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C11/56, G11C16/10
CPC Code(s): G11C16/3459
Abstract: a method of operating a semiconductor memory device includes a plurality of program loops for programming selected memory cells among a plurality of memory cells. each of the plurality of program loops includes setting a state of a bit line connected to the selected memory cells, applying a program voltage to a word line connected to the selected memory cells, and performing a verify operation on the selected memory cells using a first pre-verify voltage, a second pre-verify voltage greater than the first pre-verify voltage, and a main verify voltage greater than the second pre-verify voltage. a first program permission cell, a second program permission cell, a third program permission cell, and a program prohibition cell are determined by performing the verify operation.
Inventor(s): Hyun Chul SEO of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/538, H01L25/065
CPC Code(s): H01L23/5386
Abstract: a semiconductor package includes: a substrate; a first semiconductor chip positioned over the substrate and electrically connected to the substrate; a second semiconductor chip stack positioned over the first semiconductor chip and including a plurality of second semiconductor chips that are stacked in a vertical direction while being electrically connected to the first semiconductor chip; and a dummy third semiconductor chip positioned over the second semiconductor chip stack, wherein a third height of a third bonding structure coupling the third semiconductor chip to an uppermost second semiconductor chip among the second semiconductor chips is greater than a second height of a second bonding structure coupling one among the second semiconductor chips to an another one among the second semiconductor chips positioned directly therebelow or the first semiconductor chip positioned directly therebelow.
20250038123. MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Yoo Hyun NOH of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/544, H10B43/10, H10B43/27, H10B43/35
CPC Code(s): H01L23/544
Abstract: the present technology relates to a memory device and a method of manufacturing the same. a memory device according to an embodiment of the present disclosure includes a main chip region, a chip guard region disposed adjacent to the main chip region, a plurality of chip guard patterns formed in the chip guard region, and a buffer slit formed in a space between the plurality of chip guard patterns.
Inventor(s): Hee Sun LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/00
CPC Code(s): H01L23/562
Abstract: a stacked semiconductor device may include a first wafer and at least one first insulation support pattern. the first wafer may include a first surface having at least one insulation layer and a second surface opposite to the first surface. the first insulation support pattern may be extended from the first surface of the first wafer into the insulation layer. the first insulation support pattern may be formed in a region of the first surface where an integrated circuit may not be formed.
Inventor(s): Seung Ho LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H02H9/04
CPC Code(s): H02H9/046
Abstract: an electro-static discharge (esd) protection circuit includes an esd current discharge circuit including a first transistor, a second transistor, and a third transistor, connected in series and connected between a pad and a ground voltage, an esd detection circuit configured to turn on the third transistor when the esd event occurs, and a bias generation circuit configured to provide a bias voltage for turning on the first transistor to a gate of the first transistor when the esd event occurs.
Inventor(s): Jae Hyung JANG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H04N25/77
CPC Code(s): H04N25/77
Abstract: an image sensing device is provided to include a first pixel including a first single-photon avalanche diode (spad) that includes a cathode to receive a first bias voltage; a second pixel including a second spad that includes an anode to receive a second bias voltage; and a selection circuit coupled to the first pixel and the second pixel and configured to select the first pixel or the second pixel to produce an output.
Inventor(s): Sung Mean PARK of Gyeonggi-do (KR) for sk hynix inc., Seung Hwan KIM of Gyeonggi-do (KR) for sk hynix inc., Dong Il SONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/03
Abstract: a method for fabricating a semiconductor device includes forming a stack body including a recess target layer over a lower structure; forming sacrificial isolation openings in the stack body; forming sacrificial isolation layers including blocking layers in the sacrificial isolation openings; forming sacrificial vertical openings in the stack body between the sacrificial isolation layers; forming a preliminary horizontal layer by recessing the recess target layer of the stack body through the sacrificial vertical openings; forming a first dielectric layer that covers the preliminary horizontal layer; forming a second dielectric layer over the first dielectric layer; forming cell isolation openings by removing the sacrificial isolation layers; and trimming the first dielectric layer through the cell isolation openings.
Inventor(s): Seung Hwan KIM of Gyeonggi-do (KR) for sk hynix inc., Jeong Hoon KWON of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/03
Abstract: a method for fabricating a semiconductor device including high-integrated memory cells may include forming a cell mold in which a plurality of mold layers are stacked, over a lower structure; forming a line-shape vertical opening in the cell mold, which is vertically oriented in a stack direction of the cell mold; forming a storage opening that horizontally extends from the line-shape vertical opening; and forming a data storage element in the storage opening.
Inventor(s): Ki Hong LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B41/27, H10B41/10, H10B43/10, H10B43/27
CPC Code(s): H10B41/27
Abstract: a semiconductor device, and a method of manufacturing the semiconductor device, includes a first source layer, a second source layer, a first insulating passivation layer partially interposed between the first source layer and the second source layer, and a gate structure located on the second source layer. the semiconductor device also includes a source contact structure passing through the gate structure, the second source layer, and the first insulating passivation layer. the source contact structure is coupled to the first source layer.
20250040136. SEMICONDUCTOR MEMORY_simplified_abstract_(sk hynix inc.)
Inventor(s): In Ku KANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, G11C16/04, H10B41/10, H10B41/27, H10B43/10
CPC Code(s): H10B43/27
Abstract: there are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. the semiconductor memory device includes a lower interlayer insulating layer, an upper interlayer insulating layer, a channel pattern passing through the lower interlayer insulating layer and the upper interlayer insulating layer, a conductive layer facing the channel pattern between the lower interlayer insulating layer and the upper interlayer insulating layer, and a storage pattern arranged in a lateral groove, the lateral groove defined between the conductive layer and the channel pattern by the lower interlayer insulating layer and the upper interlayer insulating layer protruding toward the channel pattern more than the conducive layer, in which a distance from the conductive layer from the channel pattern decreases toward an end of the lateral groove.
Inventor(s): Ji Hyeun SHIN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Da Yung BYUN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H01L23/60
CPC Code(s): H10B43/27
Abstract: a memory device and a manufacturing method of the memory device are provided. the memory device includes a discharge contact; a source line adjacent to and spaced apart from the discharge contact; an etch stop pattern located between the discharge contact and the source line, the etch stop pattern being closer to the source line than the discharge contact; and a sub-support pattern located on the source line and the etch stop pattern.
Inventor(s): Min Young HEO of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/27
CPC Code(s): H10B43/27
Abstract: a semiconductor device may include a gate structure including insulating layers and conductive layers that are alternately stacked, a contact plug extending through the gate structure to connect to at least one of the conductive layers, and first insulating spacers that are disposed between the respective conductive layers and the contact plug. a lowest first insulating spacer, among the first insulating spacers, may have a first thickness. the remaining first insulating spacers may each have a second thickness greater than the first thickness.
Inventor(s): Yoon Jae NAM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L29/423, H01L29/66, H10B12/00
CPC Code(s): H01L29/42356
Abstract: a semiconductor device includes a first buried gate configured to extend in a first direction, a bit-line contact disposed on one side of the first buried gate while being located outside the first buried gate, a storage node contact disposed on the other side of the first buried gate in a diagonal direction of the bit-line contact while being located outside the first buried gate, and active regions arranged spaced apart from each other in the first direction while overlapping with the first buried gate. each active region includes a first extension region configured to extend in a second direction perpendicular to the first direction while overlapping with the bit-line contact, a second extension region configured to extend in the second direction while overlapping with the storage node contact, and a third extension region configured to extend in a diagonal direction while overlapping with the first buried gate.
- SK hynix Inc.
- G06F3/06
- CPC G06F3/0634
- Sk hynix inc.
- CPC G06F3/0653
- CPC G06F3/0655
- G06F11/10
- G06F11/07
- CPC G06F11/1068
- G06F30/3312
- G06F30/3947
- G06F119/12
- CPC G06F30/3312
- G06N3/0495
- CPC G06N3/0495
- G11C5/06
- H10B41/20
- H10B41/40
- H10B43/20
- H10B43/40
- CPC G11C5/063
- G11C8/18
- CPC G11C8/18
- G11C11/4076
- CPC G11C11/4076
- G11C11/4097
- G11C7/18
- G11C11/401
- H10B12/00
- CPC G11C11/4097
- G11C16/34
- G11C16/08
- G11C16/10
- CPC G11C16/3459
- G11C11/56
- H01L23/538
- H01L25/065
- CPC H01L23/5386
- H01L23/544
- H10B43/10
- H10B43/27
- H10B43/35
- CPC H01L23/544
- H01L23/00
- CPC H01L23/562
- H02H9/04
- CPC H02H9/046
- H04N25/77
- CPC H04N25/77
- CPC H10B12/03
- H10B41/27
- H10B41/10
- CPC H10B41/27
- G11C16/04
- CPC H10B43/27
- H01L23/60
- H01L29/423
- H01L29/66
- CPC H01L29/42356