SK hynix Inc. patent applications on February 27th, 2025
Patent Applications by SK hynix Inc. on February 27th, 2025
SK hynix Inc.: 20 patent applications
SK hynix Inc. has applied for patents in the areas of H10B43/27 (4), H01L23/00 (4), G11C16/08 (3), H01L25/065 (3), H10B80/00 (3) H10B43/27 (3), G11C16/10 (2), G01R31/2884 (1), H04N25/78 (1), H10B80/00 (1)
With keywords such as: memory, data, structure, device, cell, circuit, semiconductor, stack, layers, and active in patent application abstracts.
Patent Applications by SK hynix Inc.
20250067798. MONITORING CIRCUIT AND SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Tae-Pyeong KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G01R31/28, H01L21/66, H03K19/20
CPC Code(s): G01R31/2884
Abstract: embodiments of the present disclosure relate to a monitoring circuit and a semiconductor device, and particularly, to a monitoring circuit including an oscillation circuit configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level and a counter configured to count the number of rises or the number of falls of the oscillation signal, and a semiconductor device including the monitoring circuit.
Inventor(s): Seung Yeol LEE of Gyeonggi-do (KR) for sk hynix inc., Jung Soo KIM of Gyeonggi-do (KR) for sk hynix inc., Chang Hoon LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F11/07
CPC Code(s): G06F11/079
Abstract: a fail data augmentation device may input a plurality of fail data units to a data augmentation model, obtain a plurality of augmented fail data units outputted from the data augmentation model, and delete one or more of the augmented fail data units. the plurality of fail data units and the plurality of augmented fail data units includes a first parameter indicating one of a plurality of banks included in a random access memory, a second parameter indicating one of a plurality of matrices included in the bank corresponding to the first parameter, and a third parameter indicating one of a plurality of hex units included in the matrix corresponding to the second parameter respectively.
20250068663. STRING FILTER DEVICE AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Joo Young KIM of Gyeonggi-do (KR) for sk hynix inc., Tae Young AHN of Gyeonggi-do (KR) for sk hynix inc., Soo Hong AHN of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F16/335
CPC Code(s): G06F16/335
Abstract: a string filter device may include an input buffer group and a string comparator group. the input buffer group may store a plurality of string group data segments. each of the plurality of string group data segments has a first size and includes a plurality of string data having a variable size. the string comparator group may extract a plurality of different sub-string group data segments having a second size among the plurality of string group data segments, and compare, in parallel, each of the plurality of sub-string group data segments with query data, using a plurality of string comparators.
20250069187. IMAGE SIGNAL PROCESSOR_simplified_abstract_(sk hynix inc.)
Inventor(s): Kazuhiro YAHATA of Tokyo (JP) for sk hynix inc.
IPC Code(s): G06T3/4038, G06V10/75
CPC Code(s): G06T3/4038
Abstract: an image signal processor includes a bit extension processor configured to generate extension data by expanding, by a first number of bits, a number of bits of input data including a bayer image and a white image, and an output circuit configured to adjust, upon receiving the extension data, the first number of bits to a second number of bits, to generate output data.
Inventor(s): Byoung Sung YOU of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/10, G06F11/10, G11C7/12, G11C29/42
CPC Code(s): G11C7/1039
Abstract: a semiconductor device includes a memory cell array and a plurality of read and write circuits. the memory cell array includes a plurality of planes. any one of the read and write circuits generates parity data based on data sequentially received from a controller through a channel.
20250069630. SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Hyung Sik WON of Gyeonggi-do (KR) for sk hynix inc., Seung Hwan KIM of Gyeonggi-do (KR) for sk hynix inc., Jun Ho CHEON of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/18, G11C5/06
CPC Code(s): G11C7/18
Abstract: a semiconductor device may include a bit line extending in a third direction, a plurality of active layers extending in a first direction and contacting the bit line, a plurality of word lines extending in a second direction and each disposed at an top surface or bottom surface of each of the plurality of active layers, a plurality of capacitors contacting the plurality of active layers, and a contact formed in at least one active layer disposed at the uppermost part of the bit line, among the plurality of active layers. the bit line and the contact may be electrically connected or separated by using, as a control line, a word line disposed in the top surface or bottom surface of the at least one active layer, among the plurality of word lines.
20250069639. MEMORY AND OPERATION METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Sang Woo YOON of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/406, G06F3/06, G11C11/4078, G11C11/408, G11C11/4091, G11C11/4094, G11C29/12
CPC Code(s): G11C11/40615
Abstract: an operation method of a memory may include receiving an active command and an active address; determining whether a row corresponding to the active address and a row corresponding to a target row address are able to be substantially simultaneously activated; activating the row corresponding to the active address; and activating the row corresponding to the target row address in response to determining that the row corresponding to the active address and the row corresponding to the target row address are able to be substantially simultaneously activated.
Inventor(s): Chi Wook AN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/08, G11C16/34
CPC Code(s): G11C16/10
Abstract: a memory device includes: a plurality of memory cells; a peripheral circuit for performing a program operation of storing data in the plurality of memory cells; and a program operation control circuit for, in the program operation, controlling the peripheral circuit to perform a foggy program operation of increasing a threshold voltage of the plurality of memory cells to a threshold voltage corresponding to any one state among an erase state and first to sixth foggy program states, and perform a fine program operation of increasing the threshold voltage of the plurality of memory cells to any one state among the erase state and first to fifteenth fine program states.
Inventor(s): Ie Ryung PARK of Icheon-si (KR) for sk hynix inc., Dong Sop LEE of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G06F3/06, G11C16/30
CPC Code(s): G11C16/10
Abstract: a storage device may input a program command requesting to program target data into the memory, input the target data into a memory, and input the program confirmation command into the memory after inputting the program command and the target data into the memory. in this case, the program confirmation command may include information about a cell type of memory cells to be programmed with target data among a plurality of memory cells.
20250069674. SEMICONDUCTOR DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Sung Hyun HWANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jae Yeop JUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/08, G11C16/14, G11C16/24
CPC Code(s): G11C16/3445
Abstract: a semiconductor device includes a memory cell array and a peripheral circuit. the memory cell array is coupled to a plurality of word lines and a plurality of bit lines. the peripheral circuit performs a deep-erase verification operation to determine whether a target memory cell has a threshold voltage that is lower than a first negative reference voltage by applying a second negative reference voltage that is lower than the first negative reference voltage to the target memory cell.
Inventor(s): Yun Cheol HAN of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/00, H01L23/58
CPC Code(s): H01L23/562
Abstract: a semiconductor device may include a stack including a chip region and a guard region surrounding the chip region, contact structures positioned in the chip region, and a chip guard structure positioned in the guard region and including first protrusions protruding by a first width and second protrusions protruding by a second width greater than the first width.
Inventor(s): Han Sol PARK of Gyeonggi-do (KR) for sk hynix inc., Shin Hoo KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N25/78, H04N25/772
CPC Code(s): H04N25/78
Abstract: a readout circuit and an image sensing device including the same are disclosed. the readout circuit includes a ramp signal generator configured to generate a ramp signal having first noise, a sampling circuit configured to generate a pixel sampling signal having second noise by sampling a pixel signal, and a conversion circuit configured to compare the ramp signal with the pixel sampling signal and offset the first noise and the second noise based on the comparison result.
Inventor(s): Min Chul SUNG of Gyeonggi-do (KR) for sk hynix inc., Sei Yon KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/00
Abstract: a semiconductor device includes a bit line; a plurality of first semiconductor pillars disposed over the bit line; a plurality of first cell contact plugs disposed between the first semiconductor pillars; a plurality of second semiconductor pillars coupled to the first cell contact plugs; a plurality of second cell contact plugs disposed between the second semiconductor pillars and coupled to the first semiconductor pillars; and a plurality of capacitors respectively coupled to the second semiconductor pillars and the second cell contact plugs.
Inventor(s): Seung Hwan KIM of Gyeonggi-do (KR) for sk hynix inc., Gil Seop KIM of Gyeonggi-do (KR) for sk hynix inc., Hye Won YOON of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/03
Abstract: a method for fabricating a semiconductor device includes forming a stack body including a plurality of recess target layers over a lower structure; forming sacrificial isolation openings in the stack body; forming sacrificial isolation layers in the sacrificial isolation openings; forming sacrificial vertical openings having bottom surfaces disposed at a lower level than bottom surfaces of the sacrificial isolation openings in the stack body between the sacrificial isolation layers; forming preliminary horizontal layers by recessing the recess target layers through the sacrificial vertical openings; forming sacrificial pillar structures that fill the sacrificial vertical openings; forming cell isolation openings by removing the sacrificial isolation layers; forming horizontal layers by trimming the preliminary horizontal layers through the cell isolation openings; and forming cell isolation layers that fill the cell isolation openings.
Inventor(s): Seok Min CHOI of Gyeonggi-do (KR) for sk hynix inc., Jung Shik JANG of Gyeonggi-do (KR) for sk hynix inc., Rho Gyu KWAK of Gyeonggi-do (KR) for sk hynix inc., In Su PARK of Gyeonggi-do (KR) for sk hynix inc., Won Geun CHOI of Gyeonggi-do (KR) for sk hynix inc., Jung Dal CHOI of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H01L23/00, H01L25/065, H10B41/27, H10B41/41, H10B43/40, H10B80/00
CPC Code(s): H10B43/27
Abstract: the present technology relates to a semiconductor memory device and a method of manufacturing the same. the semiconductor memory device includes a first stack structure, a plurality of first slits passing through the first stack structure in a vertical direction and extending in a first horizontal direction orthogonal to the vertical direction, a first source line layer contacting an a top portion of the first stack structure, a second source line layer directly contacting the first source line layer, a second stack structure contacting the second source line layer and overlapping with the first stack structure in the vertical direction, and a plurality of second slits passing through the second stack structure in the vertical direction and extending in a second horizontal direction orthogonal to the vertical direction.
Inventor(s): Jae Ho KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27
CPC Code(s): H10B43/27
Abstract: a memory device including: a first stack structure including conductive layers stacked along a first direction, the first stack structure having a stepped structure defined by end portions of the conductive layers; contact plugs respectively connected to the conductive layers, the contact plugs extending along the first direction, the contact plugs extending to the inside of the first stack structure; and dummy layers located between the contact plugs.
Inventor(s): Won Geun CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Shik JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jang Won KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Mi Seong PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/10, H10B41/20, H10B41/27, H10B43/10, H10B63/00, H10B99/00
CPC Code(s): H10B43/27
Abstract: there are provided a memory device and a manufacturing method of the memory device. the memory device includes: a first gate stack structure and a second gate stack structure, disposed on a substrate; and a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other.
20250072000. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Sung Wook JUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/40, H01L23/00, H01L25/065, H01L25/18, H10B43/27, H10B80/00, G11C16/08
CPC Code(s): H10B43/40
Abstract: there is provided a semiconductor memory device. the semiconductor memory device includes a first peripheral circuit structure, a cell array structure, a mold insulating structure disposed between the first peripheral circuit structure and the cell array structure, and a second peripheral circuit structure disposed in the mold insulating structure and including a pass transistor.
20250072011. MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Jung Shik JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Seok Min CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Rho Gyu KWAK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Won Geun CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., In Su PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B80/00, H01L23/00, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H10B80/00
Abstract: a memory device includes a first peripheral circuit having first page buffers is functionally divided into a cell region and a connection region. a first memory cell array positioned on the first peripheral circuit includes first bit lines that are electrically connected to the first page buffers. a second memory cell array positioned on the first memory cell array includes second bit lines, which are electrically connected to the first bit lines, respectively. the first peripheral circuit is able to make use of both memory arrays using connections between the two memory arrays.
Inventor(s): Young Gwang YOON of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L29/51, H01L21/225, H01L21/28, H01L29/423
CPC Code(s): H01L29/513
Abstract: a semiconductor device includes a semiconductor substrate formed to include a first active region and a second active region, first and second dielectric layer disposed over the first and second active regions, first and second gate electrode disposed over the first and second dielectric layers, respectively; and wherein the first and second active region have different impurity doping types from each other, and fluorine concentration of the first dielectric layer is higher than fluorine concentration of the second dielectric layer.
- SK hynix Inc.
- G01R31/28
- H01L21/66
- H03K19/20
- CPC G01R31/2884
- Sk hynix inc.
- G06F11/07
- CPC G06F11/079
- G06F16/335
- CPC G06F16/335
- G06T3/4038
- G06V10/75
- CPC G06T3/4038
- G11C7/10
- G06F11/10
- G11C7/12
- G11C29/42
- CPC G11C7/1039
- G11C7/18
- G11C5/06
- CPC G11C7/18
- G11C11/406
- G06F3/06
- G11C11/4078
- G11C11/408
- G11C11/4091
- G11C11/4094
- G11C29/12
- CPC G11C11/40615
- G11C16/10
- G11C16/04
- G11C16/08
- G11C16/34
- CPC G11C16/10
- G11C16/30
- G11C16/14
- G11C16/24
- CPC G11C16/3445
- H01L23/00
- H01L23/58
- CPC H01L23/562
- H04N25/78
- H04N25/772
- CPC H04N25/78
- H10B12/00
- CPC H10B12/00
- CPC H10B12/03
- H10B43/27
- H01L25/065
- H10B41/27
- H10B41/41
- H10B43/40
- H10B80/00
- CPC H10B43/27
- H10B41/10
- H10B41/20
- H10B43/10
- H10B63/00
- H10B99/00
- H01L25/18
- CPC H10B43/40
- H01L25/00
- CPC H10B80/00
- H01L29/51
- H01L21/225
- H01L21/28
- H01L29/423
- CPC H01L29/513
