SK hynix Inc. patent applications on February 13th, 2025
Patent Applications by SK hynix Inc. on February 13th, 2025
SK hynix Inc.: 20 patent applications
SK hynix Inc. has applied for patents in the areas of G06F3/06 (3), H10B12/00 (3), G01R19/10 (2), H04N25/75 (2), H04N13/207 (2) H10B43/27 (2), H04N13/204 (2), H03M13/1125 (1), H10B12/315 (1), H10B12/30 (1)
With keywords such as: memory, signal, data, device, circuit, control, conductive, based, layers, and target in patent application abstracts.
Patent Applications by SK hynix Inc.
20250052808. WAFER ANALYZING DEVICE AND WAFER ANALYZING SYSTEM_simplified_abstract_(sk hynix inc.)
Inventor(s): Tae Beom KIM of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G01R31/28
CPC Code(s): G01R31/2831
Abstract: a semiconductor wafer analyzing device and semiconductor wafer analyzing system are disclosed that provide estimated analysis values of unit areas that are not measured in a target wafer. the device and system calculate estimated analysis values based on measured analysis values of unit areas in a basic wafer and measured analysis values of some unit areas in the target wafer.
Inventor(s): Ji Hyo KANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F1/08, G06F1/10, G06F1/12, H03L7/089, H03L7/191
CPC Code(s): G06F1/08
Abstract: a semiconductor apparatus includes a frequency control circuit and an internal clock generation circuit. the frequency control circuit generates a frequency information signal based on a command address signal, and generates a frequency control signal by comparing the frequency information signal with a frequency setting signal. the internal clock generation circuit generates an internal clock signal from a system clock signal based on the frequency control signal.
Inventor(s): Ji Hyo KANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F1/10, H03K3/037, H03K19/0185
CPC Code(s): G06F1/10
Abstract: a clock distribution network includes an input control circuit and a clock tree. the input control circuit is configured to generate a control input clock signal based on an input clock signal and a low power mode signal. the clock tree is configured to generate an output clock signal by buffering the control input clock signal. when the low power mode signal is enabled, the input control circuit is configured to change a dc level of the control input clock signal.
Inventor(s): Ie Ryung PARK of Icheon-si (KR) for sk hynix inc., Dong Sop LEE of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: a storage device includes: a memory device; and a memory controller configured to receive, from an external device having an external memory, a write command for storing data in the memory device and address information of an area in the external memory that corresponds to the write command, and acquire write data from the external device based on the address information. the memory controller may be further configured to store the write data in the memory device in response to the write command. the memory controller may be further configured to acquire a portion of the write data from the external memory upon a failure of storage of the portion of the write data in the memory device, and provide a response to the write command to the external device after completing storing of the write data in the memory device.
20250053333. CONTROLLER AND STORAGE DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Chi Ho KIM of Gyeonggi-do (KR) for sk hynix inc., Do Hyung KIM of Gyeonggi-do (KR) for sk hynix inc., Jea Young ZHANG of Gyeonggi-do (KR) for sk hynix inc., Hoe Seung JUNG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0656
Abstract: in an embodiment of the disclosed technology, a storage device starts in advance loading map data before outputting a signal corresponding to a read buffer command of a host device, encodes map data using a plurality of map load areas and a plurality of encoding areas, and provides encoded map data to the host device.
Inventor(s): Kyu Ho CHOI of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a storage device may receive provisioning information, which is setting information for a provisioning operation that sets a plurality of zones on a memory, from a host, and set a first zone in which cold data requested to be written by the host is stored, among the plurality of zones based on write booster type included in the provisioning information. the storage device may set the first zone in a first memory area if the write booster type is a first type, and set the first zone in a second memory area if the write booster type is a second type.
Inventor(s): Chan Keun KWON of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hyeon Cheon SEOL of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Sung Hwa OK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/10, G11C7/22
CPC Code(s): G11C7/1069
Abstract: a memory device includes: a plurality of memory planes each including a plurality of memory banks, the plurality of memory planes being grouped into memory planes; a plurality of compressing circuits respectively connected to the plurality of memory banks, the plurality of compressing circuits outputting compressed data by respectively compressing data read from the plurality of memory; a plurality of first merge circuits receiving the compressed data and output control signals corresponding to at least a portion of the memory banks, the plurality of first merge circuits outputting first merged data obtained by merging compressed data corresponding to memory banks grouped as a first merge group; a second merge circuit outputting second merged data obtained by merging first merged data generated from memory banks included in the same plane group; and an output buffer circuit outputting the second merged data, based on at least a portion of the output control signals.
20250054530. MEMORY DEVICE AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Tae Jung HA of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G11C11/16
CPC Code(s): G11C11/1673
Abstract: memory devices and operating methods are disclosed. in an embodiment, a memory device may include a memory cell array including a plurality of memory cells, each of the plurality of memory cells configured to store a data value corresponding to read data to be read out through a plurality of conductive lines, and a read circuit connected to the plurality of conductive to generate the read data corresponding to the data value stored in a selected memory cell among the plurality of memory cells based on or according to whether there is a change in a cell current flowing through the selected memory cell during a single read period.
20250054551. MEMORY DEVICE AND OPERATING METHOD OF MEMORY DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Chan Keun KWON of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jaehyeong HONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/26, G11C16/04, G11C16/32
CPC Code(s): G11C16/26
Abstract: a memory device may include memory banks comprised of memory blocks; data compressing circuits connected to memory blocks and first merge circuits. a second merge circuit receives output from the first merge circuits. a delay detecting circuit generates delay control signals by comparing the output control signals. a compensating circuit calibrates the output control signals, based on the delay control signal. an output buffer circuit latches the second merged data and outputs the second merged data, based on at least a portion of the output control signals.
Inventor(s): Won Jae CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Chang Hee LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hyun Chul CHO of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/30, G11C16/04, G11C16/24
CPC Code(s): G11C16/30
Abstract: according to an embodiment of the present disclosure, a memory device includes a memory cell array including a plurality of planes; a charge pump configured to generate an operating voltage used for an operation on each of the plurality of planes according to a first clock signal having a first cycle; page buffers each configured to store pass data representing whether an operation of each of the plurality of planes has been completed; and an operation control circuit configured to, based on a number of the pass data received from the page buffers, control the charge pump to generate the operating voltage according to a second clock signal having a second cycle that is longer than the first cycle.
Inventor(s): Haobo Wang of Sunnyvale CA (US) for sk hynix inc., Qiuju Diao of Santa Clara CA (US) for sk hynix inc., Fan Zhang of Fremont CA (US) for sk hynix inc.
IPC Code(s): H03M13/11, G06F11/10
CPC Code(s): H03M13/1125
Abstract: techniques for adjusting log likelihood ratios in a decoder may include determining an assist read (ar) zone based on performing assist reads (ar) of multibit memory cells of a memory. soft reads of the multibit memory cells may be performed to determine a bin within the ar zone for each bit of the data stored in the memory cells. each bin is associated with a log likelihood ratio (llr) value. error correction decoding on the data stored in the memory cells may be performed followed by collecting statistics on the decoded data for each bin in each ar zone. a hard error percentage may be computed for each ar zone based on the collected statistics, and one or more llr values may be adjusted based on the hard error percentage.
Inventor(s): Jeong Eun SONG of Gyeonggi-do (KR) for sk hynix inc., Oh Jun KWON of Gyeonggi-do (KR) for sk hynix inc., Yu Jin PARK of Gyeonggi-do (KR) for sk hynix inc., Sung Uk SEO of Gyeonggi-do (KR) for sk hynix inc., Min Seok SHIN of Gyeonggi-do (KR) for sk hynix inc., Sun Young LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N13/204, G01B11/22, G01R19/10, G01S17/894, H04N13/207, H04N13/218, H04N25/40, H04N25/581, H04N25/616, H04N25/705, H04N25/71, H04N25/75
CPC Code(s): H04N13/204
Abstract: an image sensing device includes a first sampling circuit suitable for sampling a reference ramp signal as a ramp signal; a switching circuit suitable for sequentially outputting first and second pixel signals to a common node based on first and second control signals; a second sampling circuit suitable for sampling the first and second pixel signals, which are sequentially outputted through the common node, as a measurement signal; a comparison circuit suitable for comparing the ramp signal with the measurement signal and generating a comparison signal corresponding to a comparison result; and a count circuit suitable for generating a count signal, which corresponds to a voltage level of the measurement signal, based on the comparison signal and a clock signal.
Inventor(s): Jeong Eun SONG of Gyeonggi-do (KR) for sk hynix inc., Oh Jun KWON of Gyeonggi-do (KR) for sk hynix inc., Yu Jin PARK of Gyeonggi-do (KR) for sk hynix inc., Sung Uk SEO of Gyeonggi-do (KR) for sk hynix inc., Min Seok SHIN of Gyeonggi-do (KR) for sk hynix inc., Sun Young LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N13/204, G01B11/22, G01R19/10, G01S17/894, H04N13/207, H04N13/218, H04N25/40, H04N25/581, H04N25/616, H04N25/705, H04N25/71, H04N25/75
CPC Code(s): H04N13/204
Abstract: an image sensing device includes a first sampling circuit suitable for sampling a reference ramp signal as a ramp signal; a switching circuit suitable for sequentially outputting first and second pixel signals to a common node based on first and second control signals; a second sampling circuit suitable for sampling the first and second pixel signals, which are sequentially outputted through the common node, as a measurement signal; a comparison circuit suitable for comparing the ramp signal with the measurement signal and generating a comparison signal corresponding to a comparison result; and a count circuit suitable for generating a count signal, which corresponds to a voltage level of the measurement signal, based on the comparison signal and a clock signal.
Inventor(s): Chang Hee PYEOUN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N17/00, G06T7/00, G06T7/90, H04N23/81
CPC Code(s): H04N17/002
Abstract: an image sensor includes a pixel array including pixels and a controller configured to control the pixels to produce a plurality of images. the image sensor also includes a defect detector configured to determine a target image based on an average green pixel value and a gain value related to a light exposure time among the images, and detect an adaptive static defective pixel, which is a defective pixel with a fixed location based on pixel values included in the target image.
Inventor(s): Cheol Jon JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Dong Ik KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jun Hyeok CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N25/68, G06T3/4015, G06T7/13
CPC Code(s): H04N25/68
Abstract: an image signal processor capable of processing image signals and an image signal processing method for the same are disclosed. the image signal processor includes a first determiner configured to determine whether a target kernel including a target pixel corresponds to a corner pattern, a second determiner configured to determine a corner pattern group corresponding to the target kernel when the target kernel corresponds to the corner pattern, a third determiner configured to determine a target corner pattern corresponding to the target kernel from among a plurality of corner patterns of a corner pattern group corresponding to the target kernel, and a pixel interpolator configured to interpolate the target pixel using pixel data of a pixel corresponding to the target corner pattern.
Inventor(s): Seung Hwan KIM of Gyeonggi-do (KR) for sk hynix inc., Seung Cheol LEE of Gyeonggi-do (KR) for sk hynix inc., Hyun Woo JIN of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/03
Abstract: a method for fabricating a semiconductor device includes: forming preliminary horizontal layers vertically stacked over a lower structure in a first direction and extending horizontally in a second direction crossing the first direction; forming trimming target layers that surround each of the preliminary horizontal layers; forming horizontal layers by trimming the preliminary horizontal layers in a third direction crossing the second direction; forming trimmed target layers by trimming the trimming target layers in the third direction; and replacing the trimmed target layers with conductive layers.
Inventor(s): Hye Won YOON of Gyeonggi-do (KR) for sk hynix inc., Seung Hwan KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/30
Abstract: a semiconductor device includes a lower structure; a plurality of horizontal conductive layers oriented in a direction parallel to a surface of the lower structure; a plurality of reservoir capacitors commonly coupled to first-side ends of the horizontal conductive layers, wherein each of the plurality of the reservoir capacitors is vertically stacked over the lower structure, and includes a cylindrical storage node; and a vertical conductive line commonly coupled to second-side ends opposite to first-side ends of the horizontal conductive layers, extending in a direction perpendicular or substantially perpendicular to the surface of the lower structure, and including a plurality of electrode portions, each electrode portion being symmetrical with the cylindrical storage node of a corresponding reservoir capacitor.
Inventor(s): Heon Yong CHANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/315
Abstract: a method of manufacturing a semiconductor device including the array of conductive patterns is presented. the semiconductor device may include first conductive patterns disposed over an insulating layer over a semiconductor substrate, a second conductive pattern disposed to extend lengthwise to the side of the first conductive patterns, and third conductive patterns connected to the first conductive patterns and the second conductive pattern. the third conductive patterns may be storage nodes of a capacitor.
Inventor(s): Won Geun CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jeong Hwan KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Shik JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, G11C16/08
CPC Code(s): H10B43/27
Abstract: the present technology includes a memory device and a method of manufacturing the memory device. the memory device includes a memory block in which first and second connection regions and a cell region between the first and second connection regions are designated, a word line included in the memory block, a first drain selection line included in the memory block and positioned on the word line, a first drain contact contacting the first drain selection line of the first connection region, a second drain contact contacting the first drain selection line of the second connection region, and a first drain voltage supply line commonly contacting the first and second drain contacts.
Inventor(s): In Ku KANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/27
CPC Code(s): H10B43/27
Abstract: a semiconductor device may include a first support including a first inclined surface, a first gate structure including first insulating layers and first conductive layers alternately stacked along the first inclined surface, a second support positioned over or on the first support and including a second inclined surface, a second gate structure including second insulating layers and second conductive layers alternately stacked along the second inclined surface, a first contact plug extending through the second gate structure and connected to at least one first conductive layer among the first conductive layers, and a second contact plug disposed over or on the second gate structure and connected to at least one second conductive layer among the second conductive layers.
- SK hynix Inc.
- G01R31/28
- CPC G01R31/2831
- Sk hynix inc.
- G06F1/08
- G06F1/10
- G06F1/12
- H03L7/089
- H03L7/191
- CPC G06F1/08
- H03K3/037
- H03K19/0185
- CPC G06F1/10
- G06F3/06
- CPC G06F3/0625
- CPC G06F3/0656
- CPC G06F3/0659
- G11C7/10
- G11C7/22
- CPC G11C7/1069
- G11C11/16
- CPC G11C11/1673
- G11C16/26
- G11C16/04
- G11C16/32
- CPC G11C16/26
- G11C16/30
- G11C16/24
- CPC G11C16/30
- H03M13/11
- G06F11/10
- CPC H03M13/1125
- H04N13/204
- G01B11/22
- G01R19/10
- G01S17/894
- H04N13/207
- H04N13/218
- H04N25/40
- H04N25/581
- H04N25/616
- H04N25/705
- H04N25/71
- H04N25/75
- CPC H04N13/204
- H04N17/00
- G06T7/00
- G06T7/90
- H04N23/81
- CPC H04N17/002
- H04N25/68
- G06T3/4015
- G06T7/13
- CPC H04N25/68
- H10B12/00
- CPC H10B12/03
- CPC H10B12/30
- CPC H10B12/315
- H10B43/27
- G11C16/08
- CPC H10B43/27
- H10B41/27
