SK hynix Inc. patent applications on April 17th, 2025
Patent Applications by SK hynix Inc. on April 17th, 2025
SK hynix Inc.: 29 patent applications
SK hynix Inc. has applied for patents in the areas of H10B43/27 (5), G06F3/06 (4), H10B43/35 (3), H01L27/146 (2), G11C29/12 (2) H10B43/27 (3), H10B43/35 (2), G06F11/1068 (2), G11C29/46 (2), G01S7/4863 (1)
With keywords such as: configured, device, signal, layer, semiconductor, data, circuit, memory, generate, and output in patent application abstracts.
Patent Applications by SK hynix Inc.
20250123372. IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Eun Chang LEE of Gyeonggi-do KR for sk hynix inc., Min Kyu KIM of Gyeonggi-do KR for sk hynix inc., Jin Seon KIM of Gyeonggi-do KR for sk hynix inc., Hak Soon KIM of Gyeonggi-do KR for sk hynix inc., Da Hwan PARK of Gyeonggi-do KR for sk hynix inc., Min Seok SHIN of Gyeonggi-do KR for sk hynix inc., Hoo Chan LEE of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G01S7/4863, G01S17/894, H04N25/78
CPC Code(s): G01S7/4863
Abstract: an image sensing device capable of detecting a distance to a target object according to a time-of-flight (tof) method is disclosed. the image sensing device includes a plurality of light receiving elements each configured to generate a sensing voltage corresponding to a current pulse based on a photon reflected from a target object; a plurality of quenching circuits corresponding to the respective light receiving elements and each configured to output a pixel signal by controlling the sensing voltage from a corresponding light receiving element of the light receiving elements, and a readout circuit shared by the plurality of quenching circuits and configured to generate a readout signal by controlling a delay time of the pixel signal.
Inventor(s): Jung Woo KIM of Icheon-si KR for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0634
Abstract: provided herein may be a storage device capable of efficiently managing a host mapping table. the storage device may include a memory device and a memory controller configured to generate map information in which a physical address of the memory device is mapped to a logical address provided from a host, to provide a first map segment among a plurality of map segments included in the map information to the host, and to generate map change information when the first map segment is changed.
Inventor(s): Seon Ju LEE of Gyeonggi-do KR for sk hynix inc., Jeong Sun PARK of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: provided herein is a semiconductor memory device having improved lifespan. the storage device may include a memory device including a plurality of super blocks, and a controller configured to control the memory device in response to each request among a plurality of requests from a host, wherein the controller is further configured to allocate a first super block to a first write request of a first type, and allocate a second super block different from the first super block to respond to a second write request of a second type, control the memory device to store in the first super block write data corresponding to the first write request, and when the second write request is received from the host before reallocation of the second super block after deallocation, control the memory device to store in the first super block write data corresponding to the second write request.
Inventor(s): Dong Hyun CHO of Icheon-si KR for sk hynix inc., Eun Ju YOON of Icheon-si KR for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0658
Abstract: a storage device includes: a nonvolatile storage area for storing a plurality of map segments including information of one or more map entries representing mapping information between a logical address provided by an external device and a physical address corresponding to the logical address; a volatile storage area for temporarily storing journal data including information that keeps track of changes to the mapping information to enable for updating the mapping information; and a controller in communication with the nonvolatile storage area and the 10 volatile storage area and configured to count a number of first map segments that store the updated mapping information, and updating the mapping information in the nonvolatile storage area according to a ratio of a number of logical addresses included in the journal data and the number of first map segments.
Inventor(s): Kyu Ho CHOI of Icheon-si KR for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: provided herein may be a computing system having improved command processing speed. the computing system may include a host device configured to generate a command including information associated with operations to be requested, the information including a first information portion associated with a first operation of the operations and a second information portion associated with a second operation to be requested subsequent to the first operation, and output the command including the first information portion and the second information portion, and a storage device configured to store data and in communication with the host device, wherein the storage device is configured to: receive the command from the host device, perform the first operation in response to the command, and perform part of the second operation based on the second information portion in the command.
20250123922. Non-Blocking Chipkill Recovery_simplified_abstract_(sk hynix inc.)
Inventor(s): Meysam ASADI of San Jose CA US for sk hynix inc., Fan ZHANG of San Jose CA US for sk hynix inc.
IPC Code(s): G06F11/10, G06F13/16
CPC Code(s): G06F11/1068
Abstract: a memory system and a method for decoding of one or more codewords. the system has a storage medium having therein a first decode, a first processor associated with the storage medium and configured to xor results obtained from the first decoder when the one or more codewords in the storage medium are decoded, and a memory controller having therein a second decoder and a buffer, the memory controller configured to xor results obtained from the second decoder. the second decoder decodes the one or more codewords after failure of the first decoder to decode the one or more codewords.
20250123923. ELECTRONIC SYSTEM FOR MONITORING ERROR OF ADDRESS_simplified_abstract_(sk hynix inc.)
Inventor(s): Jin Ho JEONG of Icheon-si Gyeonggi-do KR for sk hynix inc., Saeng Hwan KIM of Icheon-si Gyeonggi-do KR for sk hynix inc., Mun Seon JANG of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1068
Abstract: an electronic system includes a controller configured to output a command, external row addresses, and external column addresses, receive a flag signal, and output the flag signal to a host. the electronic system also includes a semiconductor device configured to correct an error of internal data output from a memory cell selected based on the command, the external row addresses, and the external column addresses to output error-corrected internal data as data, and output the flag signal that is enabled when correcting the error in the internal data a set number of times.
Inventor(s): Youngjin OH of Seoul KR for sk hynix inc., Guyong PARK of Seoul KR for sk hynix inc., Haesoo CHUNG of Seongnam-si KR for sk hynix inc., Nam IK CHO of Seoul KR for sk hynix inc.
IPC Code(s): G06T5/10
CPC Code(s): G06T5/10
Abstract: an image restoring circuit includes a first restoring circuit including a first encoder and a first decoder, and configured to generate a first output image and first tensor data by restoring an input image; a second restoring circuit including a second encoder and a second decoder, and configured to restore the input image by using an output of the first encoder, an output of the first decoder, and the first tensor data to thereby generate a second output image; and a coupling circuit configured to generate second tensor data based on the output of the first encoder and the output of the first decoder and provide the second tensor data to the second encoder.
20250124957. MEMORY DEVICE INCLUDING PIPE LATCH_simplified_abstract_(sk hynix inc.)
Inventor(s): Young Seung YOO of Gyeonggi-do KR for sk hynix inc., Ji Seong MUN of Gyeonggi-do KR for sk hynix inc., Hyeon Cheon SEOL of Gyeonggi-do KR for sk hynix inc., Sung Hwa OK of Gyeonggi-do KR for sk hynix inc., Sung Wook CHO of Gyeonggi-do KR for sk hynix inc., Kyeong Min CHAE of Gyeonggi-do KR for sk hynix inc., Hyun Kyu KANG of Gyeonggi-do KR for sk hynix inc., Won Keun SONG of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C7/10
CPC Code(s): G11C7/1039
Abstract: a pipeline system includes a first inverter latch configured to receive plural data entries, and plural second inverter latches coupled to each other in parallel for storing the plural data entries input from the first inverter latch in a distributive manner. plural first switches are arranged between the first inverter latch and the plural second inverter latches, each first switch configured for controlling transmission of each of the plural data entries from the first inverter latch to one of the plural second inverter latches. plural second switches are configured to output the plural data entries stored in the plural second inverter latches.
Inventor(s): Jae KWON of Gyeonggi-do KR for sk hynix inc., Chae Hyoun PARK of Gyeonggi-do KR for sk hynix inc., Yun Jin LEE of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C11/4076, G11C11/408, G11C11/4091
CPC Code(s): G11C11/4076
Abstract: a semiconductor device includes a first delay circuit having a first delay amount that decreases according to a common bias, and configured to generate a first delay control signal based on the first delay amount; a second delay circuit having a second delay amount that increases according to the common bias, and configured to generate a second delay control signal based on the second delay amount; a signal generation circuit configured to generate a plurality of internal control signals in response to at least one of the first delay control signal and the second delay control signal; and an internal operation circuit configured to complementarily perform a first operation and a second operation within a target time in response to the internal control signals.
Inventor(s): Byeong Cheol LEE of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C29/46, G11C29/12
CPC Code(s): G11C29/46
Abstract: a semiconductor device may include a power control signal generation circuit configured to generate a power control signal that is activated when at least one of a power-up period and a test mode operation are performed and an operating power generation circuit configured to set operating power supplied to a word line driver as a high voltage in response to the power control signal.
Inventor(s): Hyun Seung KIM of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C29/46, G11C29/12, G11C29/14
CPC Code(s): G11C29/46
Abstract: a semiconductor device includes a skip exit control circuit configured to select one of a plurality of skip signals as a selection skip signal, responsive to a test mode signal, and generate a skip exit signal, responsive to the selection skip signal, a mode control circuit configured to generate a mode signal to change the mode responsive to the skip exit signal until entering a preset final mode, and a command control circuit configured to generate internal commands for each mode, responsive to the mode signal.
Inventor(s): Choung Ki SONG of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C29/52, G11C8/06, G11C8/18
CPC Code(s): G11C29/52
Abstract: a semiconductor system includes a controller outputting a chip selection signal and a command address for performing a read operation and then outputting the chip selection signal and the command address for performing an ecs operation, and a semiconductor device including a plurality of memory cells and generating a latch row address and a latch column address by latching the command address when an error occurs in internal data that are output from a memory cell that is selected, among a plurality of memory cells, after the start of the read operation based on the chip selection signal and the command address, determining the priority of the ecs operation for the plurality of memory cells based on the latch row address and the latch column address, and storing the internal data in the same memory cell again by correcting the error of the internal data.
Inventor(s): Dong Beom LEE of Icheon-si Gyeonggi-do KR for sk hynix inc., Hyeong Soo JEONG of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C29/00, G11C29/18, G11C29/52
CPC Code(s): G11C29/787
Abstract: an electronic device includes a first counting circuit configured to generate a first counting signal based on a comparison signal that is generated by comparing a first row address after the start of a first bootup operation and first fuse data that are generated by a first rupture operation, a second counting circuit configured to generate a second counting signal based on the comparison signal that is generated by comparing a second row address after the start of a second bootup operation and second fuse data that are generated by a second rupture operation, and a repair comparison circuit configured to generate a repair detection signal for detecting whether the first and second rupture operations are additionally performed by comparing the first counting signal with the second counting signal and configured to output the repair detection signal.
Inventor(s): Seung Ju LEE of Gyeonggi-do KR for sk hynix inc., Do Young JANG of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H01L23/528, H01L21/768, H01L23/532, H01L29/06
CPC Code(s): H01L23/5283
Abstract: a semiconductor device and a method for fabricating the same are provided. the semiconductor device includes a semiconductor pattern; an impurity region disposed at a side of the semiconductor pattern and having a lower surface that forms a flat surface with a lower surface of the semiconductor pattern; a gate structure disposed under the semiconductor pattern; and a contact plug disposed over the impurity region and electrically connected to the impurity region.
Inventor(s): Soon Chul KWON of Icheon-si Gyeonggi-do KR for sk hynix inc., Min Chang KIM of Icheon-si Gyeonggi-do KR for sk hynix inc., Seul Gi KIM of Icheon-si Gyeonggi-do KR for sk hynix inc., Hong Joo SONG of Icheon-si Gyeonggi-do KR for sk hynix inc., Ic Su OH of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H03K5/02, H03K3/037, H03K5/00, H03K5/135
CPC Code(s): H03K5/023
Abstract: a phase mixer circuit is configured to receive a first input clock signal and a second input clock signal, and to generate an intermediate clock signal having an intermediate phase between phases of the first and second input clock signals. the phase mixer circuit is configured to determine a logic value of a mixed code signal, and to generate an output clock signal by mixing one of the first and second input clock signals and the intermediate clock signal.
Inventor(s): Ki Hyuk SUNG of Icheon-si KR for sk hynix inc.
IPC Code(s): H03L7/099, H03K5/00, H03L7/089
CPC Code(s): H03L7/099
Abstract: an initial control voltage generating circuit for a voltage controlled oscillator (vco) includes a resistor coupled between a supply voltage terminal and an output node from which the initial control voltage is output, and a transmission gate resistor coupled between the output node and a ground voltage terminal. the transmission gate resistor includes a p-channel type mos (pmos) transistor and an n-channel type mos (nmos) transistor coupled in parallel between the output node and the ground voltage terminal.
Inventor(s): Dong Ik KIM of Icheon-si Gyeonggi-do KR for sk hynix inc., Cheol Jon JANG of Icheon-si Gyeonggi-do KR for sk hynix inc., Jun Hyeok CHOI of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H04N23/84, H04N17/00
CPC Code(s): H04N23/843
Abstract: an image signal processor may include a defect pixel determination unit configured to determine whether a target pixel is a defect pixel based on first comparison data that are a result of comparing pixel data of the target pixel included in a target kernel with pixel data of each of a plurality of pixels having attributes identical with attributes of the target pixel, a direction determination unit configured to determine a direction of the target kernel based on second comparison data that are a result of a comparison between pixel data of a pair of pixels that are disposed on a line in one direction and that have identical attributes, and a pixel interpolation unit configured to interpolate the pixel data of the target pixel by using the pixel data of each of a plurality of pixels that are disposed at locations corresponding to the direction of the target kernel.
20250126376. IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Eun Chang LEE of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H04N25/709, H01L23/00, H01L27/146, H04N25/42
CPC Code(s): H04N25/709
Abstract: an image sensing device capable of generating a high dynamic range (hdr) image is disclosed. the image sensing device includes a pixel and a compensation circuit. the pixel configured to output to a sensing node, a sensing voltage corresponding to a voltage of a floating diffusion region, which is included therein and has first and second capacitances in respective first and second modes, the second capacitance being greater than the first capacitance. the compensation circuit controls, in a first section, an offset voltage level of the sensing node through a first path and boosts, in a second section, the sensing voltage through a second path.
Inventor(s): Do Young JANG of Gyeonggi-do KR for sk hynix inc., Jae Il KANG of Gyeonggi-do KR for sk hynix inc., Myung Hee NA of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B41/41, H10B41/30, H10B43/30, H10B43/40
CPC Code(s): H10B41/41
Abstract: a semiconductor device and a method for fabricating the same are provided. the semiconductor device includes a first semiconductor structure including a cell region and a peripheral circuit region, and including a cell capacitor disposed in the cell region and a first insulating layer disposed in the cell region and the peripheral circuit region to cover the cell capacitor; a second semiconductor structure including a cell transistor disposed over the first insulating layer in the cell region and a peripheral circuit transistor disposed over the first insulating layer in the peripheral circuit region; and a first conductor passing through the first insulating layer to electrically connect a first cell source/drain region of the cell transistor and an electrode of the cell capacitor.
Inventor(s): Nam Jae LEE of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/27, H10B41/35, H10B43/35, H10B63/00
CPC Code(s): H10B43/27
Abstract: a semiconductor device may include a first gate structure including stacked first gate lines; first contact plugs extending through the first gate structure and connected to the first gate lines, respectively; a second gate structure including stacked second gate lines; second contact plugs extending through the second gate structure and connected to the second gate lines, respectively; and a slit structure located between the first gate structure and the second gate structure and including a lower sidewall having a wave shape and an upper sidewall having a straight line shape.
Inventor(s): Do Young KIM of Icheon-si Gyeonggi-do KR for sk hynix inc., Eun Mee KWON of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B43/27
CPC Code(s): H10B43/27
Abstract: the present disclosure includes a memory device and a method of manufacturing the memory device. the memory device includes a channel layer passing through gate lines stacked spaced apart from each other, a channel junction extending on the channel layer, a capping layer surrounded by the channel layer, a void surrounded by the capping layer, a capping pattern surrounded by the channel junction and contacting an upper portion of the capping layer and the void, and a source line positioned on the gate lines and contacting the channel junction.
Inventor(s): Sun Mi PARK of Icheon-si Gyeonggi-do KR for sk hynix inc., Nam Kuk KIM of Icheon-si Gyeonggi-do KR for sk hynix inc., Eun Mee KWON of Icheon-si Gyeonggi-do KR for sk hynix inc., Sang Wan JIN of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B43/27, G11C16/04, H10B43/10
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs penetrating the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs penetrating the upper stack and overlapping the plurality of cell plugs, respectively, and a separation pattern penetrating the upper stack and disposed between at least two adjacent drain select plugs among the plurality of drain select plugs, wherein the at least two adjacent drain select plugs each have a semi-cylindrical shape and remaining drain select plugs except for the at least two adjacent drain select plugs among the plurality of drain select plugs each have a cylindrical shape.
Inventor(s): Eun Seok CHOI of Icheon-si Gyeonggi-do KR for sk hynix inc., Jae Young OH of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B43/35, H01L23/00, H01L25/00, H01L25/065, H01L25/18, H10B41/27, H10B41/35, H10B43/27, H10B80/00
CPC Code(s): H10B43/35
Abstract: provided herein is a semiconductor memory device and a method of manufacturing the same. the semiconductor memory device includes a channel layer, and a source select line surrounding at least a part of the channel layer. a p-type impurity is locally doped in the part of the channel layer or a gate insulating layer includes a first member interposed between the channel layer and the source select line and aligned with a data storage layer.
Inventor(s): Sun Mi PARK of Icheon-si Gyeonggi-do KR for sk hynix inc., Nam Kuk KIM of Icheon-si Gyeonggi-do KR for sk hynix inc., Eun Mee KWON of Icheon-si Gyeonggi-do KR for sk hynix inc., Sang Wan JIN of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B43/35, H01L25/065, H10B43/27
CPC Code(s): H10B43/35
Abstract: a semiconductor memory device, and a method of manufacturing the same, includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs passing through the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs passing through the upper stack and being in contact with an upper portion of the plurality of cell plugs, and a separation pattern separating adjacent drain select plugs among the plurality of drain select plugs, wherein the separation pattern is in contact with a sidewall of each of the adjacent drain select plugs.
Inventor(s): Tae Jung HA of Icheon-si KR for sk hynix inc.
IPC Code(s): H10B61/00, H10N50/01, H10N50/10
CPC Code(s): H10B61/10
Abstract: in an embodiment, a semiconductor device includes: a variable resistance pattern configured to switch between different resistance states in response to an applied voltage or current; and a selector pattern disposed over the variable resistance pattern and having a lower surface in direct contact with an upper surface of the variable resistance pattern, the selector pattern structured to include an insulating material doped with dopants and to exhibit a threshold switching behavior to exhibit, and selectively switch between, an (1) electrical conducting state of providing an electrical conducting path in the selector pattern, and (2) an electrical non-conducting state of turning off the electrical conducting path in the selector pattern, wherein a sidewall of the variable resistance pattern and a sidewall of the selector pattern are aligned with each other.
20250126906. IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Ji Suk PARK of Icheon-si KR for sk hynix inc.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/80373
Abstract: an image sensing device includes a semiconductor substrate, a photoelectric conversion region supported by the semiconductor substrate and configured to include first-type impurities and generate photocharges, a well region supported by the semiconductor substrate and configured to include second-type impurities and disposed over the photoelectric conversion region to contact the photoelectric conversion region within the semiconductor substrate, a floating diffusion region disposed in the well region and configured to store the photocharges, a transfer gate supported by the semiconductor substrate and configured to include a recess gate buried in the semiconductor substrate and configured to transmit the photocharges generated by the photoelectric conversion region to the floating diffusion region, and a first passivation layer supported by the semiconductor substrate and configured to include the second-type impurities, and covering side surfaces and a bottom surface of the recess gate within the semiconductor substrate.
20250126910. IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Yun Hui YANG of Icheon-si KR for sk hynix inc.
IPC Code(s): H10F39/00, H10F39/18
CPC Code(s): H10F39/8053
Abstract: an image sensing device includes a substrate layer including a plurality of photoelectric conversion elements configured to generate photocharges, a plurality of color filters disposed over the substrate layer, a metal layer disposed between the color filters adjacent to each other, a buffer layer disposed over the metal layer, an air layer disposed over the buffer layer, and a capping layer formed to cover a stacked structure of the metal layer, the buffer layer, and the air layer. a region of the capping layer that covers the air layer is formed to have a larger thickness than the other regions of the capping layer that cover the metal layer and the buffer layer.
Inventor(s): Cha Deok DONG of Icheon-si KR for sk hynix inc.
IPC Code(s): H10N70/00, H10B61/00, H10B63/00, H10N50/01, H10N50/10, H10N50/80
CPC Code(s): H10N70/841
Abstract: a semiconductor device and a method for fabricating the same are provided. the semiconductor device includes: a selector pattern configured to exhibit different electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage; an interlayer insulating layer surrounding a sidewall of the selector pattern and having an opening disposed over the selector pattern; and an electrode disposed in the opening and having a width that is maximum at an uppermost portion of the opening, and wherein the uppermost portion of the opening has a rounded edge in a cross-sectional view.
- SK hynix Inc.
- G01S7/4863
- G01S17/894
- H04N25/78
- CPC G01S7/4863
- Sk hynix inc.
- G06F3/06
- CPC G06F3/0634
- CPC G06F3/064
- CPC G06F3/0658
- CPC G06F3/0659
- G06F11/10
- G06F13/16
- CPC G06F11/1068
- G06T5/10
- CPC G06T5/10
- G11C7/10
- CPC G11C7/1039
- G11C11/4076
- G11C11/408
- G11C11/4091
- CPC G11C11/4076
- G11C29/46
- G11C29/12
- CPC G11C29/46
- G11C29/14
- G11C29/52
- G11C8/06
- G11C8/18
- CPC G11C29/52
- G11C29/00
- G11C29/18
- CPC G11C29/787
- H01L23/528
- H01L21/768
- H01L23/532
- H01L29/06
- CPC H01L23/5283
- H03K5/02
- H03K3/037
- H03K5/00
- H03K5/135
- CPC H03K5/023
- H03L7/099
- H03L7/089
- CPC H03L7/099
- H04N23/84
- H04N17/00
- CPC H04N23/843
- H04N25/709
- H01L23/00
- H01L27/146
- H04N25/42
- CPC H04N25/709
- H10B41/41
- H10B41/30
- H10B43/30
- H10B43/40
- CPC H10B41/41
- H10B43/27
- H10B41/27
- H10B41/35
- H10B43/35
- H10B63/00
- CPC H10B43/27
- G11C16/04
- H10B43/10
- H01L25/00
- H01L25/065
- H01L25/18
- H10B80/00
- CPC H10B43/35
- H10B61/00
- H10N50/01
- H10N50/10
- CPC H10B61/10
- CPC H10F39/80373
- H10F39/00
- H10F39/18
- CPC H10F39/8053
- H10N70/00
- H10N50/80
- CPC H10N70/841