SK hynix Inc. patent applications on April 10th, 2025
Patent Applications by SK hynix Inc. on April 10th, 2025
SK hynix Inc.: 27 patent applications
SK hynix Inc. has applied for patents in the areas of G06F3/06 (7), H10B43/10 (5), H10B41/27 (4), H10B43/27 (4), H10B41/10 (4) H10B43/27 (2), G05F1/575 (1), H03K3/0315 (1), H10F39/811 (1), H10B41/27 (1)
With keywords such as: device, data, configured, signal, structure, memory, direction, region, pixel, and line in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): Hyungrok DO of Icheon-si Gyeonggi-do KR for sk hynix inc., Dae Han KWON of Icheon-si Gyeonggi-do KR for sk hynix inc., Kyu Dong HWANG of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G05F1/575, G11C5/14
CPC Code(s): G05F1/575
Abstract: an electronic device includes an internal voltage generation circuit configured to detect a voltage level of an internal voltage, that is generated by the internal voltage generation circuit. the internal voltage generating circuit is also configured to generate a drive code, which, along with a drive clock, determines the magnitude of the generated internal voltage. the drive code may be reset responsive to the internal voltage. the electronic device also includes a load circuit which is powered by the generated internal voltage.
20250117136. STORAGE DEVICE AND OPERATION METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Kyu Ho CHOI of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: embodiments of the present disclosure relate to a storage device and more particularly to a storage device which processes data for each zone in a device implemented with zone storage, and an operation method of the storage device. according to the embodiments of the present disclosure, remaining blocks generated in each zone are collected and set to an over provisioning area, so that a storage space can be efficiently used. according to the embodiments of the present disclosure, data is separated and written to different zones. also, zone compression is performed on the data written to a specific zone, so that the storage space of the zone storage can be efficiently used.
Inventor(s): In Ho JUNG of Gyeonggi-do KR for sk hynix inc., Min Hwan MOON of Gyeonggi-do KR for sk hynix inc., Seung Gu JI of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: a suspend parameter determination device may include a power monitoring circuit configured to monitor power consumption information of a storage device; a memory device configured to store an artificial intelligence model; and a control circuit configured to load the artificial intelligence model, input to the artificial intelligence model, performance information for the storage device and the power consumption information received from the power monitoring circuit, and transmit, to the storage device, a suspend parameter outputted by the artificial intelligence model.
Inventor(s): Jung Woo KIM of Icheon-si KR for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: a storage device may set a plurality of zones each of which includes one or more memory blocks among a plurality of memory blocks. when a sudden power-off is detected during a write operation for a target zone among the plurality of zones, the storage device may write dummy data to the target zone during a recovery operation for the sudden power-off. when writing data of a size matching that of the dummy data onto the target zone after the dummy data is written, the storage device may write the data to a target memory block in which is outside the target zone.
Inventor(s): Eun Woo JO of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: provided herein are a memory device and a method of operating the memory device. the memory device may include a memory cell array including a plurality of memory cells coupled to a selected word line, a voltage generator configured to generate an operating voltage that is used for an internal operation, a row decoder configured to perform an under-drive operation including decreasing a voltage level of the selected word line and to apply the operating voltage to the selected word line, and control logic configured to control the row decoder to apply a ground voltage to the selected word line during the under-drive operation.
Inventor(s): Chi Je PARK of Gyeonggi-do KR for sk hynix inc., Seung Soo KIM of Gyeonggi-do KR for sk hynix inc., Hyeong Jae CHOI of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: provided herein is a method of operating a host device. the method may include, a determining that read requests for data in a first file are successive, in response to the determination that read requests are successive, generating a first read command that instructs second data to be read ahead, the second data being successive to first data, determining a logical address corresponding to the first read command, providing to a storage device the first read command and the logical address, determining whether a read-ahead request for the first file has been completed, based on a first file pointer and a first offset corresponding to a storage area within the storage device in which the first file is stored, and executing a read-ahead request for a second file in response to the determination that the read-ahead request for the first file has been completed.
Inventor(s): Choung Ki SONG of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/106
Abstract: a semiconductor system includes a controller configured to output a command and address for performing an ecs operation after the start of entry into a power-down operation, receive data and output the data in response to correcting one or more errors occurring in the data, and output a command for performing a self-refresh operation when the ecs operation is terminated, and a semiconductor device configured to output, as the data, internal data stored in multiple memory cells after the start of a read operation of the ecs operation in response to receiving the command and address, receive the data having the one or more errors corrected after the start of a write operation of the ecs operation, store the data having the one or more errors corrected, and perform a self-refresh operation on the multiple memory cells after receiving the command when the ecs operation is terminated.
Inventor(s): Gi Pyo UM of Icheon KR for sk hynix inc.
IPC Code(s): G06F12/02, G06F3/06
CPC Code(s): G06F12/0253
Abstract: a memory system or memory controller may calculate a first data size, which is the sum of sizes of data requested to be written by write requests from outside the memory system after a first reference time point, calculate a second data size, which is the sum of sizes of data updated by the write requests among data already stored in the memory device from a second reference time point, and control execution of garbage collection on data stored in the memory device based on the first data size and the second data size.
20250118368. SYSTEM AND METHOD FOR IN-NAND PATTERN SEARCH_simplified_abstract_(sk hynix inc.)
Inventor(s): Pengfei HUANG of San Jose CA US for sk hynix inc., Fan ZHANG of San Jose CA US for sk hynix inc.
IPC Code(s): G11C15/04, G11C7/10
CPC Code(s): G11C15/046
Abstract: a system and a method for pattern search capable of enabling computation capability inside of a memory device. the memory system searches for a pattern data item in response to a pattern search command, and provide to the host the pattern data item associated with a particular pattern corresponding to the pattern search command. the memory device includes: a decoder configured to receive pattern data item from a plurality of pages, and decode the pattern data item; and a hash comparator configured to compare one or more host hash values with one or more memory hash values, and provide the controller with the decoded pattern data item according to the comparison results between the host hash values and the memory hash values.
20250118387. MEMORY INCLUDING ERROR CORRECTION CIRCUIT_simplified_abstract_(sk hynix inc.)
Inventor(s): Mun Seon JANG of Gyeonggi-do KR for sk hynix inc., Sang Uhn CHA of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C29/42, G11C29/10
CPC Code(s): G11C29/42
Abstract: a memory may include a memory core, a syndrome generation circuit configured to generate a syndrome by using data that are read from the memory core and an error correction code (ecc), a first decoder configured to generate first error correction information by using a first decoding table and the syndrome, a second decoder configured to generate second error correction information by using a second decoding table different from the first decoding table and the syndrome, and an error correction circuit configured to correct an error of the read data by using the first error correction information and the second error correction information.
Inventor(s): Hong Gu LEE of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H01L21/033, H01L21/311, H01L23/13
CPC Code(s): H01L21/0337
Abstract: a mask pattern may include a first spacer and a second spacer. the first spacer may be formed over a layer. the second spacer may be formed over the first spacer. the first spacer and the second spacer may define a mesh structure having a plurality of opened regions. the opened regions may be etched to form a hole array region and a plurality of dummy holes in the layer. the hole array region may include a plurality of holes. the dummy holes may be configured to surround the hole array.
Inventor(s): Yun Cheol HAN of Gyeonggi-do KR for sk hynix inc., Hye In YEOM of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H01L23/528, H01L23/522, H10B41/10, H10B41/27, H10B43/10, H10B43/27
CPC Code(s): H01L23/5283
Abstract: a semiconductor device may include a first gate structure including stacked first selection lines, each first selection line including a first cell region and a first pad region adjacent in a first direction, a second gate structure including stacked second selection lines, each second selection line including a second cell region and a second pad region adjacent in the first direction, first contact plugs extending through the first pad region and respectively connected to the first selection lines, and second contact plugs extending through the second pad region and respectively connected to the second selection lines, and in a second direction crossing the first direction, the first pad region may have a width greater than that of the first cell region, and the second pad region may have a width greater than that of the first pad region.
20250118686. MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Hwae Bong JUNG of Icheon-si Gyeonggi-do KR for sk hynix inc., Jae Seok KIM of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H01L23/60, H01L29/08, H01L29/417, H10B43/10, H10B43/20, H10B43/40, H10B43/50
CPC Code(s): H01L23/60
Abstract: a memory device, and a method of manufacturing the same, includes a discharge contact, a source pattern surrounding a periphery of the discharge contact and floated, and a source line surrounding a periphery of the source pattern and to which a source voltage is applied. the memory device also includes a separation pattern electrically isolating the source pattern and the source line, main support patterns positioned on the source pattern, sub support patterns positioned on the source line, and a contact positioned on the discharge contact.
Inventor(s): Heon Yong CHANG of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H01L25/18, H01L21/78, H01L23/00, H01L23/29, H01L23/31, H01L23/58, H01L25/00, H10B80/00
CPC Code(s): H01L25/18
Abstract: a semiconductor device includes a first chip having a first chip body and a first bonding layer which is disposed on the first chip body and includes a first bonding pad; and a second chip bonded on the first bonding layer, and having a second chip body and a second bonding layer which is disposed under the second chip body and includes a second bonding pad bonded to the first bonding pad, wherein a side surface of the first bonding layer and a side surface of the second chip are retracted inward of a side surface of the first chip body.
Inventor(s): Dong Beom LEE of Icheon-si Gyeonggi-do KR for sk hynix inc., Hyeong Soo JEONG of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H03K3/03, G06F3/06
CPC Code(s): H03K3/0315
Abstract: an electronic device may include: a control pulse generation circuit configured to selectively generate one of a first control pulse and a second control pulse on the basis of a reference code during a test period; and a voltage control code generation circuit configured to perform an addition operation or subtraction operation on a logic bit set of a voltage control code to set the voltage level of an operation voltage on the basis of the first and second control pulses.
Inventor(s): Hyun Su PARK of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H03K17/56, H03K3/037, H03L7/06
CPC Code(s): H03K17/56
Abstract: a receiver circuit is configured to generate a reception symbol from a multi-level signal. the receiver circuit is configured to generate three compensation signal pairs from an input signal pair to perform a loop unrolled decision feedback equalization operation. a first summing circuit is configured to equalize the input signal pair with a first offset to generate a first compensation signal pair, and a second summing circuit is configured to equalize the input signal pair with a second offset to generate a second compensation signal pair. an averaging circuit is configured to average the first compensation signal pair and the second compensation signal pair to generate a third compensation signal pair.
20250119170. RECEIVER CIRCUIT_simplified_abstract_(sk hynix inc.)
Inventor(s): Bo Ram KIM of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H04B1/16, H04B1/18
CPC Code(s): H04B1/1607
Abstract: a receiver circuit includes a first buffer, a second buffer, and a sampling circuit. the first buffer receives a multi-level signal according to a first reference voltage to generate a first input signal. the second buffer receives the multi-level signal according to a second reference voltage to generate a second input signal. the sampling circuit samples each of the first input signal and the second input signal according to a first equalization method and a second equalization method, respectively, and outputs at least one of a first sampling result value according to the first equalization method and a second sampling result value according to the second equalization method according to a logic value of a previously input multi-level signal.
20250119655. IMAGE SENSING DEVICE AND IMAGING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Won Seok HWANG of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H04N25/583, H04N25/533, H04N25/585, H04N25/77
CPC Code(s): H04N25/583
Abstract: an image sensing device for generating a high dynamic range (hdr) image is disclosed. the image sensing device includes a first pixel configured to generate a first pixel signal based on light received during a first exposure time, and a second pixel configured to share a floating diffusion region with the first pixel and to generate a second pixel signal based on light received during a second exposure time different from the first exposure time. when the floating diffusion region is reset based on a pixel reset signal in a first period, a reset signal is read out, the first pixel signal is read out in a second period, and the second pixel signal is read out in a third period. the first period, the second period, and the third period are included in one frame.
20250119658. IMAGING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Ken SAWADA of Tokyo JP for sk hynix inc., Daisuke SHIRAISHI of Tokyo JP for sk hynix inc., Sung Kyu LEE of Tokyo JP for sk hynix inc.
IPC Code(s): H04N25/67, G06T5/70, G06T7/90, H04N25/11
CPC Code(s): H04N25/67
Abstract: an imaging device is provided to include a physical unclonable function (puf) pixel selection unit configured to identify a first pixel that is designated to generate puf data and select a second pixel having a color identical to a color of the first pixel, a noise extraction unit coupled to the puf pixel selection unit to receive information of the first pixel and the second pixel and configured to extract a first noise value of the first pixel and a second noise value of the second pixel, and a puf data generation unit coupled to the noise extraction unit and configured to generate the puf data based on the first noise value and the second noise value from the noise extraction unit.
20250119661. IMAGE SENSING DEVICE INCLUDING TEST PATTERN_simplified_abstract_(sk hynix inc.)
Inventor(s): Gon Ji LEE of Icheon-si KR for sk hynix inc.
IPC Code(s): H04N25/69, H01L27/146, H04N25/78
CPC Code(s): H04N25/69
Abstract: an image sensing device includes a pixel array including pixel units that include first pixel transistors located in different rows of the pixel array; first upper signal lines respectively connected to the first pixel transistors; a first test line commonly connected to the first upper signal lines; a first test pad connected to the first test line and configured to provide a first test signal to the first test line; and a first test transistor connected to the first test line and the first test pad and configured to enable or disable a test operation by selectively providing the first test signal to the first test line. during the test operation, the first test signal may be provided to the first pixel transistors located in different rows of the pixel array through the first test transistor, the first test line, and the first upper signal lines.
Inventor(s): Dong Il SONG of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/30
Abstract: a method of manufacturing a semiconductor device may include forming a vertical stack comprising a plurality of recess target layers spaced apart from each other in a first direction over a lower structure; forming preliminary horizontal layers by recessing the recess target layers in a second direction perpendicular to the first direction; forming dielectric target layers on the preliminary horizontal layers; forming conductive target layers on the dielectric target layers; forming an inter-level dielectric layer by trimming the dielectric target layers in a third direction that intersects the second direction; forming horizontal layers by trimming the preliminary horizontal layers in the third direction; and forming trimmed target layers by trimming the conductive target layers in the third direction.
Inventor(s): Jun Sik KIM of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/488
Abstract: a semiconductor device includes a plurality of semiconductor pillars having first and second sides facing each other in a first direction, and arranged in a second direction crossing the first direction; a plurality of insulating pillars having first and second sides facing each other in the first direction, and arranged alternately with the semiconductor pillars in the second direction; a back gate line formed on the first sides of the semiconductor pillars and the first sides of the insulating pillars, and extending in the second direction; and a front gate line formed on the second sides of the semiconductor pillars and the second sides of the insulating pillars, and extending in the second direction, wherein the semiconductor pillars respectively include protrusion portions that protrude more than the insulating pillars toward the front gate line in the first direction, and the front gate line surrounds a side of the protrusion portion.
20250120075. MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Nam Jae LEE of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B41/27, G11C5/06, H01L23/528, H10B41/10, H10B43/10, H10B43/27
CPC Code(s): H10B41/27
Abstract: a memory device, and a method of manufacturing the same, includes a gate stack formed on a cell region and a pass transistor region, a plurality of cell plugs extending in a vertical direction in the gate stack of the cell region, a plurality of gate contact structures extending in the vertical direction by passing through the gate stack of the pass transistor region, and a plurality of pass transistors connected to the plurality of respective gate contact structures. each of the plurality of pass transistors has a cylindrical shape structure.
Inventor(s): Nam Jae LEE of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/10, H10B41/27, H10B43/10, H10B63/00
CPC Code(s): H10B43/27
Abstract: a semiconductor device may include a gate structure including gate lines and insulating layers alternately stacked, a channel structure extending through the gate structure and including a channel layer and a channel pad connected to the channel layer, a dummy gate structure including stacked dummy gate lines, a dummy channel structure extending through the dummy gate structure and including a dummy channel layer and a dummy channel pad connected to the dummy channel layer, an isolation insulating layer disposed between the gate structure and the dummy gate structure, and a dummy pad disposed on the isolation insulating layer between the gate structure and the dummy gate structure.
Inventor(s): Jin Ho KIM of Icheon-si KR for sk hynix inc., Sang Hyun SUNG of Icheon-si KR for sk hynix inc., Go Hyun LEE of Icheon-si KR for sk hynix inc., Byung Hyun JEON of Icheon-si KR for sk hynix inc.
IPC Code(s): H10B43/27, H01L23/522, H01L23/528, H10B41/10, H10B41/27, H10B41/40, H10B43/10, H10B43/40
CPC Code(s): H10B43/27
Abstract: a three-dimensional memory device includes first and second isolation patterns extending in a first direction, and adjacent to each other in a second direction intersecting with the first direction; a stack disposed between the first isolation pattern and the second isolation pattern, and including a connection region including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction and an insulating region surrounded by the connection region; and a plurality of stairway-shaped recesses configured in the insulating region and the connecting region, and arranged in the first direction, wherein at least one of the plurality of stairway-shaped recesses comprises a first stairway structure connected to the first isolation pattern, a second stairway structure connected to the second isolation pattern, and a sidewall connecting the first stairway structure and the second stairway structure and disposed in the insulating region.
Inventor(s): Nam Jae LEE of Icheon-si KR for sk hynix inc.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/811
Abstract: disclosed is a method for manufacturing a semiconductor device, including: forming a first semiconductor structure comprising a logic transistor; forming a second semiconductor structure; bonding the first semiconductor structure to the second semiconductor structure, wherein forming the first semiconductor structure comprises: forming a first substrate; forming a first wiring layer comprising a plurality of first metal wirings and a plurality of first vias on the first substrate; forming a first bonding isolation layer on the first wiring layer, wherein forming the second semiconductor structure comprises: forming a second substrate; forming a second wiring layer comprising a plurality of second metal wirings and a plurality of second vias on the second substrate; forming a plurality of dummy plugs in the second wiring layer, forming a plurality of holes vertically penetrating the second substrate to a section in which the plurality of dummy plugs form, wherein the plurality of holes form after bonding the first semiconductor structure to the second semiconductor structure; and removing the dummy plugs.
Inventor(s): Seong Hyun KIM of Icheon-si KR for sk hynix inc., Min Su KIM of Icheon-si KR for sk hynix inc., Jae Sung PARK of Icheon-si KR for sk hynix inc., Cheol Joon PARK of Icheon-si KR for sk hynix inc.
IPC Code(s): H10N70/00, H10B63/00
CPC Code(s): H10N70/841
Abstract: a semiconductor device may include an access line, a variable resistance layer, an electrode located between the access line and the variable resistance layer, and a barrier structure located between the access line and the electrode and including an amorphous barrier. the barrier structure may further include a diffusion barrier, and the amorphous barrier has a resistivity higher than that of the diffusion barrier.
- SK hynix Inc.
- G05F1/575
- G11C5/14
- CPC G05F1/575
- Sk hynix inc.
- G06F3/06
- CPC G06F3/0613
- CPC G06F3/0625
- CPC G06F3/064
- CPC G06F3/0655
- CPC G06F3/0659
- G06F11/10
- CPC G06F11/106
- G06F12/02
- CPC G06F12/0253
- G11C15/04
- G11C7/10
- CPC G11C15/046
- G11C29/42
- G11C29/10
- CPC G11C29/42
- H01L21/033
- H01L21/311
- H01L23/13
- CPC H01L21/0337
- H01L23/528
- H01L23/522
- H10B41/10
- H10B41/27
- H10B43/10
- H10B43/27
- CPC H01L23/5283
- H01L23/60
- H01L29/08
- H01L29/417
- H10B43/20
- H10B43/40
- H10B43/50
- CPC H01L23/60
- H01L25/18
- H01L21/78
- H01L23/00
- H01L23/29
- H01L23/31
- H01L23/58
- H01L25/00
- H10B80/00
- CPC H01L25/18
- H03K3/03
- CPC H03K3/0315
- H03K17/56
- H03K3/037
- H03L7/06
- CPC H03K17/56
- H04B1/16
- H04B1/18
- CPC H04B1/1607
- H04N25/583
- H04N25/533
- H04N25/585
- H04N25/77
- CPC H04N25/583
- H04N25/67
- G06T5/70
- G06T7/90
- H04N25/11
- CPC H04N25/67
- H04N25/69
- H01L27/146
- H04N25/78
- CPC H04N25/69
- H10B12/00
- CPC H10B12/30
- CPC H10B12/488
- G11C5/06
- CPC H10B41/27
- H10B63/00
- CPC H10B43/27
- H10B41/40
- CPC H10F39/811
- H10N70/00
- CPC H10N70/841
