SK hynix Inc. (20250118387). MEMORY INCLUDING ERROR CORRECTION CIRCUIT
MEMORY INCLUDING ERROR CORRECTION CIRCUIT
Organization Name
Inventor(s)
Mun Seon Jang of Gyeonggi-do KR
Sang Uhn Cha of Gyeonggi-do KR
MEMORY INCLUDING ERROR CORRECTION CIRCUIT
This abstract first appeared for US patent application 20250118387 titled 'MEMORY INCLUDING ERROR CORRECTION CIRCUIT
Original Abstract Submitted
a memory may include a memory core, a syndrome generation circuit configured to generate a syndrome by using data that are read from the memory core and an error correction code (ecc), a first decoder configured to generate first error correction information by using a first decoding table and the syndrome, a second decoder configured to generate second error correction information by using a second decoding table different from the first decoding table and the syndrome, and an error correction circuit configured to correct an error of the read data by using the first error correction information and the second error correction information.