SK HYNIX INC. patent applications on May 8th, 2025
Patent Applications by SK HYNIX INC. on May 8th, 2025
SK HYNIX INC.: 21 patent applications
SK HYNIX INC. has applied for patents in the areas of H01L23/00 (4), H10B43/27 (3), H10B43/40 (2), H01L27/146 (2), H01L25/065 (2) C09G1/02 (1), H01L25/0657 (1), H10F39/8063 (1), H10F39/8033 (1), H10B80/00 (1)
With keywords such as: memory, device, region, layer, semiconductor, gate, structure, circuit, configured, and signal in patent application abstracts.
Patent Applications by SK HYNIX INC.
Inventor(s): Sun Joo PARK of Gyeonggi-do KR for sk hynix inc., Doc Jin KIM of Gyeonggi-do KR for sk hynix inc., Jeong Woo HONG of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G01N27/20, H01L21/66, H01L23/528, H01L23/58, H01L29/06
CPC Code(s): G01N27/20
Abstract: a semiconductor device includes a guard ring, a crack detecting circuit, and a conductive sensing line over a semiconductor substrate. the guard ring is electrically connected to a first impurity-doped region of the semiconductor substrate. the conductive sensing line is disposed at a location isolated from the crack detecting circuit with the guard ring interposed therebetween, and is extended along the guard ring and formed in a shape in which both ends of the conductive sensing line are spaced apart from each other. the semiconductor substrate includes a second impurity-doped region buried in the first impurity-doped region and extended to pass under the guard ring, a third impurity-doped region that penetrates the first impurity-doped region so that the third impurity-doped region electrically connects the conductive sensing line to the second impurity-doped region, and a fourth impurity-doped region that electrically connects the crack detecting circuit to the second impurity-doped region.
20250147543. INTERFACE DEVICE AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Yo Han HONG of Icheon-si KR for sk hynix inc., Dae Sik PARK of Icheon-si KR for sk hynix inc.
IPC Code(s): G06F1/08
CPC Code(s): G06F1/08
Abstract: the present disclosure relates to a semiconductor device. a device in communication with a host device via an interface according to the present disclosure includes a clock signal generator configured to generate a first reference clock signal to be used by the device, and a reference clock signal selection circuit coupled to be in communication with the clock signal generator to receive the first reference clock signal and configured to receive a second reference clock signal from the host device, and configured to, in response to a first reset signal received first among a plurality of reset signals from the host device, select one of the first reference clock signal and the second reference clock signal according to whether the second reference clock signal is provided from the host device.
Inventor(s): Fan Zhang of Fremont CA US for sk hynix inc., Meysam Asadi of San Jose CA US for sk hynix inc., Haobo Wang of San Jose CA US for sk hynix inc.
IPC Code(s): G06F3/06, G06N3/048
CPC Code(s): G06F3/0611
Abstract: devices, systems, and methods for improving performance of a memory device are described. an example method includes extracting parameters, which include a read threshold set, from each of a first set of host reads, replacing, based on the parameters, at least one host read from a second set of host reads by at least one host read from the first set of host reads, using a deep neural network (dnn) to generate an updated read threshold set, wherein an input to the dnn comprises the parameters from each of the second set of host reads subsequent to the replacing, and applying the updated read threshold set to the memory device to retrieve information from the memory device. in an example, the number of the first set of host reads is at least two orders of magnitude greater than the number of the second set of host reads.
20250147839. MEMORY SYSTEM AND DECODING METHOD FOR THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Bi Woong CHUNG of Gyeonggi-do KR for sk hynix inc., Dae Sung KIM of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1004
Abstract: a method for decoding a memory system, the method may include establishing a plurality of check nodes and a plurality of variable nodes corresponding to the plurality of check nodes of a codeword; setting a preliminary operation speed based on a progress rate of a preliminary operation for generating predictive error information of each of the plurality of the variable nodes; performing the preliminary operation according to the preliminary operation speed; and performing a main decoding operation for error correction on at least a part of the plurality of the variable nodes based on the predictive error information.
Inventor(s): Hyun Chul CHO of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C5/14
CPC Code(s): G11C5/147
Abstract: a semiconductor apparatus includes an internal voltage generation circuit and a control circuit. the internal voltage generation circuit includes a plurality of sub-circuits that receive an external voltage as an input and generate at least one internal voltage based on the external voltage. the control circuit determines where the external voltage falls within a range between a minimum operating voltage and a target operating voltage according to power information and a built-in lookup table and controls the plurality of sub-circuits according to a result of the determination.
20250149095. MEMORY DEVICE AND METHOD OF OPERATING THE SAME_simplified_abstract_(sk hynix inc.)
Inventor(s): Chang Beom WOO of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): G11C16/16, G11C16/04, G11C16/08
CPC Code(s): G11C16/16
Abstract: a memory device and a method of operating the same are provided. the memory device may include a memory block including a plurality of memory cells, peripheral circuits configured to perform an erase operation including a gate induced drain leakage (gidl) current generation operation and a data erase operation using an gidl current on the memory block, and control logic configured to control the peripheral circuits to perform the erase operation, wherein the control logic is configured to control the peripheral circuits to apply a negative voltage to word lines of the memory block during the gidl current generation operation.
Inventor(s): Hee Joung PARK of Gyeonggi-do KR for sk hynix inc., Chang Han SON of Gyeonggi-do KR for sk hynix inc., Hyun Seob SHIN of Gyeonggi-do KR for sk hynix inc., Myung Su KIM of Gyeonggi-do KR for sk hynix inc., Sung Hun KIM of Gyeonggi-do KR for sk hynix inc., Kang Woo PARK of Gyeonggi-do KR for sk hynix inc., Ming ZHANG of Rancho Cordova CA US for sk hynix inc., Yogesh WAKCHAURE of Rancho Cordova CA US for sk hynix inc., Curtis GITTENS of Rancho Cordova CA US for sk hynix inc., Zion KWOK of Rancho Cordova CA US for sk hynix inc., Bing XIAO of Rancho Cordova CA US for sk hynix inc., Hui-chun WU of Rancho Cordova CA US for sk hynix inc.
IPC Code(s): G11C29/44
CPC Code(s): G11C29/44
Abstract: a memory system comprising a memory device including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches coupled to the bit lines, and configured to program input data stored in the latches into memory cells of a selected word line during a program operation, and output, as information data, at least one or more data among first data stored in the latches and second data stored in the memory cells of the selected word line during a program suspend operation for suspending the program operation, and a controller configured to repair the input data by performing a set logic operation on the information data from the memory device, and apply the set logic operation whose type is different according to an execution moment of the program suspend operation.
Inventor(s): Nam Jae LEE of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H01L23/528, H01L23/00, H10B43/27, H10D64/23
CPC Code(s): H01L23/528
Abstract: provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. the semiconductor memory device includes a source structure, a stacked conductive layer that overlaps with the source structure, a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer, a stacked insulating layer disposed between the first and second select conductive layers and the stacked conductive layer, and a separation insulating structure provided between the first select conductive layer and the second select conductive layer.
Inventor(s): Hyun Chul SEO of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/11
Abstract: a semiconductor device including bumps and a method of manufacturing the same. the semiconductor device includes a first pillar and a second pillar formed over a substrate, a first solder layer configured to cover a first surface of the first pillar, and a second solder layer configured to cover a second surface of the second pillar. the first surface of the first pillar has a lower height than a height of the second surface of the second pillar. the second solder layer has a smaller thickness than a thickness of the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface.
Inventor(s): Jae Min KIM of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H01L25/065, H01L23/00, H01L23/29, H01L23/31
CPC Code(s): H01L25/0657
Abstract: a semiconductor package includes a bonding wire which is connected to a semiconductor chip. a first encapsulation layer which surrounds the bonding wire is disposed. a second encapsulation layer which surrounds the first encapsulation layer is disposed. a surface roughness of the first encapsulation layer is less than that of the second encapsulation layer. a landing pad which contacts the bonding wire is disposed.
Inventor(s): Gwan Woo KIM of Icheon-si Gyeonggi-do KR for sk hynix inc., In Seok KONG of Icheon-si Gyeonggi-do KR for sk hynix inc., Keun Seon AHN of Icheon-si Gyeonggi-do KR for sk hynix inc., Sung Hwa OK of Icheon-si Gyeonggi-do KR for sk hynix inc., Eun Ji CHOI of Icheon-si Gyeonggi-do KR for sk hynix inc., Jae Hyeong HONG of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H03K5/01, H03K3/017, H03K19/00
CPC Code(s): H03K5/01
Abstract: a transmission circuit includes a plurality of driving units coupled with an input/output pad. the transmission circuit performs a data transmission operation by selecting at least one main driving unit corresponding to a predetermined driving strength from among the plurality of driving units and performs an equalization operation by selecting at least one auxiliary driving unit from among remaining driving units excluding the main driving unit.
Inventor(s): Hyun Bae LEE of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H03K19/0185, H03K3/017, H03K19/20
CPC Code(s): H03K19/018507
Abstract: a transmission and reception system includes a transmission circuit and a reception circuit. the transmission circuit is configured to generate a transmission signal based on an input signal. the reception circuit is configured to generate an output signal based on the transmission signal. the transmission circuit is configured to provide a duty cycle offset which is complementary with a duty cycle offset of the reception circuit.
Inventor(s): Bi Woong CHUNG of Gyeonggi-do KR for sk hynix inc., Dae Sung KIM of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H03M13/11
CPC Code(s): H03M13/1128
Abstract: a memory system includes a memory device and a controller. the memory device is configured to output a codeword. the controller is configured to establish, from the codeword, a plurality of variable nodes and a plurality of check nodes, and schedule a decoding operation to ensure that a number of check-sum updates during one cycle of the decoding operation does not exceed a threshold set to be less than a number of the check nodes, wherein the decoding operation includes iterative operations, and each iterative operation includes plural sub-iterative operations.
20250151270. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Sung Wook JUNG of Icheon-si Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/10, H10B41/27, H10B41/40, H10B43/10, H10B43/40
CPC Code(s): H10B43/27
Abstract: there is provided a semiconductor memory device and a method of manufacturing the same. the semiconductor memory device includes a first gate stacked body including a first channel hole, a second gate stacked body overlapping the first gate stacked body and including a second channel hole, a first memory layer extending along an inner wall of the first channel hole, a second memory layer extending along an inner wall of the second channel hole and including an end protruding into the first channel hole.
Inventor(s): Nam Jae LEE of Cheongju-si Chungcheongbuk-do KR for sk hynix inc.
IPC Code(s): H10B43/40, H10B41/27, H10B41/41, H10B43/27
CPC Code(s): H10B43/40
Abstract: there is provided a semiconductor memory device including: a substrate having a complementary metal oxide semiconductor (cmos) circuit; a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on the substrate; a channel structure having a first part penetrating the gate stack structure and a second part extending from one end of the first part, the second part extending beyond the gate stack structure; a common source line extending to overlap with the gate stack structure, the common source line surrounding the second part of the channel structure; a memory layer disposed between the first part of the channel structure and the gate stack structure; and a bit line connected to the other end of the first part of the channel structure, the bit line being disposed between the substrate and the gate stack structure.
Inventor(s): Sang Soo LEE of Gyeonggi-do KR for sk hynix inc., Jae Hyun HAN of Gyeonggi-do KR for sk hynix inc.
IPC Code(s): H10B80/00, H01L23/00, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H10B80/00
Abstract: a semiconductor device may include stacked first gate lines, stacked second gate lines, a channel structure extending through the first gate lines and the second gate lines, first contact plugs extending through the first gate lines and respectively connected to front surfaces of the first gate lines, and second contact plugs extending through the second gate lines and respectively connected to rear surfaces of the second gate lines.
20250151429. SINGLE PHOTON AVALANCHE DIODE_simplified_abstract_(sk hynix inc.)
Inventor(s): Soon Yeol PARK of Icheon-si KR for sk hynix inc.
IPC Code(s): H10F39/00, G01S7/481, G01S7/4865, G01S17/894
CPC Code(s): H10F39/8033
Abstract: a single photon avalanche diode may include a first diode, a second diode and a third diode. the first diode includes a first pn junction vertically spaced from a light-receiving surface by a first depth. the second diode is formed to be partially contacted with the first diode. the second diode includes a second pn junction vertically spaced from the light-receiving surface by a second depth greater than the first depth. the third diode is formed to be partially contacted with the second diode. the third diode includes a third pn junction spaced from the light-receiving surface by a third depth greater than the second depth. the first to third diodes include different breakdown voltages.
Inventor(s): Han Jun KIM of Icheon-si KR for sk hynix inc.
IPC Code(s): H01L27/146, B82Y20/00, G06F30/27, G06F111/14
CPC Code(s): H10F39/8063
Abstract: image sensing devices including meta lenses and methods for manufacturing the image sensing devices are disclosed. in an embodiments, an image sensing device includes a plurality of microlenses including first to fourth microlenses arranged in a (2�2) matrix structure, a plurality of optical filters disposed under the first to fourth microlens, and configured to correspond to the first to fourth microlenses, one microlens per optical filter, respectively, and an optical element disposed at a center of the (2�2) matrix structure among the first to fourth microlenses and configured to separate incident light into light rays of in different wavelength ranges of different colors to guide each of the light rays to one of the plurality of optical filters of a corresponding color.
20250151439. IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Sung Wook CHO of Icheon-si KR for sk hynix inc.
IPC Code(s): H01L27/146
CPC Code(s): H10F39/807
Abstract: disclosed is an image sensing device, including: a pixel array that includes a plurality of unit pixels. a unit pixel in the pixel array may include a plurality of sub-pixels, a first isolation region may be formed in an edge region of a sub-pixel, a second isolation region may extend from the first isolation region toward a central portion of the sub-pixel, the second isolation region may include: a first inner isolation region protruding in a first direction from one region of the first isolation region to the central portion of the sub-pixel, and a second inner isolation region formed on a same straight line as the first inner isolation region and protruding in a second direction from another region of the first isolation region to the central portion of the sub-pixel, and the first inner isolation region and the second inner isolation region may have sharp end portions.
- SK HYNIX INC.
- G01N27/20
- H01L21/66
- H01L23/528
- H01L23/58
- H01L29/06
- CPC G01N27/20
- Sk hynix inc.
- G06F1/08
- CPC G06F1/08
- G06F3/06
- G06N3/048
- CPC G06F3/0611
- G06F11/10
- CPC G06F11/1004
- G11C5/14
- CPC G11C5/147
- G11C16/16
- G11C16/04
- G11C16/08
- CPC G11C16/16
- G11C29/44
- CPC G11C29/44
- H01L23/00
- H10B43/27
- H10D64/23
- CPC H01L23/528
- CPC H01L24/11
- H01L25/065
- H01L23/29
- H01L23/31
- CPC H01L25/0657
- H03K5/01
- H03K3/017
- H03K19/00
- CPC H03K5/01
- H03K19/0185
- H03K19/20
- CPC H03K19/018507
- H03M13/11
- CPC H03M13/1128
- H10B41/10
- H10B41/27
- H10B41/40
- H10B43/10
- H10B43/40
- CPC H10B43/27
- H10B41/41
- CPC H10B43/40
- H10B80/00
- H01L25/00
- H01L25/18
- CPC H10B80/00
- H10F39/00
- G01S7/481
- G01S7/4865
- G01S17/894
- CPC H10F39/8033
- H01L27/146
- B82Y20/00
- G06F30/27
- G06F111/14
- CPC H10F39/8063
- CPC H10F39/807