SEMICONDUCTOR ENERGY LABORATORY CO., LTD. patent applications on May 8th, 2025
Patent Applications by SEMICONDUCTOR ENERGY LABORATORY CO., LTD. on May 8th, 2025
SEMICONDUCTOR ENERGY LABORATORY CO., LTD.: 37 patent applications
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. has applied for patents in the areas of H10D30/67 (12), H10D86/60 (11), H10D86/40 (11), G02F1/1333 (7), H10K59/12 (7) H10B80/00 (2), G09F9/30 (2), H10D86/60 (2), H10D30/6755 (2), H10D86/0212 (1)
With keywords such as: layer, semiconductor, device, transistor, provided, display, region, oxide, insulating, and third in patent application abstracts.
Patent Applications by SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor(s): Shunpei YAMAZAKI of Tokyo JP for semiconductor energy laboratory co., ltd., Tetsunori MARUYAMA of Atsugi JP for semiconductor energy laboratory co., ltd., Yuki IMOTO of Atsugi JP for semiconductor energy laboratory co., ltd., Hitomi SATO of Isehara JP for semiconductor energy laboratory co., ltd., Masahiro WATANABE of Tochigi JP for semiconductor energy laboratory co., ltd., Mitsuo MASHIYAMA of Oyama JP for semiconductor energy laboratory co., ltd., Kenichi OKAZAKI of Tochigi JP for semiconductor energy laboratory co., ltd., Motoki NAKASHIMA of Atsugi JP for semiconductor energy laboratory co., ltd., Takashi SHIMAZU of Tokyo JP for semiconductor energy laboratory co., ltd.
IPC Code(s): C23C14/34, B28B11/24, C04B35/453, C04B35/64, C23C14/08, H01L21/02, H10D30/67, H10D62/80, H10D99/00
CPC Code(s): C23C14/3414
Abstract: there have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. an oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. the target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
20250147353. Display Device_simplified_abstract_(semiconductor energy laboratory co., ltd.)
Inventor(s): Satohiro OKAMOTO of Atsugi JP for semiconductor energy laboratory co., ltd., Yasuyuki Arai of Atsugi JP for semiconductor energy laboratory co., ltd., Ikuko Kawamata of Atsugi JP for semiconductor energy laboratory co., ltd., Atsushi Miyaguchi of Atsugi JP for semiconductor energy laboratory co., ltd., Yoshitaka Moriya of Sagamihara JP for semiconductor energy laboratory co., ltd.
IPC Code(s): G02F1/1333, G02F1/1345, G02F1/167, G06F3/041, G09G3/20, G09G3/3208, G09G3/36, G09G5/00, G09G5/39, H05K1/18, H10D86/40, H10D86/60
CPC Code(s): G02F1/133305
Abstract: the display device includes: a flexible display panel including a display portion in which scanning lines and signal lines cross each other; a supporting portion for supporting an end portion of the flexible display panel; a signal line driver circuit for outputting a signal to the signal line, which is provided for the supporting portion; and a scanning line driver circuit for outputting a signal to the scanning line, which is provided for a flexible surface of the display panel in a direction which is perpendicular or substantially perpendicular to the supporting portion.
Inventor(s): Shunpei YAMAZAKI of Tokyo JP for semiconductor energy laboratory co., ltd., Daisuke Kubota of Atsugi JP for semiconductor energy laboratory co., ltd., Naoto Kusumoto of Isehara JP for semiconductor energy laboratory co., ltd.
IPC Code(s): G02F1/1335, F21S2/00, G02B5/30, G02F1/1333, G02F1/1347, G09F9/00, G09G3/00, G09G3/20, G09G3/32, G09G3/3233, G09G3/36, H10F55/10
CPC Code(s): G02F1/1335
Abstract: a display device includes a first region and a second region adjacent to the first region. a display element included in the first region has a function of reflecting visible light and a function of emitting visible light. a display element included in the second region has a function of emitting visible light. in an electronic device including the display device, the first region is located on a first surface (e.g., top surface) on which a main image is displayed, and the second region is located on a second surface (e.g., side surface) on which an auxiliary image is displayed.
Inventor(s): Yasuharu HOSAKA of Tochigi JP for semiconductor energy laboratory co., ltd., Yukinori SHIMA of Tatebayashi JP for semiconductor energy laboratory co., ltd., Kenichi OKAZAKI of Tochigi JP for semiconductor energy laboratory co., ltd., Shunpei YAMAZAKI of Tokyo JP for semiconductor energy laboratory co., ltd.
IPC Code(s): G02F1/1368, G02F1/1333, G02F1/1335, G02F1/1337, G02F1/1345, G02F1/1362, H10D86/40, H10D86/60
CPC Code(s): G02F1/1368
Abstract: the display device includes a first substrate provided with a driver circuit region that is located outside and adjacent to a pixel region and includes at least one second transistor which supplies a signal to the first transistor in each of the pixels in the pixel region, a second substrate facing the first substrate, a liquid crystal layer between the first substrate and the second substrate, a first interlayer insulating film including an inorganic insulating material over the first transistor and the second transistor, a second interlayer insulating film including an organic insulating material over the first interlayer insulating film, and a third interlayer insulating film including an inorganic insulating material over the second interlayer insulating film. the third interlayer insulating film is provided in part of an upper region of the pixel region, and has an edge portion on an inner side than the driver circuit region.
20250147552. Electronic Book_simplified_abstract_(semiconductor energy laboratory co., ltd.)
Inventor(s): Shunpei YAMAZAKI of Tokyo JP for semiconductor energy laboratory co., ltd., Jun KOYAMA of Sagamihara JP for semiconductor energy laboratory co., ltd., Yasuyuki ARAI of Atsugi JP for semiconductor energy laboratory co., ltd., Ikuko KAWAMATA of Atsugi JP for semiconductor energy laboratory co., ltd., Atsushi MIYAGUCHI of Atsugi JP for semiconductor energy laboratory co., ltd., Yoshitaka MORIYA of Atsugi JP for semiconductor energy laboratory co., ltd.
IPC Code(s): G06F1/16, G02F1/1333, G02F1/1345, G02F1/1368, G06F3/14, G06F3/147, G09G3/00, G09G3/20, G09G3/3225, G09G3/34, G09G3/36, G09G5/00
CPC Code(s): G06F1/1652
Abstract: an e-book reader in which destruction of a driver circuit at the time when a flexible panel is handled is inhibited. in addition, an e-book reader having a simplified structure. a plurality of flexible display panels each including a display portion in which display control is performed by a scan line driver circuit and a signal line driver circuit, and a binding portion fastening the plurality of display panels together are included. the signal line driver circuit is provided inside the binding portion, and the scan line driver circuit is provided at the edge of the display panel in a direction perpendicular to the binding portion.
20250147587. ELECTRONIC DEVICE_simplified_abstract_(semiconductor energy laboratory co., ltd.)
Inventor(s): Hiromichi GODO of Isehara JP for semiconductor energy laboratory co., ltd., Yoshiyuki KUROKAWA of Sagamihara JP for semiconductor energy laboratory co., ltd., Seiko INOUE of Atsugi JP for semiconductor energy laboratory co., ltd., Kazuaki OHSHIMA of Atsugi JP for semiconductor energy laboratory co., ltd., Shunpei YAMAZAKI of Setagaya JP for semiconductor energy laboratory co., ltd.
IPC Code(s): G06F3/01, G06T1/20, G06T7/73, G06V10/141, G06V40/18, H04N23/611, H04N23/617, H04N23/90
CPC Code(s): G06F3/013
Abstract: an electronic device that enables smooth communication is provided. the electronic device includes a display portion including a first camera; a second camera; and an image processing portion. the second camera is positioned in a region not overlapping with the display portion. the first camera has a function of generating a first image of a subject, and the second camera has a function of generating a second image of the subject. the image processing portion includes a generator that performs learning using training data. the training data includes an image including a person's face. the image processing portion has a function of making the first image clear when the first image is input to the generator and a function of tracking the gaze of the subject on the basis of the second image.
Inventor(s): Daiki NAKAMURA of Atsugi JP for semiconductor energy laboratory co., ltd., Masataka IKEDA of Shinjuku JP for semiconductor energy laboratory co., ltd.
IPC Code(s): G06F3/041, G02F1/1333
CPC Code(s): G06F3/041
Abstract: a touch panel capable of performing display and sensing along a curved surface or a touch panel that maintains high detection sensitivity even when it is curved along a curved surface is provided. a flexible display panel is placed along a curved portion included in a surface of a support. a first film layer is attached along a surface of the display panel by a bonding layer. second to n-th film layers (n is an integer of 2 or more) are sequentially attached along a surface of the first film layer by bonding layers. a flexible touch sensor is attached along a surface of the n-th film layer by a bonding layer.
Inventor(s): Kazuma FURUTANI of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Yoshiyuki KUROKAWA of Sagamihara, Kanagawa JP for semiconductor energy laboratory co., ltd., Kazuaki OHSHIMA of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Hideki UOCHI of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/102
Abstract: a highly reliable memory device is provided. of an information bit and a check bit forming a hamming code, the information bit having a larger bit length than the check bit is stored in a first memory portion, and the check bit is stored in the second memory portion. the hamming code is divided and stored in a plurality of memory portions, whereby occurrence of a soft error is suppressed. the first memory portion that needs a large memory capacity is formed using a si transistor, and the second memory portion is formed using an os transistor. a combination of memory scribing and bit interleaving achieves a highly reliable memory device.
Inventor(s): Naoaki TSUTSUI of Atsugi JP for semiconductor energy laboratory co., ltd., Toshiki HAMADA of Isehara JP for semiconductor energy laboratory co., ltd.
IPC Code(s): G06F16/33, G06F16/35, G06F40/186
CPC Code(s): G06F16/3344
Abstract: a novel information processing system that is highly convenient, useful, or reliable is provided. the information processing system includes a first component, a second component, and a third component. the first component has a function of receiving a text written in a natural language and a query for performing retrieval in design assets and transferring the text and the query to the third component, a function of providing a code, and a function of emphasizing a portion related to the code and then providing the design assets. the second component has a function of generating an intermediate code from the text in accordance with a prompt and transferring the intermediate code to the third component. the third component has a function of classifying the text into a predetermined class, generating the prompt, and transferring the prompt to the second component. the third component has a function of generating the code from the command using the received intermediate code as an argument in accordance with the syntax, and transferring the code to the first component.
Inventor(s): Shingo EGUCHI of Atsugi JP for semiconductor energy laboratory co., ltd., Taiki NONAKA of Atsugi JP for semiconductor energy laboratory co., ltd., Daiki NAKAMURA of Atsugi JP for semiconductor energy laboratory co., ltd., Nozomu SUGISAWA of Isehara JP for semiconductor energy laboratory co., ltd., Kazuhiko FUJITA of Hiratsuka JP for semiconductor energy laboratory co., ltd., Shunpei YAMAZAKI of Tokyo JP for semiconductor energy laboratory co., ltd.
IPC Code(s): G09F9/30, G06F1/16, H05K5/00, H05K5/02, H10K59/12, H10K77/10
CPC Code(s): G09F9/30
Abstract: a novel display panel that is highly convenient, useful, or reliable is provided. the display panel includes a display region, a first support, and a second support, the display region includes a first region, a second region, and a third region, the first region and the second region each have a belt-like shape extending in one direction, and the third region is sandwiched between the first region and the second region. the first support overlaps with the first region and is less likely to be warped than the third region, and the second support overlaps with the second region and is less likely to be warped than the third region. the second support can pivot on an axis extending in the one direction with respect to the first support.
Inventor(s): Shunpei YAMAZAKI of Tokyo JP for semiconductor energy laboratory co., ltd., Yukinori SHIMA of Tatebayashi JP for semiconductor energy laboratory co., ltd., Masami JINTYOU of Shimotsuga JP for semiconductor energy laboratory co., ltd.
IPC Code(s): G09F9/30, H10D30/67, H10K50/00, H10K59/00
CPC Code(s): G09F9/30
Abstract: a semiconductor device that can be highly integrated is provided.
Inventor(s): Shunpei YAMAZAKI of Tokyo JP for semiconductor energy laboratory co., ltd., Yukinori SHIMA of Tatebayashi JP for semiconductor energy laboratory co., ltd., Masami JINTYOU of Shimotsuga JP for semiconductor energy laboratory co., ltd.
IPC Code(s): G09F9/30, H10D30/67, H10K50/00, H10K59/00
CPC Code(s): G09F9/30
Abstract: the semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, and a first conductive layer. the third insulating layer is positioned over the semiconductor layer and includes a first opening over the semiconductor layer. the first conductive layer is positioned over the semiconductor layer, the first insulating layer is positioned between the first conductive layer and the semiconductor layer, and the second insulating layer is provided in a position that is in contact with a side surface of the first opening, the semiconductor layer, and the first insulating layer. the semiconductor layer includes a first portion overlapping with the first insulating layer, a pair of second portions between which the first portion is sandwiched and which overlap with the second insulating layer, and a pair of third portions between which the first portion and the pair of second portions are sandwiched and which overlap with neither the first insulating layer nor the second insulating layer. the first portion has a smaller width than the first opening and has a thinner shape of the semiconductor layer than the second portions, and the second portions have a thinner shape of the semiconductor layer than the third portions.
20250148985. DISPLAY DEVICE_simplified_abstract_(semiconductor energy laboratory co., ltd.)
Inventor(s): Shunpei YAMAZAKI of Setagaya JP for semiconductor energy laboratory co., ltd., Kenichi OKAZAKI of Atsugi JP for semiconductor energy laboratory co., ltd., Koji KUSUNOKI of Isehara JP for semiconductor energy laboratory co., ltd.
IPC Code(s): G09G3/3233, H10K59/121
CPC Code(s): G09G3/3233
Abstract: a display device that has high display quality is provided. a highly reliable display device is provided. a display device with low power consumption is provided. a light-emitting element is electrically connected to one of a source and a drain of a first transistor. the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of a second transistor. a gate electrode of the second transistor is electrically connected to one of a source and a drain of a third transistor. a semiconductor layer of the second transistor and a semiconductor layer of the third transistor each include indium, zinc and a third metal. the ratio of the number of indium atoms to the total number of the indium atoms, zinc atoms, and atoms of the third metal in the semiconductor layer of the second transistor is higher than or equal to 30 atomic % and lower than or equal to 100 atomic %. the second transistor has a function of controlling the amount of light emission of the light-emitting element.
20250149446. SEMICONDUCTOR DEVICE_simplified_abstract_(semiconductor energy laboratory co., ltd.)
Inventor(s): Shoki MIYATA of Atsugi JP for semiconductor energy laboratory co., ltd., Takanori MATSUZAKI of Atsugi JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H01L23/528, H01L23/532, H01L29/40, H10B10/00
CPC Code(s): H01L23/5283
Abstract: a semiconductor device with large memory capacity, a semiconductor device which can be miniaturized or highly integrated, a highly reliable semiconductor device, a semiconductor device with low power consumption, or a semiconductor device with high operating speed is provided. a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer are provided over a first conductive layer in this order and each include an opening portion reaching the first conductive layer. in the opening portion of the second conductive layer, a third insulating layer, a first charge-accumulation layer, a fourth insulating layer, an oxide semiconductor layer, a fifth insulating layer, a second charge-accumulation layer, a sixth insulating layer, and a fourth conductive layer are provided in this order from a sidewall of the opening portion. the first conductive layer and the third conductive layer function as a source electrode or a drain electrode of a transistor. the fourth conductive layer functions as a first control gate. the second conductive layer functions as a second control gate.
20250150083. SEMICONDUCTOR DEVICE_simplified_abstract_(semiconductor energy laboratory co., ltd.)
Inventor(s): Masashi FUJITA of Tokyo JP for semiconductor energy laboratory co., ltd., Yutaka SHIONOIRI of Isehara JP for semiconductor energy laboratory co., ltd., Kiyoshi KATO of Atsugi JP for semiconductor energy laboratory co., ltd., Hidetomo KOBAYASHI of Isehara JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H03K19/17728, H03K19/173, H03K19/17758, H03K19/17772
CPC Code(s): H03K19/17728
Abstract: an object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. in a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.
Inventor(s): Shunpei YAMAZAKI of Setagaya JP for semiconductor energy laboratory co., ltd., Tatsuya ONUKI of Atsugi JP for semiconductor energy laboratory co., ltd., Kiyoshi KATO of Atsugi JP for semiconductor energy laboratory co., ltd., Hitoshi KUNITAKE of Machida JP for semiconductor energy laboratory co., ltd., Ryota HODO of Atsugi JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/00
Abstract: a semiconductor device that can be miniaturized or highly integrated is provided. the semiconductor device includes a memory cell including first to third transistors and a capacitor. the second and third transistors share a metal oxide. the capacitor is provided between the first and second transistors. an insulator is provided over an electrode functioning as a source or a drain of the first transistor, and the insulator has an opening reaching the electrode. the capacitor is provided in the opening. one electrode of the capacitor includes, in the opening, a region in contact with the other of the source electrode and the drain electrode of the first transistor. the one electrode of the capacitor includes a region in contact with a gate electrode of the second transistor.
Inventor(s): Hajime KIMURA of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Shunpei YAMAZAKI of Setagaya, Tokyo JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/482
Abstract: a semiconductor device having high memory density is provided. the semiconductor device includes a first insulator, a first layer, a second insulator, a second layer, a third insulator, and a third layer, which are stacked in this order. each of the first layer and the third layer includes a first and a second transistor and a first conductor. the second layer includes a second conductor. in the first transistor in each of the first and the third layer, a source and a drain are positioned on a semiconductor layer and a gate is positioned over the semiconductor layer. in the second transistor in each of the first and the third layer, a source and a drain are positioned on a semiconductor layer and a gate is positioned over the semiconductor layer. in each of the first and the third layer, the first conductor electrically connects a region on the source or the drain of the first transistor and a region on the gate of the second transistor. the first conductor and the second conductor in the first layer, and the semiconductor layer of the first transistor in the third layer overlap with each other.
Inventor(s): Hajime KIMURA of Atsugi JP for semiconductor energy laboratory co., ltd., Tatsunori INOUE of Atsugi JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10B43/27, H01L21/02, H10B41/27, H10B41/35, H10B41/41, H10B43/20, H10B43/35, H10B43/40, H10D30/60, H10D30/68, H10D62/80, H10D64/01, H10D99/00
CPC Code(s): H10B43/27
Abstract: an object is to provide a semiconductor device with large memory capacity. the semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. the first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. the third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. the fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. the sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. the seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.
20250151294. STORAGE DEVICE_simplified_abstract_(semiconductor energy laboratory co., ltd.)
Inventor(s): Shunpei YAMAZAKI of Setagaya JP for semiconductor energy laboratory co., ltd., Tatsuya ONUKI of Atsugi JP for semiconductor energy laboratory co., ltd., Hitoshi KUNITAKE of Machida JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10B80/00, H01L25/07, H10B12/00, H10D1/68
CPC Code(s): H10B80/00
Abstract: a semiconductor device that can be miniaturized or highly integrated is provided. a storage device includes a first transistor, a second transistor, a first capacitor, and a second capacitor. the first capacitor includes a first electrode and a second electrode. the second capacitor includes the first electrode and a third electrode. one of a source and a drain of the first transistor is electrically connected to the second electrode; one of a source and a drain of the second transistor is electrically connected to the third electrode; and the first electrode includes a portion overlapping with each of the second electrode, the third electrode, the first transistor, and the second transistor and is supplied with a fixed potential or a ground potential.
20250151295. SEMICONDUCTOR DEVICE_simplified_abstract_(semiconductor energy laboratory co., ltd.)
Inventor(s): Shunpei YAMAZAKI of Setagaya, Tokyo JP for semiconductor energy laboratory co., ltd., Tatsuya ONUKI of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Hitoshi KUNITAKE of Machida, Tokyo JP for semiconductor energy laboratory co., ltd., Ryota HODO of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10B80/00, H01L25/07, H10B12/00, H10D30/67
CPC Code(s): H10B80/00
Abstract: a semiconductor device that can be miniaturized or highly integrated is provided. the semiconductor device includes a first memory cell, a second memory cell over the first memory cell, a first conductor, and a second conductor over the first conductor. the first memory cell and the second memory cell each include a transistor and a capacitor. one of a source and a drain of the transistor is electrically connected to a lower electrode of the capacitor. the first conductor includes a portion in contact with the other of the source and the drain of the transistor included in the first memory cell. a top surface of the first conductor includes a portion in contact with a bottom surface of the second conductor. the second conductor includes a portion in contact with the other of the source and the drain of the transistor included in the second memory cell.
20250151332. SEMICONDUCTOR DEVICE_simplified_abstract_(semiconductor energy laboratory co., ltd.)
Inventor(s): Shunpei YAMAZAKI of Tokyo JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10D30/67, H10D86/40, H10D86/60
CPC Code(s): H10D30/6755
Abstract: an object is to stabilize electric characteristics of a semiconductor device including an oxide semiconductor to increase reliability. the semiconductor device includes an insulating film; a first metal oxide film on and in contact with the insulating film; an oxide semiconductor film partly in contact with the first metal oxide film; source and drain electrodes electrically connected to the oxide semiconductor film; a second metal oxide film partly in contact with the oxide semiconductor film; a gate insulating film on and in contact with the second metal oxide film; and a gate electrode over the gate insulating film.
Inventor(s): Shunpei YAMAZAKI of Setagaya JP for semiconductor energy laboratory co., ltd., Yasuharu HOSAKA of Tochigi JP for semiconductor energy laboratory co., ltd., Mitsuo MASHIYAMA of Oyama JP for semiconductor energy laboratory co., ltd., Kenichi OKAZAKI of Tochigi JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10D30/67, H10D30/01, H10K59/12, H10K59/121
CPC Code(s): H10D30/6755
Abstract: a circuit capable of high-speed operation and a pixel are integrally formed over the same substrate. a first metal oxide film, a first metal film, and an island-shaped first resist mask are formed over a first insulating layer. an island-shaped first metal layer and an island-shaped first oxide semiconductor layer are formed and a part of a top surface of the first insulating layer is exposed; then, the first resist mask is removed. a second metal oxide film, a second metal film, and an island-shaped second resist mask are formed over the first metal layer and the first insulating layer. an island-shaped second metal layer and an island-shaped second oxide semiconductor layer are formed; then, the second resist mask is removed. the first metal layer and the second metal layer are removed.
Inventor(s): Shunpei YAMAZAKI of Tokyo JP for semiconductor energy laboratory co., ltd., Masayuki SAKAKURA of Isehara, Kanagawa JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10D30/67, H10D62/17, H10D62/40, H10D84/01, H10D84/03, H10D84/85, H10D86/40, H10D86/60, H10D88/00
CPC Code(s): H10D30/6756
Abstract: a transistor with small parasitic capacitance can be provided. a transistor with high frequency characteristics can be provided. a semiconductor device including the transistor can be provided. provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. the first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. the oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.
Inventor(s): Shunpei YAMAZAKI of Setagaya JP for semiconductor energy laboratory co., ltd., Yoshiharu HIRAKATA of Ebina JP for semiconductor energy laboratory co., ltd., Takashi HAMADA of Atsugi JP for semiconductor energy laboratory co., ltd., Kohei YOKOYAMA of Fujisawa JP for semiconductor energy laboratory co., ltd., Yasuhiro JINBO of Isehara JP for semiconductor energy laboratory co., ltd., Tetsuji ISHITANI of Atsugi JP for semiconductor energy laboratory co., ltd., Daisuke KUBOTA of Atsugi JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10D86/01, G02F1/1333, G02F1/1335, G02F1/1339, G02F1/1362, G02F1/1368, H10D30/67, H10D86/40, H10D86/60, H10K50/842, H10K50/844, H10K59/38, H10K59/40, H10K71/50, H10K102/00
CPC Code(s): H10D86/0212
Abstract: a display device in which a peripheral circuit portion has high operation stability is provided. the display device includes a first substrate and a second substrate. a first insulating layer is provided over a first surface of the first substrate. a second insulating layer is provided over a first surface of the second substrate. the first surface of the first substrate and the first surface of the second substrate face each other. an adhesive layer is provided between the first insulating layer and the second insulating layer. a protective film in contact with the first substrate, the first insulating layer, the adhesive layer, the second insulating layer, and the second substrate is formed in the vicinity of a peripheral portion of the first substrate and the second substrate.
Inventor(s): Shunpei YAMAZAKI of Setagaya JP for semiconductor energy laboratory co., ltd., Toshinari SASAKI of Atsugi JP for semiconductor energy laboratory co., ltd., Junichiro SAKATA of Atsugi JP for semiconductor energy laboratory co., ltd., Masashi TSUBUKU of Atsugi JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10D86/60, H10D30/67, H10D62/80, H10D64/27, H10D64/62, H10D86/40, H10K59/121, H10K59/123
CPC Code(s): H10D86/60
Abstract: it is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. in a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.
Inventor(s): Jun KOYAMA of Sagamihara JP for semiconductor energy laboratory co., ltd., Shunpei YAMAZAKI of Setagaya JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10D86/60, G02F1/1333, G02F1/1343, G02F1/1345, G02F1/1362, G02F1/1368, G09G3/3266, G09G3/3275, G09G3/36, H10D30/01, H10D30/67, H10D62/40, H10D86/01, H10D86/40, H10D99/00
CPC Code(s): H10D86/60
Abstract: one embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. a first oxide component is formed over a base component. crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. a second oxide component is formed over the first oxide crystal component. crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. thus, a stacked oxide material is formed. a transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor.
Inventor(s): Takayuki IKEDA of Atsugi JP for semiconductor energy laboratory co., ltd., Yoshiyuki KUROKAWA of Sagamihara JP for semiconductor energy laboratory co., ltd., Shintaro HARADA of Sagamihara JP for semiconductor energy laboratory co., ltd., Hidetomo KOBAYASHI of Isehara JP for semiconductor energy laboratory co., ltd., Roh YAMAMOTO of Toyama JP for semiconductor energy laboratory co., ltd., Kiyotaka KIMURA of Atsugi JP for semiconductor energy laboratory co., ltd., Takashi NAKAGAWA of Sagamihara JP for semiconductor energy laboratory co., ltd., Yusuke NEGORO of Atsugi JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10F39/00, H04N25/40, H04N25/766, H04N25/77, H10D30/67, H10D86/40, H10D86/60, H10F39/18
CPC Code(s): H10F39/8023
Abstract: an imaging device capable of image processing is provided. the imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. when the binary data is taken in a neural network or the like, processing such as image recognition can be performed. since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.
Inventor(s): Tatsuya ONUKI of Atsugi JP for semiconductor energy laboratory co., ltd., Kiyoshi KATO of Atsugi JP for semiconductor energy laboratory co., ltd., Takanori MATSUZAKI of Atsugi JP for semiconductor energy laboratory co., ltd., Hajime KIMURA of Atsugi JP for semiconductor energy laboratory co., ltd., Shunpei YAMAZAKI of Tokyo JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10F39/00, H04N25/771, H04N25/772, H10B12/00, H10D30/67, H10D86/40, H10D86/60, H10D87/00
CPC Code(s): H10F39/809
Abstract: an imaging device which has a stacked-layer structure and can be manufactured easily is provided. the imaging device includes a signal processing circuit, a memory device, and an image sensor. the imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. the signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.
Inventor(s): Ryo ARASAWA of Isehara JP for semiconductor energy laboratory co., ltd., Hideaki SHISHIDO of Atsugi JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10H20/817, H10D86/40, H10D86/60
CPC Code(s): H10H20/817
Abstract: an object is to provide a light-emitting display device in which a pixel including a thin film transistor using an oxide semiconductor has a high aperture ratio. the light-emitting display device includes a plurality of pixels each including a thin film transistor and a light-emitting element. the pixel is electrically connected to a first wiring functioning as a scan line. the thin film transistor includes an oxide semiconductor layer over the first wiring with a gate insulating film therebetween. the oxide semiconductor layer is extended beyond the edge of a region where the first wiring is provided. the light-emitting element and the oxide semiconductor layer overlap with each other.
Inventor(s): Satoshi Seo of Sagamihara JP for semiconductor energy laboratory co., ltd., Nobuharu Ohsawa of Zama JP for semiconductor energy laboratory co., ltd., Shunpei Yamazaki of Tokyo JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10K50/17, H10K50/11, H10K50/16, H10K59/12, H10K59/38, H10K85/30, H10K85/60, H10K101/30, H10K101/40, H10K102/00
CPC Code(s): H10K50/17
Abstract: a long-lifetime light-emitting device is provided. the light-emitting apparatus includes a first light-emitting device and a first color conversion layer. the first color conversion layer contains a first substance. an el layer of the first light-emitting device includes a first layer, a second layer, a third layer, a light-emitting layer, and a fourth layer in this order from the anode side. the first layer contains a first organic compound and a second organic compound. the second layer contains a third organic compound. the third layer contains a fourth organic compound. the light-emitting layer contains a fifth organic compound and a sixth organic compound. the fourth layer contains a seventh organic compound. the first organic compound is an organic compound having an electron accepting property to the second organic compound. the fifth organic compound is an emission center substance. the homo level of the second organic compound is higher than or equal to −5.7 ev and lower than or equal to −5.4 ev.
Inventor(s): Hisao IKEDA of Zama JP for semiconductor energy laboratory co., ltd., Tomoya AOYAMA of Atsugi JP for semiconductor energy laboratory co., ltd., Kensuke YOSHIZUMI of Atsugi JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10K50/856, G02B27/01, G06F1/16, H10K59/131
CPC Code(s): H10K50/856
Abstract: a high-resolution display device is provided. the display device includes a plurality of light-emitting units emitting light of different colors. the light-emitting unit has a microcavity structure and intensifies light with a specific wavelength. in the light-emitting units emitting light of different colors, reflective layers with different thicknesses are formed, an insulating layer is formed to cover the reflective layers, and then a top surface of the insulating layer is subjected to planarization treatment, whereby an insulating layer with different thicknesses is formed. after that, light-emitting elements emitting white light are formed over the planarized top surface of the insulating layer to overlap with the respective reflective layers, whereby the light-emitting units that intensify different colors due to different optical path lengths are separately formed.
Inventor(s): Hideaki SHISHIDO of Atsugi JP for semiconductor energy laboratory co., ltd., Naoto KUSUMOTO of Isehara JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10K59/122, G02F1/133, G06F3/041, G09G3/20, G09G3/3225, G09G3/3233, G09G3/3258, G09G3/36, H10D30/67, H10D86/40, H10D86/60, H10K10/84, H10K50/115, H10K50/814, H10K59/121, H10K59/128, H10K71/20
CPC Code(s): H10K59/122
Abstract: a display device with a narrow bezel is provided. the display device includes a pixel circuit and a driver circuit which are provided on the same plane. the driver circuit includes a selection circuit and a buffer circuit. the selection circuit includes a first transistor. the buffer circuit includes a second transistor. the first transistor has a region overlapping with the second transistor. one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. one of a source and a drain of the second transistor is electrically connected to the pixel circuit.
Inventor(s): Yasuharu HOSAKA of Tochigi JP for semiconductor energy laboratory co., ltd., Yukinori SHIMA of Tatebayashi JP for semiconductor energy laboratory co., ltd., Masami JINTYOU of Shimotsuga JP for semiconductor energy laboratory co., ltd., Masataka NAKADA of Tochigi JP for semiconductor energy laboratory co., ltd., Junichi KOEZUKA of Tochigi JP for semiconductor energy laboratory co., ltd., Kenichi OKAZAKI of Atsugi JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10K59/124, H10K59/12, H10K59/121
CPC Code(s): H10K59/124
Abstract: a semiconductor device including a miniaturized transistor is provided. the semiconductor device includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. the first insulating layer is provided over the first conductive layer. the first insulating layer has a first opening reaching the first conductive layer. the semiconductor layer is in contact with a top surface and a side surface of the first insulating layer and a top surface of the first conductive layer. the second conductive layer is provided over the semiconductor layer. the second conductive layer includes a second opening in a region overlapping with the first opening. the second insulating layer is provided over the semiconductor layer and the second conductive layer. the third conductive layer is provided over the second insulating layer. the first insulating layer has a stacked-layer structure of a third insulating layer and a fourth insulating layer over the third insulating layer. the fourth insulating layer includes a region having a film density higher than that of the third insulating layer.
Inventor(s): Toshiyuki ISA of Atsugi JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10K59/40, G06F3/041, G06F3/044, H05B33/26, H10K59/12, H10K59/131, H10K71/80, H10K77/10, H10K102/00
CPC Code(s): H10K59/40
Abstract: the display defects of a display device are reduced. the display quality of the display device is improved. the display device includes a display panel and a first conductive layer. the display panel includes a display element including a pair of electrodes. an electrode of the pair of electrodes which is closer to one surface of the display panel is supplied with a constant potential. a constant potential is supplied to the first conductive layer. the second conductive layer provided on the other surface of the display panel is in contact with the first conductive layer, whereby the second conductive layer is also supplied with the constant potential. the second conductive layer includes a portion not fixed to the first conductive layer.
Inventor(s): Taisuke KAMADA of Niiza JP for semiconductor energy laboratory co., ltd., Ryo HATSUMI of Hadano JP for semiconductor energy laboratory co., ltd., Daisuke KUBOTA of Atsugi JP for semiconductor energy laboratory co., ltd., Naoaki HASHIMOTO of Sagamihara JP for semiconductor energy laboratory co., ltd., Tsunenori SUZUKI of Yokohama JP for semiconductor energy laboratory co., ltd., Harue OSAKA of Atsugi JP for semiconductor energy laboratory co., ltd., Satoshi SEO of Sagamihara JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10K65/00, H10K39/32, H10K50/16, H10K50/17, H10K50/86, H10K59/12, H10K59/40, H10K101/30
CPC Code(s): H10K65/00
Abstract: an object is to provide a highly reliable display unit having a function of sensing light. the display unit includes a light-receiving device and a light-emitting device. the light-receiving device includes an active layer between a pair of electrodes. the light-emitting device includes a hole-injection layer, a light-emitting layer, and an electron-transport layer between a pair of electrodes. the light-receiving device and the light-emitting device share one of the electrodes, and may further share another common layer between the pair of electrodes. the hole-injection layer is in contact with an anode and contains a first compound and a second compound. the electron-transport property of the electron-transport layer is low; hence, the light-emitting layer is less likely to have excess electrons. here, the first compound is the material having a property of accepting electrons from the second compound.
Inventor(s): Yui YOSHIYASU of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Kyoko TAKEDA of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Masatoshi TAKABATAKE of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Sachiko KAWAKAMI of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Tsunenori SUZUKI of Yokohama, Kanagawa JP for semiconductor energy laboratory co., ltd., Toshiki SASAKI of Kawasaki, Kanagawa JP for semiconductor energy laboratory co., ltd., Naoaki HASHIMOTO of Sagamihara, Kanagawa JP for semiconductor energy laboratory co., ltd., Tomoya AOYAMA of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10K71/40, C07F1/02, C07F1/04, C07F1/08, C07F3/06, C07F5/06, C07F11/00, C07F15/06, H10K50/11, H10K50/15, H10K71/20, H10K85/30, H10K85/60, H10K101/00, H10K101/10, H10K101/25, H10K101/30
CPC Code(s): H10K71/40
Abstract: the heat resistance of an organic semiconductor device including a step of forming an aluminum oxide film over and in contact with an organic semiconductor layer is improved. a heating step is performed after a layer containing an organometallic compound for a mask for an organic semiconductor layer, which is represented by general formula (g1) below, is provided over the organic semiconductor layer.
Inventor(s): Yui YOSHIYASU of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Kyoko TAKEDA of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Masatoshi TAKABATAKE of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Sachiko KAWAKAMI of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Tsunenori SUZUKI of Yokohama, Kanagawa JP for semiconductor energy laboratory co., ltd., Toshiki SASAKI of Kawasaki, Kanagawa JP for semiconductor energy laboratory co., ltd., Naoaki HASHIMOTO of Sagamihara, Kanagawa JP for semiconductor energy laboratory co., ltd., Tomoya AOYAMA of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10K71/40, C07F1/02, C07F1/04, C07F1/08, C07F3/06, C07F5/06, C07F11/00, C07F15/06, H10K50/11, H10K50/15, H10K71/20, H10K85/30, H10K85/60, H10K101/00, H10K101/10, H10K101/25, H10K101/30
CPC Code(s): H10K71/40
Abstract:
Inventor(s): Yui YOSHIYASU of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Kyoko TAKEDA of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Masatoshi TAKABATAKE of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Sachiko KAWAKAMI of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd., Tsunenori SUZUKI of Yokohama, Kanagawa JP for semiconductor energy laboratory co., ltd., Toshiki SASAKI of Kawasaki, Kanagawa JP for semiconductor energy laboratory co., ltd., Naoaki HASHIMOTO of Sagamihara, Kanagawa JP for semiconductor energy laboratory co., ltd., Tomoya AOYAMA of Atsugi, Kanagawa JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10K71/40, C07F1/02, C07F1/04, C07F1/08, C07F3/06, C07F5/06, C07F11/00, C07F15/06, H10K50/11, H10K50/15, H10K71/20, H10K85/30, H10K85/60, H10K101/00, H10K101/10, H10K101/25, H10K101/30
CPC Code(s): H10K71/40
Abstract: in general formula (g1), ar represents a substituted or unsubstituted aryl group having 6 to 30 carbon atoms or a substituted or unsubstituted heteroaryl group having 1 to 30 carbon atoms, x represents oxygen or sulfur, m represents a metal, n represents an integer greater than or equal to 1 and less than or equal to 5, and n is the same as the valence of the metal m. note that when n is greater than or equal to 2, a plurality of ars may be the same or different and xs may be the same or different. when ar represents the substituted or unsubstituted heteroaryl group having 1 to 30 carbon atoms, a heteroatom of the heteroaryl group may be coordinated to the metal m.
20250151612. Light-Emitting Device_simplified_abstract_(semiconductor energy laboratory co., ltd.)
Inventor(s): Toshiki SASAKI of Kawasaki JP for semiconductor energy laboratory co., ltd., Nobuharu OHSAWA of Zama JP for semiconductor energy laboratory co., ltd., Hiromi SEO of Sagamihara JP for semiconductor energy laboratory co., ltd., Shinya FUKUZAKI of Atsugi JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10K85/60, H10K50/11, H10K50/17, H10K101/40
CPC Code(s): H10K85/654
Abstract: a light-emitting device with high reliability is provided. the light-emitting device includes a first electrode, a second electrode, and an el layer. the el layer is positioned between the first electrode and the second electrode. the el layer includes a light-emitting layer and an electron-injection layer. the electron-injection layer contains a metal or an oxide of the metal, a first organic compound, and a second organic compound. the first organic compound includes a first �-electron deficient heteroaromatic ring with an electron-donating group. the second organic compound includes a second �-electron deficient heteroaromatic ring. the lumo level of the second organic compound is lower than that of the first organic compound by 0.20 ev or more.
Inventor(s): Miki KURIHARA of Isehara JP for semiconductor energy laboratory co., ltd., Hideko YOSHIZUMI of Isehara JP for semiconductor energy laboratory co., ltd., Satomi WATABE of Isehara JP for semiconductor energy laboratory co., ltd., Hiromitsu KIDO of Atsugi JP for semiconductor energy laboratory co., ltd., Satoshi SEO of Sagamihara JP for semiconductor energy laboratory co., ltd.
IPC Code(s): H10K85/60, C07D491/048, H10K50/11, H10K59/12, H10K71/16
CPC Code(s): H10K85/6576
Abstract: a novel organic compound is provided. that is, a novel organic compound that is effective in improving reliability of a light-emitting element is provided. the organic compound includes a condensed ring including a pyrimidine ring and is represented by general formula (g1). in general formula (g1), a represents a group having 6 to 100 carbon atoms and includes at least one of an aromatic ring and a heteroaromatic ring. the aromatic ring and the heteroaromatic ring may each include a substituent. furthermore, q represents oxygen or sulfur. a ring x represents a substituted or unsubstituted naphthalene ring or a substituted or unsubstituted phenanthrene ring.
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. patent applications on May 8th, 2025
- SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
- C23C14/34
- B28B11/24
- C04B35/453
- C04B35/64
- C23C14/08
- H01L21/02
- H10D30/67
- H10D62/80
- H10D99/00
- CPC C23C14/3414
- Semiconductor energy laboratory co., ltd.
- G02F1/1333
- G02F1/1345
- G02F1/167
- G06F3/041
- G09G3/20
- G09G3/3208
- G09G3/36
- G09G5/00
- G09G5/39
- H05K1/18
- H10D86/40
- H10D86/60
- CPC G02F1/133305
- G02F1/1335
- F21S2/00
- G02B5/30
- G02F1/1347
- G09F9/00
- G09G3/00
- G09G3/32
- G09G3/3233
- H10F55/10
- CPC G02F1/1335
- G02F1/1368
- G02F1/1337
- G02F1/1362
- CPC G02F1/1368
- G06F1/16
- G06F3/14
- G06F3/147
- G09G3/3225
- G09G3/34
- CPC G06F1/1652
- G06F3/01
- G06T1/20
- G06T7/73
- G06V10/141
- G06V40/18
- H04N23/611
- H04N23/617
- H04N23/90
- CPC G06F3/013
- CPC G06F3/041
- G06F11/10
- CPC G06F11/102
- G06F16/33
- G06F16/35
- G06F40/186
- CPC G06F16/3344
- G09F9/30
- H05K5/00
- H05K5/02
- H10K59/12
- H10K77/10
- CPC G09F9/30
- H10K50/00
- H10K59/00
- H10K59/121
- CPC G09G3/3233
- H01L23/528
- H01L23/532
- H01L29/40
- H10B10/00
- CPC H01L23/5283
- H03K19/17728
- H03K19/173
- H03K19/17758
- H03K19/17772
- CPC H03K19/17728
- H10B12/00
- CPC H10B12/00
- CPC H10B12/482
- H10B43/27
- H10B41/27
- H10B41/35
- H10B41/41
- H10B43/20
- H10B43/35
- H10B43/40
- H10D30/60
- H10D30/68
- H10D64/01
- CPC H10B43/27
- H10B80/00
- H01L25/07
- H10D1/68
- CPC H10B80/00
- CPC H10D30/6755
- H10D30/01
- H10D62/17
- H10D62/40
- H10D84/01
- H10D84/03
- H10D84/85
- H10D88/00
- CPC H10D30/6756
- H10D86/01
- G02F1/1339
- H10K50/842
- H10K50/844
- H10K59/38
- H10K59/40
- H10K71/50
- H10K102/00
- CPC H10D86/0212
- H10D64/27
- H10D64/62
- H10K59/123
- CPC H10D86/60
- G02F1/1343
- G09G3/3266
- G09G3/3275
- H10F39/00
- H04N25/40
- H04N25/766
- H04N25/77
- H10F39/18
- CPC H10F39/8023
- H04N25/771
- H04N25/772
- H10D87/00
- CPC H10F39/809
- H10H20/817
- CPC H10H20/817
- H10K50/17
- H10K50/11
- H10K50/16
- H10K85/30
- H10K85/60
- H10K101/30
- H10K101/40
- CPC H10K50/17
- H10K50/856
- G02B27/01
- H10K59/131
- CPC H10K50/856
- H10K59/122
- G02F1/133
- G09G3/3258
- H10K10/84
- H10K50/115
- H10K50/814
- H10K59/128
- H10K71/20
- CPC H10K59/122
- H10K59/124
- CPC H10K59/124
- G06F3/044
- H05B33/26
- H10K71/80
- CPC H10K59/40
- H10K65/00
- H10K39/32
- H10K50/86
- CPC H10K65/00
- H10K71/40
- C07F1/02
- C07F1/04
- C07F1/08
- C07F3/06
- C07F5/06
- C07F11/00
- C07F15/06
- H10K50/15
- H10K101/00
- H10K101/10
- H10K101/25
- CPC H10K71/40
- CPC H10K85/654
- C07D491/048
- H10K71/16
- CPC H10K85/6576
