Qualcomm incorporated (20250062754). CLOCK SPUR REDUCTION VIA PHASE-CONTROLLED REPLICA PATH
CLOCK SPUR REDUCTION VIA PHASE-CONTROLLED REPLICA PATH
Organization Name
Inventor(s)
Shahin Mehdizad Taleie of San Diego CA (US)
Dongwon Seo of San Diego CA (US)
Bhushan Shanti Asuri of San Diego CA (US)
Ibrahim Ramez Chamas of Carlsbad CA (US)
Zhiheng Wang of San Diego CA (US)
Reza Rodd of San Diego CA (US)
CLOCK SPUR REDUCTION VIA PHASE-CONTROLLED REPLICA PATH
This abstract first appeared for US patent application 20250062754 titled 'CLOCK SPUR REDUCTION VIA PHASE-CONTROLLED REPLICA PATH
Original Abstract Submitted
certain aspects of the present disclosure provide apparatus and techniques to generate signals for clock spur attenuation. an example apparatus generally includes: one or more circuits coupled between a voltage rail and a reference potential node, wherein the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delay signal; and signal generation circuitry coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delay signal.