Patent Applications by QUALCOMM Incorporated on 31st July 2025

QUALCOMM Incorporated: 97 patent applications

QUALCOMM Incorporated has applied for patents in the areas of H04W72/21 (in the uplink direction of a wireless link, i.e. towards the network, 6), H04W74/0833 (Random access procedures, e.g. with 4-step access, 5), H04W72/232 (in the downlink direction of a wireless link, i.e. towards a terminal, 5), H04L5/0051 (Arrangements affording multiple use of the transmission path, 5), H04L5/14 (Two-way operation using the same type of signal, i.e. duplex, 4)

Patent Applications by QUALCOMM Incorporated

20250244375. DISTANCE ESTIMATION FOR MULTIPLE DEVICES ON A TRANSMISSION LINE USING CONTROLLABLE SHORTS

Abstract: Systems and techniques are provided for distance estimation. A first pulse signal injected into a first end of a transmission line can reflect off a first short caused across the transmission line by a first device. A peak voltage of a first difference signal corresponding to the reflection can be m...

20250244461. MULTIPATH RADIO PROPAGATION REPORTING

Abstract: In an aspect, a sensing node may obtain one or more multipath measurements of one or more sensing signals associated with one or more radio propagation paths. The sensing node may obtain radio propagation paths information associated with the one or more radio propagation paths based on the one or m...

20250244806. POWER AWARE THERMAL MITIGATION FRAMEWORK

Abstract: Aspects relate to mechanisms for providing a power aware thermal mitigation framework for a system-on-chip (SoC) of a device (e.g., a mobile device). A thermal controller of the SoC is configured to calculate a respective power of each of a plurality of electronic control units (ECUs) on the SoC at ...

20250244819. ENHANCED CURRENT LIMITING TECHNIQUES

Abstract: Certain aspects of the present disclosure are directed towards techniques and apparatus for power control. An example apparatus generally includes: a system on chip (SoC) having a plurality of processing units, wherein the plurality of processing units are coupled to respective voltage supply paths;...

20250244950. SHUFFLE EXCHANGE NETWORK TO GENERATE FULL SET OF PERMUTATIONS

Abstract: A shuffle exchange network includes a first circuit that includes a first stage having a first set of elements storing a first set of sequences of length N, and multiple exchange units each receiving input from a first pair of the elements. Each exchange unit selectively couples the first pair of el...

20250244976. UNROLLING AN INFINITE LOOP DURING RAY QUERY TRAVERSAL

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for unrolling an infinite loop during ray query traversal. A processor obtains, during a compile time, a number of loops associated with a BVH traversal based on a number of ray t...

20250245041. OUT-OF-ORDER EXECUTION FOR GRAPHICS PROCESSING UNIT HARDWARE

Abstract: Aspects presented herein relate to methods and devices for data or graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a plurality of workloads for graphics processing. The apparatus may also perform a binning process for a first workload of the plurali...

20250245100. TRANSIENT FAULT DETECTION IN MEMORY USING DYNAMIC BIST

Abstract: A method for managing a plurality of imaging devices in a vehicle includes determining that a change of data security mode is indicated for frames of image data transmitted over a first data communication link, determining whether a sensor management system has sufficient processing capacity to supp...

20250245141. Hardware And Software Hybrid Configuration Of DRAM Channel Interleaving Management

Abstract: Various embodiments include a memory controller and methods for implementing functions of the memory controller for hardware and software hybrid configuration of memory channel interleaving management. Embodiments may include a memory controller having a signaling mechanism configured to provide a c...

20250245159. REDUCING DC POWER CONSUMPTION USING DYNAMIC MEMORY PREFETCHING FOR PROCESSING ENGINES

Abstract: Aspects of the disclosure are directed to dynamic memory prefetching. In accordance with one aspect, the disclosure includes a main memory configured to store data; a memory hierarchy coupled to the main memory, the memory hierarchy configured to augment the main memory; and a trusted zone element c...

20250245169. LOCAL STALING PARAMETER FOR CACHE MEMORY MANAGEMENT IN A PROCESSOR

Abstract: Aspects of the disclosure are directed to cache memory management. In accordance with one aspect, the disclosure includes a shared cache memory configured to store data into a plurality of cache lines; and a client coupled to the shared cache memory, the client configured to determine if a local sta...

20250245291. CONFIGURING COMPLEX SYSTEMS USING INTERPOLATED PERFORMANCE FUNCTIONS AND POLYHARMONIC SPLINES

Abstract: Certain aspects of the present disclosure provide techniques and apparatus for executing a workload on a computing device based on an approximation of a target function. An example method generally includes obtaining first performance data associated with a function to be approximated based on a set...

20250245386. CONTROLLING ACCESS TO RESTRICTED AND UNRESTRICTED SOFTWARE FUNCTIONALITY

Abstract: Some disclosed methods involve controlling a display system to present one or more restricted access virtual buttons in a secure region. The restricted access virtual buttons may correspond to functionality of the apparatus or functionality of a software application for which access is restricted. S...

20250245427. SELECTIVE PARAMETER-EFFICIENT FINE-TUNING FOR LARGE-SCALE MODELS

Abstract: A processor-implemented method for selective parameter efficient fine-tuning (PEFT) includes receiving a large language model (LLM). The LLM has multiple layers with each layer having a set of parameters. A subset of the parameters are identified to fine-tune for a downstream task based on a score f...

20250245430. EFFICIENT SPECULATIVE DECODING IN AUTOREGRESSIVE GENERATIVE ARTIFICIAL INTELLIGENCE MODELS

Abstract: Certain aspects of the present disclosure provide techniques and apparatus for efficiently generating a response to a query input in a generative artificial intelligence model. An example method generally includes generating, based on an input prompt and using a first machine learning model, a set o...