Patent Application 18770783 - Epitaxies of a Chemical Compound Semiconductor - Rejection
Appearance
Patent Application 18770783 - Epitaxies of a Chemical Compound Semiconductor
Title: Epitaxies of a Chemical Compound Semiconductor
Application Information
- Invention Title: Epitaxies of a Chemical Compound Semiconductor
- Application Number: 18770783
- Submission Date: 2025-05-15T00:00:00.000Z
- Effective Filing Date: 2024-07-12T00:00:00.000Z
- Filing Date: 2024-07-12T00:00:00.000Z
- Examiner Employee Number: 69602
- Art Unit: 2897
- Tech Center: 2800
Rejection Summary
- 102 Rejections: 0
- 103 Rejections: 3
Cited Patents
The following patents were cited in the rejection:
Office Action Text
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-20 in the reply filed on 4/1/25 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lau et al. (US pub 20140209979) in combination with Lutgen et al. (US pat 9773896) and Koo et al. (US pub 20110279146). With respect to claim 1, Lau et al. teach a structure comprising (see figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2): a barrier layer (buffer 1) including one of GaAs and InGaAs; wherein the barrier layer is between a substrate (n type silicon (100) substrate) and a channel layer (undoped Ga0.47In0.52As, channel). Lau et al. teach the barrier layer having a dopant concentration but fail to the dopant concentration is about 1017 cm-3. Lutgen et al. teach doping a barrier layer with a dopant having a concentration of about 1017 cm-3. See col. 5, lines 5-20. It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of Lutgen et al. into the device of Lau et al to achieve adjustment of the threshold voltage without loss in electrical properties. See col. 5, lines 5-20. With respect to claim 2, Lau et al. fail to teach the channel layer includes an InAs layer sandwiched between 2 layers with different composition than InAs. Koo et al. teach a channel comprises of an InAs sandwiched between Ga layers. See para 004. It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching Koo et al. into the device of Lau et al. to achieve high electron mobility. See para 0040. With respect to claim 3, Lau et al. teach the channel layer is disposed within a transistor. See figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2. With respect to claim 4, Lau et al. in combination with Lutgen et al. teach the barrier layer is P-type or N-type. See col. 5, lines 5-20 of Lutgen e tal. With respect to claim 5, Lau et al. teach the prelayer includes arsenic. See figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2. Claims 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lau et al. (US pub 20140209979) in combination with Lutgen et al. (US pat 9773896) and Koo et al. (US pub 20110279146). With respect to claim 6, Lau et al. teach a structure comprising (see figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2): a barrier layer (buffer 1); wherein the barrier layer is between a substrate (n type silicon (100) substrate) and a channel layer (undoped Ga0.47In0.52As, channel). Lau et al. teach the barrier layer having a dopant concentration but fail to the dopant concentration is about 1017 cm-3. Lutgen et al. teach doping a barrier layer with a dopant having a concentration of about 1017 cm-3. See col. 5, lines 5-20. It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of Lutgen et al. into the device of Lau et al to achieve adjustment of the threshold voltage without loss in electrical properties. See col. 5, lines 5-20. With respect to claim 7, Lau et al. fail to teach the channel layer includes an InAs layer sandwiched between 2 layers with different composition than InAs. Koo et al. teach a channel comprises of an InAs sandwiched between Ga layers. See para 004. It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching Koo et al. into the device of Lau et al. to achieve high electron mobility. See para 0040. With respect to claim 8, Lau et al. teach the channel layer includes AlSb or III-V material. See para 0031. With respect to claim 9, Lau et al. teach the channel layer includes AlGaSb or III-V material. See para 0031. With respect to claim 10, Lau et al. teach the channel layer includes AlInSb or III-V material. See para 0031. With respect to claim 11, Lau et al. teach the channel layer includes InAs or III-V material. See para 0031. Claims 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lau et al. (US pub 20140209979) in combination with Lutgen et al. (US pat 9773896) and Koo et al. (US pub 20110279146). With respect to claim 12, Lau et al. teach a structure comprising (see figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2): a barrier layer (buffer 1); and a channel layer including a heterostructure comprising InAs (see para 0031); wherein the barrier layer is between a substrate (n type silicon (100) substrate) and the channel layer. Lau et al. teach the barrier layer having a dopant concentration but fail to the dopant concentration is about 1017 cm-3. Lutgen et al. teach doping a barrier layer with a dopant having a concentration of about 1017 cm-3. See col. 5, lines 5-20. It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of Lutgen et al. into the device of Lau et al to achieve adjustment of the threshold voltage without loss in electrical properties. See col. 5, lines 5-20. With respect to claim 13, Lau et al. fail to teach the channel layer includes an InAs layer sandwiched between 2 layers with different composition than InAs. Koo et al. teach a channel comprises of an InAs sandwiched between Ga layers. See para 004. It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching Koo et al. into the device of Lau et al. to achieve high electron mobility. See para 0040. With respect to claim 14, Lau et al. teach the channel layer includes AlSb or III-V material. See para 0031. With respect to claim 15, Lau et al. teach the channel layer includes AlGaSb or III-V material. See para 0031. With respect to claim 16, Lau et al. teach the channel layer includes AlInSb or III-V material. See para 0031. With respect to claim 17, Lau et al. teach the channel layer includes InAs or III-V material. See para 0031. With respect to claim 18, Lau et al. teach the channel layer is disposed within a transistor. See figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2. With respect to claim 19, Lau et al. in combination with Lutgen et al. teach the barrier layer is P-type or N-type. See col. 5, lines 5-20 of Lutgen e tal. With respect to claim 20, Lau et al. teach the prelayer includes arsenic. See figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2. Examiner’s Cited References The cited references generally show the similar or related structure having a barrier layer between a substrate and a channel layer and having a dopant concentration about 1017 cm-3 as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
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