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Patent Application 18603156 - Computer System with Reconfigurable Processors - Rejection

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Patent Application 18603156 - Computer System with Reconfigurable Processors

Title: Computer System with Reconfigurable Processors

Application Information

  • Invention Title: Computer System with Reconfigurable Processors
  • Application Number: 18603156
  • Submission Date: 2025-05-14T00:00:00.000Z
  • Effective Filing Date: 2024-03-12T00:00:00.000Z
  • Filing Date: 2024-03-12T00:00:00.000Z
  • National Class: 718
  • National Sub-Class: 104000
  • Examiner Employee Number: 89896
  • Art Unit: 2196
  • Tech Center: 2100

Rejection Summary

  • 102 Rejections: 0
  • 103 Rejections: 3

Cited Patents

The following patents were cited in the rejection:

Office Action Text


    DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b)  CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.


The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.


Claim 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA  35 U.S.C. 112, the applicant), regards as the invention.

As per claim 1, it is not clear what “an array of reconfigurable processing units configurable to allocate a plurality of sets of processing units in the array  .  .  .  a plurality of execution fragment resource groups EFRG” should be construed as.  [0007] of the spec appears to suggest that processing units and EFRGs are the same thing as in “the array of processing units is configurable to allocate a plurality of sets of processing units in the array, designated execution fragment resource groups EFRGs, to implement respective execution fragments of the data processing operation”.  In claim 1, they appear to be two distinct elements.  This creates confusion.  In this rejection, they are assumed to be the same thing. 

All dependent claims (not mentioned above) are rejected by virtue of base claim. 

Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Prabhakar et al (Prabhakar, Raghu, et al. "Plasticine: A reconfigurable architecture for parallel paterns." ACM SIGARCH Computer Architecture News 45.2 (2017): 389-402.) (hereinafter Prabhakar) in view of Sachs et al (US 4884197 ) (hereinafter Sachs) further in view of Dasgupta et al (US 2009/0241117 ) (hereinafter Dasgupta).

As per claim 1, Prabhakar teaches: 

A computer system, comprising:
an array of reconfigurable processing units configurable to allocate a plurality of sets of processing units in the array (Prabhakar, 3.1 Pattern Compute Unit—under BRI, sets of processing units in the array can be PCUs);
a plurality of execution fragment resource groups EFRG (Prabhakar, 3.1 Pattern Compute Unit);
wherein the array is configured into the plurality of EFRGs for executing fragments of a data processing operation (Prabhakar, 3.1 Pattern Compute Unit—under BRI, fragments of a data processing operation can be parallel pattern in an application)
wherein an execution fragment comprises, in a coarse-grained reconfigurable architecture CGRA, a subset of operations (Prabhakar, 3.1 Pattern Compute Unit); 

Prabhakar does not expressly teach: 
the fragments having quiesce boundaries;
and  
wherein the subset of operations is in a control and data flow graph of the data processing operation;
a quiesce controller for distributing quiesce control signals to quiesce logic associated with the processing units in the array, and for receiving quiesce ready signals from the respective sets of processing units.


However, Sachs discloses: 
the fragments having quiesce boundaries (Sachs, Abstract-- quiesce boundaries exist in order to context switch);
and  
a quiesce controller for distributing quiesce control signals to quiesce logic associated with the processing units in the array, and for receiving quiesce ready signals from the respective sets of processing units (Sachs, col 15, ll60-63, ll66-68—interrupts can be seen as quiesce control signals and maskable interrupts signals can be seen quiesce ready signals [when not masked, the processor is quiesce ready]).

Both Sachs and Prabhakar pertain to the art of configurable logic.  

It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Sach’s method to interrupt and ready to be interrupt because it is well-known that in an interrupt scheme, devices don't have to constantly check for interrupt events. Constant checking (polling) can waste processing time, and insufficient polling can cause latency, since this wait leaves devices unattended.  

Prabhakar/Sachs does not expressly teach: 

wherein the subset of operations is in a control and data flow graph of the data processing operation;

However, Dasgupta discloses: 
wherein the subset of operations is in a control and data flow graph of the data processing operation (Dasgupta, [0109]);

Both Dasgupta and Prabhakar/Sachs pertain to the art of data processing systems.  

It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Dasgupta’s method to have operations in control and data flow graph because it is well-known in the art that CFGs, which represent the execution flow of a program, are crucial for identifying potential issues like unreachable code and infinite loops. DFGs, on the other hand, focus on the movement and transformation of data, enabling optimization by identifying redundancies and dependencies, and aiding in detecting errors like uninitialized variables.   

As per claim 2, Prabhakar/Sachs/Dasgupta teaches: 
The system of claim 1 (see rejection on claim 1), further configured to generate the control signal in response to an internal event originating in the array (Sachs, col 15, ll60-63).

Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Prabhakar/Sachs/Dasgupta as applied to claim 1 above, and further in view of Hornick et al (US 7117391) (hereinafter Hornick).

As per claim 3, Prabhakar/Sachs/Dasgupta teaches:
The system of claim 1 (see rejection on claim 1).

Prabhakar/Sachs/Dasgupta does not expressly teach:
 further configured to generate the control signal in response to an external event originating outside the array.

However, Hornick discloses: 
further configured to generate the control signal in response to an external event originating outside the array (Hornick, col 5, ll13-15).

Both Hornick and Prabhakar/Sachs/Dasgupta pertain to the art of interrupt logic.  

It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Hornick’s method to interrupt based on external event because it is well-known in the art that external interrupts offer several benefits, primarily focusing on efficiency, speed, and real-time responsiveness. They allow a system to respond to external events almost instantaneously, freeing up the processor to perform other tasks.   

Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Prabhakar/Sachs/Dasgupta as applied to claim 1 above, and further in view of Ratiner et al (US 2019/0334922 ) (hereinafter Ratiner).

As per claim 4, Prabhakar/Sachs/Dasgupta teaches: 
The system of claim 1 (see rejection on claim 1).

Prabhakar/Sachs/Dasgupta does not expressly teach:
wherein the control signal is asynchronous relative to the plurality of execution fragments.

However, Ratiner discloses: 
wherein the control signal is asynchronous relative to the plurality of execution fragments (Ratiner, [0035]).

Both Ratiner and Prabhakar/Sachs/Dasgupta pertain to the art of interrupt logic.  

It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Ratiner’s method to async interrupt because it is well-known in the art that interrupting asynchronous processes offers benefits like improved application performance, better resource utilization, and enhanced user experience, especially for long-running or resource-intensive tasks.  

Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLIE SUN whose telephone number is (571)270-5100. The examiner can normally be reached 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached on (571) 270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHARLIE SUN/Primary Examiner, Art Unit 2196                                                                                                                                                                                                        


    
        
            
        
            
        
            
        
            
        
            
        
            
        
            
        
            
    


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