Patent Application 18358341 - MAGNETIC TUNNEL JUNCTION MEMORY CELL WITH A

Title: MAGNETIC TUNNEL JUNCTION MEMORY CELL WITH A BUFFER-LAYER AND METHODS FOR FORMING THE SAME
Application Information

Invention Title: MAGNETIC TUNNEL JUNCTION MEMORY CELL WITH A BUFFER-LAYER AND METHODS FOR FORMING THE SAME
Application Number: 18358341
Submission Date: 2025-05-14T00:00:00.000Z
Effective Filing Date: 2023-07-25T00:00:00.000Z
Filing Date: 2023-07-25T00:00:00.000Z
National Class: 257
National Sub-Class: 421000
Examiner Employee Number: 97080
Art Unit: 2893
Tech Center: 2800
Rejection Summary

102 Rejections: 1
103 Rejections: 3
Cited Patents

The following patents were cited in the rejection:
Office Action Text



    DETAILED ACTION

Notice of Pre-AIA  or AIA  Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
	

Claim Objections
Claim 11 is objected to because of the following informalities: “dielectric material which around the dielectric spacer” should read for example, “dielectric material which surrounds the dielectric spacer.  Appropriate correction is required.


Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.

The following is a quotation of the first paragraph of pre-AIA  35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.

Claims 1-10 and 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA  35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. 

Regarding claims 1 and 18, the claims recite, “a ratio of an etch rate of the second dielectric oxide material to an etch rate of a material of the bottom electrode layer under an ion beam etch condition employed in the ion beam etch process is in a range from 0.8 to 1.3; and
a ratio of an etch rate of the first dielectric oxide material to the etch rate of the material of the bottom electrode layer under the ion beam etch condition employed in the ion beam etch process is in a range from 2.2 to 2.9”, however, the disclosure does not have support for all the materials that would have the etch rate ratio within the claimed range.
	Claims 2-10 depend upon claim 1 and do not rectify the problem therefore, they are also rejected.
	Claims 19-20 depend upon claim 18 and do not rectify the problem therefore, they are also rejected.


The following is a quotation of 35 U.S.C. 112(b):
(b)  CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.


The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.


Claims 1-10 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA  35 U.S.C. 112, the applicant regards as the invention. 


	Regarding claims 1 and 18, the claims recite, “ion beam etch condition” which is indefinite as it is not clear what are the ion beam etch conditions and if these conditions are same for all the materials.
	Claims 2-10 depend upon claim 1 and do not rectify the problem therefore, they are also rejected.
	Claims 19-20 depend upon claim 18 and do not rectify the problem therefore, they are also rejected.


Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.


(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.

Claims 11, 14 and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Noh (US 2018/0212140 A1).

Regarding claim 11, Noh teaches a method of forming a memory device (see e.g., Figures 10-15), the method comprising:
forming a first metal line structure (see e.g., first lower interconnect structure including cell contact plugs 122 and lower conductive patterns 124, Para [0064], Figures 10-15) in a dielectric material layer (see e.g., the first lower interconnect structure formed in the lower interlayered insulating layer 120, Para [0064], Figures 101-5) overlying a substrate (see e.g., the lower interlayered insulating layer formed on a substrate 100);
forming a dielectric layer stack (see e.g., etch stop layer 128 and the mold insulating layer 130, Para [0066], Figures 10-15) including, from bottom to top, a dielectric cap layer (see e.g., bottommost layer the etch stop layer 128, Para [0066], Figures 10-15), a connection-via-level dielectric layer (see e.g., first mold insulating layer 132, Para [0066], Figures 10-15), and a buffer layer (see e.g., the second mold insulating layer 134 the top most layer, Para [0066], Figures 10-15) over the first metal line structure and the dielectric material layer and;(see e.g., the etch stop layer 128 and the mold insulating layer 130 formed over the first lower interconnect structure and the lower interlayered insulating layer 120, Figures 10-15)
forming a connection via structure (see e.g., the bottom electrode contact BEC, Para 0067], Figures 10-15) through the dielectric layer stack (see e.g., the bottom electrode contact BEC penetrates the etch stop layer 128 and the mold insulating layer 130, Figures 10-15) on a top surface of the first metal line structure (see e.g., the bottom electrode contact BEC formed on a top surface of the lower conductive pattern 124, Para [0067], Figures 10-15);
forming a bottom electrode layer (see e.g., bottom electrode layer BEL, Para [0068], Figure 11) and magnetic tunnel junction (MTJ) layers (see e.g., the magnetic tunnel junction layer MTJL, Para [0068], Figure 11) over the dielectric layer stack (see e.g., the bottom electrode layer BEL and the magnetic tunnel junction layer MTJL formed over the etch stop layer 128 and the mold insulating layer 130, Figure 11);
forming a metallic etch mask portion over the MTJ layers in a memory array region; and (see e.g., the top electrode TE, made of a conductive metal nitride such as titanium nitride or tungsten nitride, is used as an etch mask over the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL in the memory region R1, Paras [0068], [0070], Figure 12)
patterning the MTJ layers and the bottom electrode layer into a magnetic tunnel junction (MTJ) memory cell by performing an ion beam etch process (see e.g., ion beam etching process is used to pattern the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL to form memory element with a bottom electrode BE and magnetic tunnel junction MTJ, Para [0070], Figure 13);
forming a dielectric spacer laterally surrounding the MTJ memory cell; and (see e.g., cap insulating layer 140 covering the side surfaces of the memory element ME, Para [0071], Figure 14)
forming a memory-level dielectric layer (see e.g., upper interlayered insulating layer 150, Para [0073], Figure 15) comprising a dielectric material (see e.g., the upper interlayered insulating layer 150 is made of an insulating material, Para [0073], Figure 15) which around the dielectric spacer (see e.g., the upper interlayered insulating layer 150 surround the capping insulating layer 140, Figure 15), wherein the dielectric material of the memory-level dielectric layer is formed directly on a recessed horizontal surface segment of a top surface of the buffer layer in the memory array region (see e.g., the upper interlayered insulating layer 150 is formed on the recessed portion 134a of the second mold insulating layer 134 in the memory region R1, Figure 15), and directly contacts a horizontal surface of the connection-via-level dielectric layer in a logic region (see e.g., the upper interlayered insulating layer 150 will be directly on the top surface of the first mold insulating layer 132 in case the recessed portion 134b is wholly removed from the logic region R2, Para [0070], Figure 15) that is laterally spaced from the memory array region (see e.g., the logic region R2 is laterally spaced from the memory region R1, Figure 15).


	Regarding claim 14, Noh, as referred in claim 11, further teaches
further comprising planarizing the memory-level dielectric layer such that the top surface of the memory-level dielectric layer is formed in a horizonal plane including a top surface of the metallic etch mask portion (see e.g., the upper interlayered insulating layer 150 is planarized such that its top surface is at a horizontal level with the top electrode TE, Para [0073], Figure 15).  

Regarding claim 17, Noh teaches a method of forming a memory device (see e.g., Figures 10-15), the method comprising:
forming metal line structures (see e.g., first lower interconnect structure including cell contact plugs 122 and lower conductive patterns 124, Para [0064], Figures 10-15) in a dielectric material layers (see e.g., the first lower interconnect structure formed in the lower interlayered insulating layer 120, Para [0064], Figures 101-5) overlying a substrate (see e.g., the lower interlayered insulating layer formed on a substrate 100);
forming a dielectric layer stack (see e.g., etch stop layer 128 and the mold insulating layer 130, Para [0066], Figures 10-15) including, from bottom to top, a dielectric cap layer, (see e.g., bottommost layer the etch stop layer 128, Para [0066], Figures 10-15), a connection-via-level dielectric layer (see e.g., first mold insulating layer 132, Para [0066], Figures 10-15), and a buffer layer (see e.g., the second mold insulating layer 134 the top most layer, Para [0066], Figures 10-15) over the dielectric material layers(see e.g., the etch stop layer 128 and the mold insulating layer 130 formed over the first lower interconnect structure and the lower interlayered insulating layer 120, Figures 10-15);
forming an array of connection via structures (see e.g., an array of the bottom electrode contact BEC, Para [0067], Figures 10-15) through the dielectric layer stack (see e.g., the bottom electrode contact BEC penetrates the etch stop layer 128 and the mold insulating layer 130, Figures 10-15) on a respective one of the metal line structures; and (see e.g., each of the bottom electrode contact BEC formed on a respective top surface of the lower conductive pattern 124, Para [0067], Figures 10-15)
forming a bottom electrode layer (see e.g., bottom electrode layer BEL, Para [0068], Figure 11) and magnetic tunnel junction (MTJ) layers (see e.g., the magnetic tunnel junction layer MTJL, Para [0068], Figure 11) over the dielectric layer stack (see e.g., the bottom electrode layer BEL and the magnetic tunnel junction layer MTJL formed over the etch stop layer 128 and the mold insulating layer 130, Figure 11);
forming an array of metallic etch mask portions over the MTJ layers in a memory array region; and (see e.g., an array of the top electrode TE, made of a conductive metal nitride such as titanium nitride or tungsten nitride, is used as an etch mask over the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL in the memory region R1, Paras [0068], [0070], Figure 12)
patterning the MTJ layers and the bottom electrode layer into an array of stacks of a bottom electrode and a magnetic tunnel junction (MTJ) memory cell by performing an ion beam etch process (see e.g., ion beam etching process is used to pattern the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL to form memory elements ME with a bottom electrode BE and magnetic tunnel junction MTJ, Para [0070], Figure 13), wherein a recessed top surface of the buffer layer is formed between neighboring pairs of the bottom electrodes within the array of stacks (see e.g., the recessed portion 134a of the second mold insulating layer 134 is formed between neighboring pairs of bottom electrodes, Para [0070], Figure 15);
forming an array of a dielectric spacer around the array of stacks (see e.g., cap insulating layer 140 covering the side surfaces of the memory elements ME, Para [0071], Figure 14);
removing a portion of the buffer layer in a logic region that is adjacent to the memory array region, whereby a top surface of the connection-via-level dielectric layer is physically exposed in the logic region; and (see e.g., the logic region R2 is adjacent to the memory region R1. The recessed portion 134b in the logic region maybe wholly removed whereby a top surface of the first mold insulating layer 132 would be exposed, Para [0070], Figure 15)
forming a memory-level dielectric layer (see e.g., upper interlayered insulating layer 150, Para [0073], Figure 15) comprising a dielectric material (see e.g., the upper interlayered insulating layer 150 is made of an insulating material, Para [0073], Figure 15) directly on the array of dielectric spacer (see e.g., the upper interlayered insulating layer 150 surround the capping insulating layer 140, Figure 15), segments of the recessed top surface of the buffer layer in the memory array region (see e.g., the upper interlayered insulating layer 150 is formed on the recessed portion 134a of the second mold insulating layer 134 in the memory region R1, Figure 15), and on the physically exposed top surface of the connection-via-level dielectric layer (see e.g., the upper interlayered insulating layer 150 will be directly on the top surface of the first mold insulating layer 132 in case the recessed portion 134b is wholly removed from the logic region R2, Para [0070], Figure 15).


Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

Claims 1-10, 12 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2018/0212140 A1) in view of Tseng et al. (US 2019/0148625 A1; hereafter Tseng).

	Regarding claim 1, Noh teaches a method of forming a memory device (see e.g., Figures 10-15), the method comprising:
	forming a dielectric layer stack (see e.g., mold insulating layer 130 including first and second mold insulating layers 132 and 134, Para [0045], Figures 10-15) comprising a connection-via-level dielectric layer comprising a first dielectric oxide material (see e.g., first mold insulating layer 132 made of for example silicon oxide, Para [0045], Figures 10-15) and a buffer layer comprising a second dielectric oxide material (see e.g., second mold insulating layer 134 made of for example silicon oxynitride, Para [0045], Figures 10-15);
	forming a connection via structure through the dielectric layer stack (see e.g., bottom electrode contact BEC extending through the mold insulating layer 130, Para [0045], Figure 10);
forming a bottom electrode layer and magnetic tunnel junction (MTJ) layers over the dielectric layer stack (see e.g., a bottom electrode layer BEL and a magnetic tunnel junction layer MTJL are formed over the mold insulating layer 130, Para [0068], Figure 11);
	forming a metallic etch mask portion over the MTJ layers; and (see e.g., the top electrode TE made of a conductive metal nitride for example, titanium nitride, tantalum nitride or tungsten nitride is used as a mask to etch the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL, Paras [0068] - [0070], Figure 12)
	patterning the MTJ layers and the bottom electrode layer into a magnetic tunnel junction (MTJ) memory cell by performing an ion beam etch process (see e.g., the etching of the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL may be performed using, for example, an ion beam etching process to form the memory element ME including the bottom electrode BE and the magnetic tunnel junction MTJ, Para [0070], Figure 13), 

	 Noh does not explicitly teach
	“wherein the second dielectric oxide material and the first dielectric oxide material have material compositions such that:
		a ratio of an etch rate of the second dielectric oxide material to an etch rate of a material of the bottom electrode layer under an ion beam etch condition employed in the ion beam etch process is in a range from 0.8 to 1.3; and 
	a ratio of an etch rate of the first dielectric oxide material to the etch rate of the material of the bottom electrode layer under the ion beam etch condition employed in the ion beam etch process is in a range from 2.2 to 2.9”.
	
	In a similar field of endeavor Tseng teaches wherein the second dielectric oxide material (see e.g., etch stop layer 220 including silicon carbide, silicon nitride, aluminum oxide or any other suitable material, Para [0050], Figure 5) and the first dielectric oxide material (see e.g., the first interlayer dielectric ILD layer 210 which includes one or more dielectric layers, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like, Para [0040], Figure 5) have material compositions such that:
		a ratio of an etch rate of the second dielectric oxide material to an etch rate of a material of the bottom electrode layer under an ion beam etch condition employed in the ion beam etch process is in a range from 0.8 to 1.3; and 
	a ratio of an etch rate of the first dielectric oxide material to the etch rate of the material of the bottom electrode layer under the ion beam etch condition employed in the ion beam etch process is in a range from 2.2 to 2.9.

	Tseng teaches similar materials for the bottom electrode (see e.g., bottom electrode 250 made of for example, TiN, Para [0051], Figure 5), etch stop layer 220 (equivalent to instant application’s buffer layer) and the ILD layer 210 (equivalent to instant application’s connection-via-level dielectric layer) as the instant application. Therefore, the ratio of an etch rate of layer etch stop layer 220 and the bottom electrode 250 under an ion beam condition employe in an ion beam process will be in arrange from 0.8 to 1.3 and the ratio of etch rate of ILD layer 210 and the bottom electrode 250 under the ion beam etch condition employed in the ion beam etch process is in a range from 2.2 to 2.9.

	
	Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tseng’s teachings of wherein the second dielectric oxide material and the first dielectric oxide material have material compositions such that:
		a ratio of an etch rate of the second dielectric oxide material to an etch rate of a material of the bottom electrode layer under an ion beam etch condition employed in the ion beam etch process is in a range from 0.8 to 1.3; and 
	a ratio of an etch rate of the first dielectric oxide material to the etch rate of the material of the bottom electrode layer under the ion beam etch condition employed in the ion beam etch process is in a range from 2.2 to 2.9.
in the method of Noh in order to provide etch selectivity.	


Regarding claim 2, Noh, as modified by Tseng, teaches the limitations of claim 1 as mentioned above. Noh does not explicitly teach 
“wherein the first dielectric oxide material comprises undoped silicate glass or a doped silicate glass.”


In a similar field of endeavor Tseng teaches 
wherein the first dielectric oxide material comprises undoped silicate glass or a doped silicate glass (see e.g., the first interlayer insulating layer ILD 210 made of fluorine-doped silicate glass, Para [0040], Figure 5).

Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tseng’s teachings of wherein the first dielectric oxide material comprises undoped silicate glass or a doped silicate glass in the method of Noh since these dielectrics are used in thick layers and have low dielectric constant thereby preventing change built up.


Regarding claim 3, Noh, as modified by Tseng, teaches the limitations of claim 2 as mentioned above. Noh does not explicitly teach
“wherein the second dielectric oxide material comprises aluminum oxide or titanium pentoxide.”

In a similar field of endeavor Tseng teaches 
wherein the second dielectric oxide material comprises aluminum oxide or titanium pentoxide (see e.g., the etch stop layer 220 made of aluminum oxide, Para [0050], Figure 5).

Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tseng’s teachings of wherein the second dielectric oxide material comprises aluminum oxide or titanium pentoxide in the method of Noh as aluminum oxide provides etch selectivity.


Regarding claim 4, Noh, as modified by Tseng teaches the limitations of claim 1 as mentioned above. Noh further teaches
wherein the dielectric layer stack further comprises a dielectric capping layer that underlies the connection-via-level dielectric layer (see e.g., etch stop layer 128 underlying the mold insulating layer 130 and includes silicon nitride or silicon carbonitride, Para [0066], Figures 10-15).


Regarding claim 5, Noh, as modified by Tseng teaches the limitations of claim 4 as mentioned above. Noh further teaches 
wherein the dielectric capping layer comprises a material selected from silicon nitride and silicon carbide (see e.g., etch stop layer 128 underlying the mold insulating layer 130 and includes silicon nitride or silicon carbonitride, Para [0066], Figures 10-15).


Regarding claim 6, Noh, as modified by Tseng teaches the limitations of claim 1 as mentioned above. Noh further teaches 
further comprising: a semiconductor substrate (see e.g., silicon, germanium or a silicon-germanium substrate 100, Para [0044], Figures 10-15) underlying the dielectric layer stack (see e.g., the substrate 100 underlies the mold insulating layer 130); and dielectric material layers (see e.g., lower insulating layer 120 which maybe a multi-layered structure, Para [0064], Figures 10-15) embedding metal interconnect structures (see e.g., the first lower interconnect structure, formed in the lower insulating layer 120, includes cell contact plugs 122 and lower conductive patterns 124, Para [0064], Figures 10-15) and located between the semiconductor substrate and the dielectric layer stack (see e.g., the lower insulating layer 120 is located between the substrate 100 and the mold insulating layer 130, Figures 10-15), wherein the dielectric layer stack is formed over a topmost surface of the dielectric material layers (see e.g., the mold insulating layer130 is formed over the lower interlayered insulating layer 120, Para [0064], Figures 10-15).


Regarding claim 7, Noh, as modified by Tseng teaches the limitations of claim 1 as mentioned above. Noh further teaches 
wherein the bottom electrode layer comprises titanium nitride (see e.g., the bottom electrode BE is formed of metal nitride for example, titanium nitride, Para [0049], Figures 11-15).


Regarding claim 8, Noh, as modified by Tseng teaches the limitations of claim 1 as mentioned above. Noh further teaches 
wherein the buffer layer (see e.g., second mold insulating layer 134, Para [0045], Figures 10- 13) after the ion beam etch (see e.g., etching of the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL is performed using for example, ion beam etching, Para [0070], Figure 13) process comprise a recessed surface (see e.g., the ion beam etching process is performed in such a way that an etch rate of the second mold insulating layer 134 is higher than that of the magnetic tunnel junction layer MTJL. Thus, between the magnetic tunnel junctions MTJ, a top surface of the second mold insulating layer 134 may be recessed during the formation of the memory elements ME. Owing to a difference in pattern density between the first and second regions R1 and R2, the recess depth of the top surface of the second mold insulating layer 134 may be greater on the second region R2 than on the first region R1. Accordingly, the second mold insulating layer 134 may be formed to have recessed top surfaces 134a and 134b whose levels are different from each other. The recessed top surface 134b of the second mold insulating layer 134 on the second region R2 may be lower than the recessed top surface 134a of the second mold insulating layer 134 on the first region R1. The second mold insulating layer 134 may be wholly removed from the second region R2, Para [0070], Figure 13) that is formed above a horizontal plane including a bottom surface of the remaining portion of the buffer layer (see e.g., the recessed portions 134a and 134b are formed above the bottom surface of the remaining portion of the second mold insulating layer 134 as shown in Figure 13).


Regarding claim 9, Noh, as modified by Tseng teaches the limitations of claim 1 as mentioned above. Noh further teaches 
further comprising removing a first portion of the buffer layer from a logic region to expose a top surface of the connection-via-level dielectric layer without removing a second portion of the buffer layer from a memory array region that includes the MTJ memory cell (see e.g., ion beam etching process forms recessed portion 134a in the memory region R1 and 134b in the logic region. The second mold insulating layer 134 may be wholly removed from the second region R2, Para [0070], Figure 13).


Regarding claim 10, Noh, as modified by Tseng teaches the limitations of claim 9 as mentioned above. Noh further teaches 
further comprising forming a memory level dielectric layer directly on the top surface of the contact-via-level dielectric layer and the second portion of the buffer layer (see e.g., upper interlayered insulating layer 150 formed on the recessed portions 134a of the second mold insulating layer portions 134. In case the recessed portion 134b is wholly removed from the logic region the upper interlayered insulating layer 150 would be directly on the top surface of first mold insulating layer 132, Para [0070], Figure 15).


Regarding claim 12, Noh, as referred in claim 11, does not explicitly teach
“wherein the buffer layer comprises aluminum oxide (Al2O3)”.
	

In a similar field of endeavor Tseng teaches 
wherein the buffer layer comprises aluminum oxide (Al2O3) (see e.g., the etch stop layer 220 made of aluminum oxide, Para [0050], Figure 5).

Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tseng’s teachings of wherein the buffer layer comprises aluminum oxide (Al2O3) in the method of Noh as aluminum oxide provides etch selectivity.



Regarding claim 18, Noh, as referred in claim 17, further teaches
wherein:
the connection-via-level dielectric layer comprises a first dielectric oxide material (see e.g., first mold insulating layer 132 made of for example silicon oxide, Para [0045], Figures 10-15);
the buffer layer comprises a second dielectric oxide material (see e.g., second mold insulating layer 134 made of for example silicon oxynitride, Para [0045], Figures 10-15);
the array of stacks is patterned by performing an ion bean etch process (see e.g., the etching of the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL may be performed using, for example, an ion beam etching process to form the memory elements ME including the bottom electrode BE and the magnetic tunnel junction MTJ, Para [0070], Figure 13);

Noh does not explicitly teach
“a ratio of an etch rate of the second dielectric oxide material to an etch rate of a material of the bottom electrode layer under an ion beam etch condition employed in the ion beam etch process is in a range from 0.8 to 1.3; and
a ratio of an etch rate of the first dielectric oxide material to the etch rate of the material of the bottom electrode layer under the ion beam etch condition employed in the ion beam etch process is in a range from 2.2 to 2.9”.

In a similar field of endeavor Tseng teaches 
a ratio of an etch rate of the second dielectric oxide material to an etch rate of a material of the bottom electrode layer under an ion beam etch condition employed in the ion beam etch process is in a range from 0.8 to 1.3; and
a ratio of an etch rate of the first dielectric oxide material to the etch rate of the material of the bottom electrode layer under the ion beam etch condition employed in the ion beam etch process is in a range from 2.2 to 2.9

Tseng teaches similar materials for the bottom electrode (see e.g., bottom electrode 250 made of for example, TiN, Para [0051], Figure 5), aluminum oxide etch stop layer 220 (equivalent to instant application’s buffer layer) and the doped silicate glass ILD layer 210 (equivalent to instant application’s connection-via-level dielectric layer) as the instant application. Therefore, the ratio of an etch rate of layer etch stop layer 220 and the bottom electrode 250 under an ion beam condition employe in an ion beam process will be in arrange from 0.8 to 1.3 and the ratio of etch rate of ILD layer 210 and the bottom electrode 250 under the ion beam etch condition employed in the ion beam etch process is in a range from 2.2 to 2.9.
	
	Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tseng’s teachings of 
		a ratio of an etch rate of the second dielectric oxide material to an etch rate of a material of the bottom electrode layer under an ion beam etch condition employed in the ion beam etch process is in a range from 0.8 to 1.3; and 
	a ratio of an etch rate of the first dielectric oxide material to the etch rate of the material of the bottom electrode layer under the ion beam etch condition employed in the ion beam etch process is in a range from 2.2 to 2.9  in the method of Noh in order to provide etch selectivity.	


Regarding claim 19, Noh, as modified by Tseng, teaches the limitations of claim 18 as mentioned above. Noh does not explicitly teach
“wherein: the first dielectric oxide material comprises undoped silicate glass or a doped silicate glass; and the second dielectric oxide material comprises aluminum oxide or titanium pentoxide”.



In a similar field of endeavor Tseng teaches 
wherein: the first dielectric oxide material comprises undoped silicate glass or a doped silicate glass (see e.g., the first interlayer insulating layer ILD 210 made of fluorine-doped silicate glass, Para [0040], Figure 5); and the second dielectric oxide material comprises aluminum oxide or titanium pentoxide (see e.g., the etch stop layer 220 made of aluminum oxide, Para [0050], Figure 5).

Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tseng’s teachings of wherein: the first dielectric oxide material comprises undoped silicate glass or a doped silicate glass; and the second dielectric oxide material comprises aluminum oxide or titanium pentoxide in the method of Noh since these dielectrics are used in thick layers and have low dielectric constant thereby preventing change built up and aluminum oxide provides etch selectivity.



Regarding claim 20, Noh, as modified by Tseng, teaches the limitations of claim 18 as mentioned above. Noh further teaches 
wherein the dielectric capping layer comprises a material selected from silicon nitride and silicon carbide (see e.g., etch stop layer 128 made of silicon nitride or silicon carbide, Para [0066], Figures 10-15).


Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2018/0212140 A1) in view of AVCI et al. (US 2020/0105743 A1; hereafter AVCI).

Regarding claim 13, Noh, as referred in claim 11, does not explicitly teach
“wherein the buffer layer comprises tantalum pentoxide (Ta2O5)”.

However, Noh’s second mold insulating layer 134 is made of dielectric material such as silicon nitride or silicon oxynitride is functionally equivalent to a tantalum pentoxide layer as taught by AVCI.

In a similar field of endeavor AVCI teaches a dielectric layer made from one or a combination of dielectric materials such as silicon dioxide (Si02), aluminum oxide (Al203), hafnium oxide (Hf02), zirconium dioxide (Zr02), tantalum pentoxide (Ta2O5), titanium dioxide (Ti02), and lanthanum oxide (La203), among others, a carbon (C)-doped oxide, a nitride, such as silicon nitride (Si3N4), or a carbide, such as silicon carbide (SiC).

Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement AVCI’s teachings of wherein the buffer layer comprises tantalum pentoxide (Ta2O5) in the method of Noh in order to use any of the alternatively usable materials and arrive at the claimed invention. 


Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2018/0212140 A1) in view of Sung et al. (US 2017/0222128 A1; hereafter Sung).

Regarding claim 15, Noh, as referred in claim 14, does not explicitly teach
“further comprising depositing and patterning at least one dielectric etch stop layer such that the at least one dielectric etch stop layer covers the metallic etch mask portion and does not cover an area within the logic region”.

In a similar field of endeavor Sung teaches 
further comprising depositing and patterning at least one dielectric etch stop layer such that the at least one dielectric etch stop layer covers the metallic etch mask portion and does not cover an area within the logic region (see e.g., third dielectric layer 127C which covers a top surface of the dielectric layer 129 and a top surface and sidewalls of the top electrode 133. The third dielectric layer 127C is formed in the MRAM cell region 100A and not in the logic region 100B, Paras [0038], [0057], Figure 14; Examiner’s interpretation: 127C is made of silicon nitride which functions as an etch stop layer).

Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Sung’s teachings of further comprising depositing and patterning at least one dielectric etch stop layer such that the at least one dielectric etch stop layer covers the metallic etch mask portion and does not cover an area within the logic region in the method of Noh since the etch stop layer functions as an etch stop to a passivation operation.


Regarding claim 16, Noh, as modified by Sung, teaches the limitations of claim 15 as mentioned above. Noh further teaches
forming a connection via structure (see e.g., peripheral via plug 155, Para [0075], Figure 15) and wherein the connection via structure vertically extends through, and contacts, the dielectric layer stack and contacts one of the first metal line structures (see e.g., peripheral via plug 155 vertically extends through and contacts the first mold insulating layer 132 and the etch stop layer 128 and contacts the lower interconnection line 125, Para [0075], Figure 15).

Noh does not explicitly teach
“further comprising: forming a via-level dielectric layer over the at least one dielectric etch stop layer; and forming a contact via structure and a connection via structure through the via-level dielectric layer, wherein the contact via structure vertically extends through, and contacts, the at least one dielectric etch stop layer and contacts a top surface of the metallic etch mask portion”.

In a similar field of endeavor Sung teaches
further comprising: forming a via-level dielectric layer (see e.g., inter-metal dielectrics IMDs 125, Paras [0035], Figure 16) over the at least one dielectric etch stop layer (see e.g., the inter-metal dielectrics IMDs 125 is formed over the third dielectric layer 127C, Figure 16); and forming a contact via structure (see e.g., metal line 123’ formed in the MRAM cell region 100a, Para [0064], Figure 16) and a connection via structure (see e.g., metal line 123’ formed in the logic region 100B, Para [0064], Figure 16) through the via-level dielectric layer (see e.g., the metal line 123’ in both the MRAM cell region 100A and the logic region 100B is formed through the inter-metal dielectrics IMDs 125, Figure 16), wherein the contact via structure vertically extends through, and contacts, the at least one dielectric etch stop layer and contacts a top surface of the metallic etch mask portion (see e.g., the metal line 123’ in the MRAN region 100A vertically extends through and contacts the third dielectric layer 127C and contacts a top surface of the top electrode 133, Figure 16), 

Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Sung’s teachings of  further comprising: forming a via-level dielectric layer over the at least one dielectric etch stop layer; and forming a contact via structure and a connection via structure through the via-level dielectric layer, wherein the contact via structure vertically extends through, and contacts, the at least one dielectric etch stop layer and contacts a top surface of the metallic etch mask portion in the method of Noh in order to provide electrical connections. 


Conclusion
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/FAKEHA SEHAR/Examiner, Art Unit 2893                                                                                                                                                                                                        
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893