Patent Application 18314144 - CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - Rejection
Patent Application 18314144 - CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF
Title: CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF, AND LIGHT EMITTING MODULE
Application Information
- Invention Title: CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF, AND LIGHT EMITTING MODULE
- Application Number: 18314144
- Submission Date: 2025-05-21T00:00:00.000Z
- Effective Filing Date: 2023-05-09T00:00:00.000Z
- Filing Date: 2023-05-09T00:00:00.000Z
- National Class: 361
- National Sub-Class: 783000
- Examiner Employee Number: 79640
- Art Unit: 3729
- Tech Center: 3700
Rejection Summary
- 102 Rejections: 1
- 103 Rejections: 2
Cited Patents
No patents were cited in this rejection.
Office Action Text
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I (claims 1-9) in the reply filed on April 16, 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent 9,042,113 to Kim.
Regarding claim 1, Kim discloses a manufacturing method of a circuit board, comprising: providing a substrate structure (see Fig. 8), wherein the substrate structure comprises a substrate(111) and a first circuit layer (130) disposed on the substrate; forming a first insulating layer on the substrate (140), wherein the first insulating layer has an insulating opening (141) exposing a portion of the first circuit layer (see Fig. 12); forming a first conductive layer (160) on the substrate, wherein the first conductive layer covers the first insulating layer (140) having the insulating opening (141) and the portion of the first circuit layer exposed by the insulating opening (see Fig. 14); forming a second insulating layer (220) on the first conductive layer, wherein the first conductive layer has a first portion and a second portion, the first portion does not overlap the second insulating layer, and the second portion overlaps the second insulating layer (see Fig. 15); forming a second conductive layer (170) on the first portion (see Fig. 16); removing the second insulating layer (see Fig. 17) and the second portion, the first portion and the second conductive layer forming a second circuit layer (see Fig. 18); and forming a solder resist layer (180) on the second circuit layer, wherein the solder resist layer has a solder resist opening exposing a portion of the second circuit layer (see Fig. 19).
Regarding claim 2, Kim discloses disposing an insulating film (140) on the substrate to cover the first circuit layer; and removing a portion of the insulating film to form the first insulating layer having the insulating opening (see Figs. 10-12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of U.S. Patent 8,878,077 to Ito et al.
Kim does not explicitly disclose how the insulating film is formed on the substrate; process of forming opening and conductive layers. Ito et al teach the process of manufacturing a circuit board (1, see Fig. 7) comprising the steps of: (claim 3) laying the insulating film on the substrate at one time; (claim 4) pressing the insulating film disposed on the substrate before removing the portion of the insulating film to form the first insulating layer having the insulating opening (see Fig. 3C); (claim 5) performing a photolithography process to form opening (VH, Fig. 4A); (claim 6) the first conductive layer is formed by including a sputtering process, and the second conductive layer is formed by including an electroplating process (see Col. 6, line 56-57 and Col. 7, line 7); (claim 7) the first conductive layer (420/44)at least partially covers a sidewall of the insulating opening (see Fig. 2B/5A) for forming the conductive layer on the insulating layer having good adhesive condition (see Col. 10, lines 46-49). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention Kim by utilizing the processes of forming the insulating layer, opening and conductive layer as taught by Ito et al for obtaining a circuit board having the conductive layer on the insulating layer having good adhesive condition thereon.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of U.S. Patent 8,309,860 to Sunohara at al.
Kim does not disclose a chip on a substrate structure. Sunohara et al teach the steps of disposing a chip (10) on the substrate structure (1, see Fig. 2A) and electrically connecting the first circuit layer (see Fig. 3A); and disposing an insulating film (500) on the substrate to cover the first circuit layer and the chip (see Fig. 2B); and removing a portion of the insulating film to form the first insulating layer having the insulating opening (see Fig. 2C) for manufacturing an electronic component built-in circuit board at low cost (see Col. 2, lines 6-10). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention Kim by utilizing the method of disposing a chip on the circuit structure as taught by Sunohara et al for manufacturing the circuit board having built-in electronic component at low cost.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Prior art cited for their general teachings of manufacturing a circuit board.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONGHAI D NGUYEN whose telephone number is (571)272-4566. The examiner can normally be reached M-F 9:00-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sunil K. Singh can be reached at 571-272-3460. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DN/ /DONGHAI D NGUYEN/May 17, 2025 Primary Examiner, Art Unit 3729
