Patent Application 18307734 - DYNAMIC MEMORY REFRESH INTERVAL TO REDUCE - Rejection
Patent Application 18307734 - DYNAMIC MEMORY REFRESH INTERVAL TO REDUCE
Title: DYNAMIC MEMORY REFRESH INTERVAL TO REDUCE BANDWIDTH PENALTY
Application Information
- Invention Title: DYNAMIC MEMORY REFRESH INTERVAL TO REDUCE BANDWIDTH PENALTY
- Application Number: 18307734
- Submission Date: 2025-05-19T00:00:00.000Z
- Effective Filing Date: 2023-04-26T00:00:00.000Z
- Filing Date: 2023-04-26T00:00:00.000Z
- National Class: 711
- National Sub-Class: 106000
- Examiner Employee Number: 82168
- Art Unit: 2139
- Tech Center: 2100
Rejection Summary
- 102 Rejections: 0
- 103 Rejections: 3
Cited Patents
The following patents were cited in the rejection:
Office Action Text
DETAILED ACTION
Claims 1-4 and 7-20 are present for examination.
Claims 1, 7, 12, 15-16 and 20 have been amended.
Claims 5-6 have been cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/23/2024 has been entered.
Claim Objections
Claims 1 and 12 are objected to because of the following informalities:
In claim 1, lines 12-13, where it says “region a first frequency…” should be --region at a first frequency…--.
In claim 12, line 13, where it says “memory region a first frequency…” should be --memory region at a first frequency…--.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-16 of U.S. Patent No. 10,896,715 contains every element of claims 1-20 of the instant application and as such anticipates claims 1-4 and 7-20 of the instant application.
Claim 1 of the present application corresponds to claim 1 of the ‘715 patent, where “A method…” corresponds to claim 1, line 1 of the ‘715 patent; “identifying, by a controller coupled to a dynamic memory system…” corresponds to claim 1, lines 2-6 of the ‘715 patent; “wherein the first memory region stores data…” corresponds to claim 1, lines 6-9 of the ‘715 patent; “reaching a decision, by the controller, to reduce memory bandwidth…” corresponds to claim 1, lines 13-15 of the ‘715 patent; “in response to the decision, reducing, by the controller, a rate…” corresponds to claim 1, lines 16-19 of the ‘715 patent; “including refreshing the first memory region …” corresponds to claim 1, lines 22-23 of the ‘715 patent; and “refreshing the second memory location …” corresponds to claim 1, lines 24-26 of the ‘715 patent.
Claim 2 of the present application corresponds to claim 2 of the ‘715 patent, where “refreshing the one or more…” corresponds to claim 2, lines 2-3 of the ‘715 patent.
Claim 3 of the present application corresponds to claim 3 of the ‘715 patent, where “wherein the refreshing is performed by repeating…” corresponds to claim 3, lines 1-4 of the ‘715 patent; “reading data from a memory location…” corresponds to claim 3, line 5 of the ‘715 patent; and “writing the data back to the memory location…” corresponds to claim 3, lines 6 of the ‘715 patent.
Claim 4 of the present application corresponds to claim 4 of the ‘715 patent, where “wherein each of the plurality of memory regions…” corresponds to claim 4, line 2 of the ‘715 patent.
Claim 7 of the present application corresponds to claim 5 of the ‘715 patent, where “wherein the first region…” corresponds to claim 4, lines 1-2 of the ‘715 patent.
Claim 8 of the present application corresponds to claim 6 of the ‘715 patent, where “wherein the first frequency is below a threshold…” corresponds to claim 6, lines 1-6 of the ‘715 patent.
Claim 9 of the present application corresponds to claim 7 of the ‘715 patent, where “wherein the data of the first type…” corresponds to claim 7, lines 1-3 of the ‘715 patent.
Claim 10 of the present application corresponds to claim 1 of the ‘715 patent, where “refreshing the one or more…” corresponds to claim 1, lines 10-12 of the ‘715 patent.
Claim 11 of the present application corresponds to claim 8 of the ‘715 patent, where “partitioning memory in the dynamic memory system…” corresponds to claim 8, lines 2-4 of the ‘715 patent; and “storing data in the plurality of regions…” corresponds to claim 8, lines 5-6 of the ‘715 patent.
Claim 12 of the present application corresponds to claim 9 of the ‘715 patent, where “A system…” corresponds to claim 9, line 1 of the ‘715 patent; “a dynamic memory system having a plurality…” corresponds to claim 9, lines 2-3 of the ‘715 patent; “wherein a first memory region in the plurality…” corresponds to claim 9, lines 4-7 of the ‘715 patent; “a controller coupled to the dynamic memory system…” corresponds to claim 9, lines 8-9 of the ‘715 patent; “monitor usages of memory access bandwidth…” corresponds to claim 9, lines 10-11 of the ‘715 patent; “determine to reduce memory bandwidth…” corresponds to claim 9, lines 12-13 of the ‘715 patent; “reduce a refresh rate…” corresponds to claim 9, lines 14-16 of the ‘715 patent; “including refreshing the first memory region…” corresponds to claim 9, lines 22-23 of the ‘715 patent; and “refreshing a second memory location in the plurality…” corresponds to claim 9, lines 24-26 of the ‘715 patent.
Claim 13 of the present application corresponds to claim 10 of the ‘715 patent, where “wherein each of the plurality of memory regions…” corresponds to claim 10, lines 1-3 of the ‘715 patent; and “refresh the one of the plurality…” corresponds to claim 10, lines 4-5 of the ‘715 patent.
Claim 14 of the present application corresponds to claim 11 of the ‘715 patent, where “wherein a refreshing operation is repeated…” corresponds to claim 11, lines 1-3 of the ‘715 patent; “reading data from a memory location…” corresponds to claim 11, line 4 of the ‘715 patent; and “writing the data back to the memory location…” corresponds to claim 11, line 5 of the ‘715 patent.
Claim 15 of the present application corresponds to claim 9 of the ‘715 patent, where “wherein each of the plurality of memory regions…” corresponds to claim 9, lines 19-21 of the ‘715 patent.
Claim 16 of the present application corresponds to claims 9 and 12 of the ‘715 patent, where “the first frequency…” corresponds to claim 12, lines 1-2 of the ‘715 patent.
Claim 17 of the present application corresponds to claim 13 of the ‘715 patent, where “wherein the first frequency is below a threshold…” corresponds to claim 13, lines 1-6 of the ‘715 patent.
Claim 18 of the present application corresponds to claim 14 of the ‘715 patent, where “wherein the data of the first type…” corresponds to claim 14, lines 1-2 of the ‘715 patent.
Claim 19 of the present application corresponds to claim 15 of the ‘715 patent, where “wherein the data of the first type represents media…” corresponds to claim 15, lines 1-3 of the ‘715 patent.
Claim 20 of the present application corresponds to claim 16 of the ‘715 patent, where “A non-transitory computer-readable storage…” corresponds to claim 16, lines 1-4 of the ‘715 patent; “partitioning memory of a dynamic memory system…” corresponds to claim 16, lines 5-7 of the ‘715 patent; “storing data in the plurality of regions…” corresponds to claim 16, lines 14-15 of the ‘715 patent; “wherein a first memory region in the plurality…” corresponds to claim 9, lines 4-7 of the ‘715 patent; “monitoring memory bandwidth usages …” corresponds to claim 16, lines 16-18 of the ‘715 patent; “determining to reduce bandwidth penalty…” corresponds to claim 16, lines 19-20 of the ‘715 patent; and “reducing a refresh rate…” corresponds to claim 16, lines 21-23 of the ‘715 patent.
Claims 1-3 of U.S. Patent No. 11,657,865 contains every element of claims 1-20 of the instant application and as such anticipates claims 1-4 and 7-20 of the instant application.
Claim 1 of the present application corresponds to claim 1 of the ‘865 patent, where “A method…” corresponds to claim 1, line 1 of the ‘865 patent; “identifying, by a controller coupled to a dynamic memory system…” corresponds to claim 1, lines 2-6 of the ‘865 patent; “wherein a first memory region in the plurality…” corresponds to claim 1, lines 6-9 of the ‘865 patent; “reaching a decision, by the controller, to reduce memory bandwidth…” corresponds to claim 1, lines 19-21 of the ‘865 patent; “in response to the decision, reducing, by the controller, a rate…” corresponds to claim 1, lines 22-25 of the ‘865 patent; “including refreshing the first memory region …” corresponds to claim 1, lines 25-26 of the ‘865 patent; and “refreshing a second memory region in the plurality…” corresponds to claim 1, lines 26-29 of the ‘865 patent.
Claim 2 of the present application corresponds to claim 1 of the ‘865 patent, where “refreshing the one or more…” corresponds to claim 1, lines 25-32 of the ‘865 patent.
Claim 3 of the present application corresponds to claim 1 of the ‘865 patent, where “wherein the refreshing is performed by repeating…” corresponds to claim 1, lines 30-32 of the ‘865 patent; “reading data from a memory location…” corresponds to claim 1, line 33 of the ‘865 patent; and “writing the data back to the memory location…” corresponds to claim 1, line 34 of the ‘865 patent.
Claim 4 of the present application corresponds to claim 1 of the ‘865 patent, where “wherein each of the plurality of memory regions…” corresponds to claim 1, lines 2-6 of the ‘865 patent.
Claim 7 of the present application corresponds to claim 1 of the ‘865 patent, where “wherein the first region…” corresponds to claim 1, lines 28-29 of the ‘865 patent.
Claim 8 of the present application corresponds to claim 1 of the ‘865 patent, where “wherein the first frequency is below a threshold…” corresponds to claim 1, lines 35-40 of the ‘865 patent.
Claim 9 of the present application corresponds to claim 1 of the ‘865 patent, where “wherein the data of the first type…” corresponds to claim 1, lines 11-13 of the ‘865 patent.
Claim 10 of the present application corresponds to claim 1 of the ‘865 patent, where “refreshing the one or more…” corresponds to claim 1, lines 9-12 of the ‘865 patent.
Claim 11 of the present application corresponds to claim 1 of the ‘865 patent, where “partitioning memory in the dynamic memory system…” corresponds to claim 1, lines 14-16 of the ‘865 patent; and “storing data in the plurality of regions…” corresponds to claim 1, lines 17-18 of the ‘865 patent.
Claim 12 of the present application corresponds to claim 2 of the ‘865 patent, where “A system…” corresponds to claim 2, line 1 of the ‘865 patent; “a dynamic memory system having a plurality…” corresponds to claim 2, lines 2-4 of the ‘865 patent; “wherein a first memory region in the plurality…” corresponds to claim 2, lines 4-7 of the ‘865 patent; “a controller coupled to the dynamic memory system…” corresponds to claim 2, lines 12-13 of the ‘865 patent; “monitor usages of memory access bandwidth…” corresponds to claim 2, lines 14-15 of the ‘865 patent; “determine to reduce memory bandwidth…” corresponds to claim 2, lines 16-17 of the ‘865 patent; “reduce a refresh rate…” corresponds to claim 2, lines 18-20 of the ‘865 patent; “including refreshing the first memory region…” corresponds to claim 2, lines 20-22 of the ‘865 patent; and “refreshing a second memory location in the plurality…” corresponds to claim 2, lines 22-24 of the ‘865 patent.
Claim 13 of the present application corresponds to claim 2 of the ‘865 patent, where “wherein each of the plurality of memory regions…” corresponds to claim 2, lines 2-4 of the ‘865 patent; and “refresh the one of the plurality…” corresponds to claim 2, lines 18-19 of the ‘865 patent.
Claim 14 of the present application corresponds to claim 2 of the ‘865 patent, where “wherein a refreshing operation is repeated…” corresponds to claim 2, lines 25-27 of the ‘865 patent; “reading data from a memory location…” corresponds to claim 2, line 28 of the ‘865 patent; and “writing the data back to the memory location…” corresponds to claim 2, line 29 of the ‘865 patent.
Claim 15 of the present application corresponds to claim 2 of the ‘865 patent, where “wherein each of the plurality of memory regions…” corresponds to claim 2, lines 2-4 of the ‘865 patent.
Claim 16 of the present application corresponds to claim 2 of the ‘865 patent, where “the first frequency…” corresponds to claim 2, lines 23-24 of the ‘865 patent.
Claim 17 of the present application corresponds to claim 2 of the ‘865 patent, where “wherein the first frequency is below a threshold…” corresponds to claim 2, lines 30-35 of the ‘865 patent.
Claim 18 of the present application corresponds to claim 2 of the ‘865 patent, where “wherein the data of the first type…” corresponds to claim 2, lines 10-11 of the ‘865 patent.
Claim 19 of the present application corresponds to claim 2 of the ‘865 patent, where “wherein the data of the first type represents media…” corresponds to claim 2, lines 7-10 of the ‘865 patent.
Claim 20 of the present application corresponds to claim 3 of the ‘865 patent, where “A non-transitory computer-readable storage…” corresponds to claim 3, lines 1-4 of the ‘865 patent; “partitioning memory of a dynamic memory system…” corresponds to claim 3, lines 5-8 of the ‘865 patent; “storing data in the plurality of regions…” corresponds to claim 3, lines 9-10 of the ‘865 patent; “wherein a first memory region …” corresponds to claim 3, lines 10-16 of the ‘865 patent; “monitoring memory bandwidth usages …” corresponds to claim 3, lines 17-19 of the ‘865 patent; “determining to reduce bandwidth penalty…” corresponds to claim 3, lines 20-21 of the ‘865 patent; and “reducing a refresh rate…” corresponds to claim 3, lines 22-24 of the ‘865 patent.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7-9, 11-13, 15-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chun et al. (US 2019/0006001) in view of Henderson et al. (US 2013/0128682).
With respect claim 1, Chun et al. teaches identifying, by a controller coupled to a dynamic memory system via a communication channel (see Fig. 1 and page 3, paragraph 31; controller coupled to DRAM by memory channel), a plurality of memory regions in the dynamic memory system, the plurality of memory regions respectively storing a plurality of different types of data (see page 3, paragraph 30 and 31; data region and parity region), wherein a first memory region in the plurality of memory regions stores data of a first type of data (see page 3, paragraph 30 and page 5, paragraph 50; data region is configured to store user data payloads) different from a second type of data stored in a second memory region (see page 3, paragraph 30 and page 5, paragraph 50; parity region is configured to store parity words).
Even though Chun et al. teaches determining a refresh rate based on a type of data stored in the one or more plurality of region (see page 3, paragraph 32 and page 6, paragraphs 58 and 59; a first refresh rate for data region and a second refresh rate for parity region). Chun et al. does not teach reaching a decision, by the controller, to reduce memory bandwidth used to refresh the dynamic memory system; and in response to the decision, reducing, by the controller, a rate to refresh at least one of the plurality of memory regions, including refreshing the first memory region a first frequency, and refreshing the second memory region at a second frequency different from the first frequency.
However, Henderson et al. teaches reaching a decision, by the controller, to reduce memory bandwidth used to refresh the dynamic memory system (see page 3, paragraphs 24 and 25; low bandwidth refresh is determined); and in response to the decision, reducing, by the controller, a rate to refresh at least one of the plurality of memory regions (see page 3, paragraph 25; refresh time (i.e., rate) is determined and is less than t1 (i.e., with t2 refresh rate is reduced)), including refreshing a first memory region a first frequency (see page 3, paragraph 34 and page 6, paragraph 58; data region is refreshed at a first refresh rate (i.e., frequency)), and refreshing a second memory region at a second frequency different from the first frequency (see page 3, paragraph 34 and page 6, paragraph 59; parity region is refreshed at a second refresh rate (i.e., frequency)).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Chun et al. to include the above mentioned to improve system performance (see Henderson, page 2, paragraph 14).
With respect claim 2, Chun et al. teaches refreshing the one of the plurality of memory regions at a reduced rate (see page 3, paragraph 32; first refresh rate of data region is lower than second refresh rate of parity region (i.e., data region is refreshed at a reduced rate)).
With respect claim 4, Chun et al. teaches wherein each of the plurality of memory regions includes dynamic random access memory (see page 3, paragraph 30; DRAM).
With respect claim 7, Chun et al. teaches wherein the first frequency is lower than the second frequency (see page 3, paragraph 32data region first refresh rate is lower than parity region second refresh rate).
With respect claim 8, Chun et al. teaches wherein the first frequency is below a threshold (see page 6, paragraph 58);
the second frequency is no less than the threshold (see page 6, paragraph 59); and
refreshing the dynamic memory system at the second frequency is sufficient to prevent data corruption (see page 6, paragraph 59; second refresh rate may be a refresh rate that is expected, or has been determined, to result in an acceptable or desired number of memory errors in the parity region… the acceptable or desired number of memory errors may be zero errors); and
refreshing the dynamic memory system at the first frequency is insufficient to prevent data corruption (see page 6, paragraph 58; first refresh rate may be a refresh rate that is expected, or has been determined, to result in tan acceptable or desired number of memory errors in the data region… the acceptable or desired number of memory errors may be maximum or threshold number of errors, which may correspond to a number of memory errors that can be detected or corrected by the error correction scheme).
With respect claim 9, Chun et al. teaches wherein the data of the first type is more error tolerant than the data of the second type (see page 6, paragraphs 58 and 59; first refresh rate may to result in an acceptable or desired number of memory errors in the data region; the acceptable or desired number of memory errors may correspond to a number of memory errors that can be detected or corrected by the error correction scheme… the acceptable or desired number of memory errors for the second refresh rate may be zero errors).
With respect claim 11, Chun et al. teaches partitioning memory in the dynamic memory system into the plurality of regions pre-associated with the plurality of types of data (see page 3 paragraph 30; data region and parity region); and
storing data in the plurality of regions according to types of the data (see page 3, paragraph 30; data is stored in regions according to type of data).
With respect claim 12, Chun et al. teaches a dynamic memory system having a plurality of memory regions respectively storing a plurality of different types of data (see page 3, paragraph 30 and 31; data region and parity region), wherein a first memory region in the plurality of memory regions stores data of a first type of data (see page 3, paragraph 30 and page 5, paragraph 50; data region is configured to store user data payloads) different from a second type of data stored in a second memory region (see page 3, paragraph 30 and page 5, paragraph 50; parity region is configured to store parity words); and
a controller coupled to the dynamic memory system via a communication channel and operatively to (see Fig. 1 and page 3, paragraph 31; controller coupled to DRAM by memory channel).
Even though Chun et al. teaches determining a refresh rate based on a type of data stored in the one or more plurality of region (see page 3, paragraph 32 and page 6, paragraphs 58 and 59; a first refresh rate for data region and a second refresh rate for parity region). Chun et al. does not teach monitor usages of memory access bandwidth of the plurality of memory regions; determine to reduce memory bandwidth used by refreshing the dynamic memory system; and reduce a refresh rate of at least one of the plurality of memory regions, including refreshing the first memory region a first frequency, and refreshing the second memory region at a second frequency different from the first frequency.
However, Henderson et al. teaches monitor usages of memory access bandwidth of the plurality of memory regions (see page 2, paragraph 21, lines 1-10, bandwidth utilization is monitored); determine to reduce memory bandwidth used by refreshing the dynamic memory system (see page 3, paragraphs 24 and 25; low bandwidth refresh is determined); and reduce a refresh rate of at least one of the plurality of memory regions (see page 3, paragraph 25; refresh time (i.e., rate) is determined and is less than t1 (i.e., with t2 refresh rate is reduced)), including refreshing a first memory region a first frequency (see page 3, paragraph 34 and page 6, paragraph 58; data region is refreshed at a first refresh rate (i.e., frequency)), and refreshing a second memory region at a second frequency different from the first frequency (see page 3, paragraph 34 and page 6, paragraph 59; parity region is refreshed at a second refresh rate (i.e., frequency)).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Chun et al. to include the above mentioned to improve system performance (see Henderson, page 2, paragraph 14).
With respect claim 13, Chun et al. teaches wherein each of the plurality of memory regions includes dynamic random access memory (see page 3, paragraph 30; DRAM); and
the controller is further to: refresh the one of the plurality of memory regions at a reduced rate (see page 3, paragraph 32; first refresh rate of data region is lower than second refresh rate of parity region (i.e., data region is refreshed at a reduced rate)).
With respect claim 15, Chun et al. teaches wherein each of the plurality of memory regions includes dynamic random access memory (see page 3, paragraph 30; DRAM).
With respect claim 16, Chun et al. teaches wherein the first frequency is lower than the second frequency (see page 3, paragraph 32data region first refresh rate is lower than parity region second refresh rate).
With respect claim 17, Chun et al. teaches wherein the first frequency is below a threshold; see page 6, paragraph 58);
the second frequency is no less than the threshold (see page 6, paragraph 59); and
refreshing the dynamic memory system at the second frequency is sufficient to prevent data corruption (see page 6, paragraph 59; second refresh rate may be a refresh rate that is expected, or has been determined, to result in an acceptable or desired number of memory errors in the parity region… the acceptable or desired number of memory errors may be zero errors); and
refreshing the dynamic memory system at the first frequency is insufficient to prevent data corruption (see page 6, paragraph 58; first refresh rate may be a refresh rate that is expected, or has been determined, to result in tan acceptable or desired number of memory errors in the data region… the acceptable or desired number of memory errors may be maximum or threshold number of errors, which may correspond to a number of memory errors that can be detected or corrected by the error correction scheme).
With respect claim 18, Chun et al. teaches wherein the data of the first type is more error tolerant than the data of the second type (see page 6, paragraphs 58 and 59; first refresh rate may to result in an acceptable or desired number of memory errors in the data region; the acceptable or desired number of memory errors may correspond to a number of memory errors that can be detected or corrected by the error correction scheme… the acceptable or desired number of memory errors for the second refresh rate may be zero errors).
With respect claim 20, Chun et al. teaches partitioning memory of a dynamic memory system into a plurality of regions pre-associated with a plurality of different types of data (see page 3 paragraph 30; data region and parity region); and
storing data in the plurality of regions according to types of the data (see page 3, paragraph 30; data is stored in regions according to type of data), wherein a first memory region in the plurality of memory regions stores data of a first type of data (see page 3, paragraph 30 and page 5, paragraph 50; data region is configured to store user data payloads) different from a second type of data stored in a second memory region (see page 3, paragraph 30 and page 5, paragraph 50; parity region is configured to store parity words).
Even though Chun et al. teaches determining a refresh rate based on a type of data stored in the one or more plurality of region (see page 3, paragraph 32 and page 6, paragraphs 58 and 59; a first refresh rate for data region and a second refresh rate for parity region). Chun et al. does not teach monitor usages of memory access bandwidth of the plurality of memory regions; determine to reduce memory bandwidth used by refreshing the dynamic memory system; and reduce a refresh rate of at least one of the plurality of memory regions.
However, Henderson et al. teaches monitoring usages of memory access bandwidth of the plurality of memory regions (see page 2, paragraph 21, lines 1-10, bandwidth utilization is monitored); determining to reduce memory bandwidth used by refreshing the dynamic memory system (see page 3, paragraphs 24 and 25; low bandwidth refresh is determined); and reducing a refresh rate of at least one of the plurality of memory (see page 3, paragraph 25; refresh time (i.e., rate) is determined and is less than t1 (i.e., with t2 refresh rate is reduced)).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the storage medium taught by Chun et al. to include the above mentioned to improve system performance (see Henderson, page 2, paragraph 14).
Claims 3 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chun et al. (US 2019/0006001) and Henderson et al. (US 2013/0128682) as applied to claims 1-2 and 12-13 above, and further in view of Longwell et al. (US 6,385,113).
With respect claim 3, Chun et al. does not teach wherein the refreshing is performed by repeating a refreshing operation at a time interval determined by the reduced rate; and the refreshing operation includes: reading data from a memory location; and writing the data back to the memory location.
However, Henderson et al. teaches wherein the refreshing is performed by repeating a refreshing operation at a time interval determined by the reduced rate (see page 3, paragraph 25 and 26; refresh command may be repeated in a loop).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Chun et al. to include the above mentioned to improve system performance (see Henderson, page 2, paragraph 14).
Chun et al. and Henderson et al does not explicitly teach the refreshing operation includes: reading data from a memory location; and writing the data back to the memory location.
However, Longwell et al. teaches the refreshing operation includes: reading data from a memory location; and writing the data back to the memory location (see column 5, lines 33-35; refreshing involves reading a value present in memory cell and then writing it back into the memory cell).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Chun et al. and Henderson et al. to include the above mentioned to reduce power consumption (see Longwell, column 1, lines 43-45 and column 9, lines 1-9).
With respect claim 14, Chun et al. does not teach wherein a refreshing operation is repeated at a time interval determined by the reduced rate; and the refreshing operation includes: reading data from a memory location; and writing the data back to the memory location.
However, Henderson et al. teaches wherein a refreshing operation is repeated at a time interval determined by the reduced rate (see page 3, paragraph 25 and 26; refresh command may be repeated in a loop).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Chun et al. to include the above mentioned to improve system performance (see Henderson, page 2, paragraph 14).
Chun et al. and Henderson et al does not explicitly teach the refreshing operation includes: reading data from a memory location; and writing the data back to the memory location.
However, Longwell et al. teaches the refreshing operation includes: reading data from a memory location; and writing the data back to the memory location (see column 5, lines 33-35; refreshing involves reading a value present in memory cell and then writing it back into the memory cell).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Chun et al. and Henderson et al. to include the above mentioned to reduce power consumption (see Longwell, column 1, lines 43-45 and column 9, lines 1-9).
Claims 10 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chun et al. (US 2019/0006001) and Henderson et al. (US 2013/0128682) as applied to claims 1 and 5-7 above, and further in view of Pattabiraman et al. (US 2011/0231601).
With respect claim 10, Chun et al. and Henderson et al. do not teach wherein the data of the first type represents media for a media player; and the data of the second type contains instructions of applications.
However, Pattabiraman et al. teaches wherein user can create the application code 102 (or modify existing application code) so that it includes designations of at least two types of data… The type-A data may include information used to maintain the order among video frames. The second data may include the video content of the frames themselves (see page 2, paragraph 33)…a refresh control module 404 can configure the memory units such that the first set 112 of memory units is refreshed at a higher rate than the second set 114 of memory units. This implementation corresponds to the case in which the available memory can be partitioned and refreshed at different rates. In other cases, different types of memory units having different inherent characteristics are already provided; the task in this case is to allocate different types of data to the appropriate types of memory units (see page 3, paragraph 44).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the storage medium taught by Chun et al. and Henderson et al. to include the above mentioned to implementing an device in an energy-efficient manner, without substantially degrading overall performance (see Pattabiraman, Abstract, lines 1-4).
With respect claim 19, Chun et al. and Henderson et al. do not teach wherein the data of the first type represents media for a media player; and the data of the second type contains instructions of applications.
However, Pattabiraman et al. teaches wherein user can create the application code 102 (or modify existing application code) so that it includes designations of at least two types of data… The type-A data may include information used to maintain the order among video frames. The second data may include the video content of the frames themselves (see page 2, paragraph 33)…a refresh control module 404 can configure the memory units such that the first set 112 of memory units is refreshed at a higher rate than the second set 114 of memory units. This implementation corresponds to the case in which the available memory can be partitioned and refreshed at different rates. In other cases, different types of memory units having different inherent characteristics are already provided; the task in this case is to allocate different types of data to the appropriate types of memory units (see page 3, paragraph 44).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Chun et al. and Henderson et al. to include the above mentioned to implementing an device in an energy-efficient manner, without substantially degrading overall performance (see Pattabiraman, Abstract, lines 1-4).
Response to Arguments
Applicant's arguments filed 09/23/2024 have been fully considered but they are not persuasive.
Applicant's representative argues, in pages 1-2, that Chun does not teach the limitation " a plurality of memory regions in the dynamic memory system, ..." as recited in claim 1, 12 and 20. Applicant's representative argues that in the claim limitation the memory regions store user data of a first type and second type, and that Chun does not make any distinction as to different types of user data that is stored in the data regions.
In response: The examiner disagrees. The applicant’s arguments are not commensurate with the scope of the claims. The claim limitation as presented do not specify that the different types of data are of any particular data type (i.e., different types of user data) as argued by the applicant's representative, instead the claims specify only that the “memory regions respectively store a plurality of different types of data. Chun et al. teaches storing a user data payload and parity data (i.e., which are different types of data) in a plurality of memory regions (see page 3, paragraph 30 and 31; data region storing user data payloads and parity region storing parity data).
Applicant's representative argues, in page 2, that Chun does not teach the limitation "reducing a rate to refresh based on a type of user data stored in the memory regions" as recited in claims 1, 12 and 20. Applicant's representative argues that Chun merely describes a first refresh rate for the data region 134, and a second refresh rate for parity region 132. Thus, the person of ordinary skill is directed by Chun to use the same refresh rate for the single (or multiple) data regions 134. In other words, because Chun makes no distinction regarding refresh rate for different types of user data.
In response: The examiner disagrees. As stated above, the claim limitation as presented do not specify that the different types of data are of any particular data type (i.e., different types of user data), instead the claims specify only that the “memory regions respectively store a plurality of different types of data. Chun et al. teaches determining a refresh rate based on a type of data stored in the one or more plurality of region (see page 3, paragraph 32 and page 6, paragraphs 58 and 59; a first refresh rate for data region and a second refresh rate for parity region).
Claims 1-4 and 7-20 are still rejected under nonstatutory double patenting rejection.
Conclusion
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/ARACELIS RUIZ/ Primary Examiner, Art Unit 2139
