Patent Application 18206283 - MANAGING POWER FOR SERVERLESS COMPUTING - Rejection

Patent Application 18206283 - MANAGING POWER FOR SERVERLESS COMPUTING

Title: MANAGING POWER FOR SERVERLESS COMPUTING

Application Information

• Invention Title: MANAGING POWER FOR SERVERLESS COMPUTING
• Application Number: 18206283
• Submission Date: 2025-04-07T00:00:00.000Z
• Effective Filing Date: 2023-06-06T00:00:00.000Z
• Filing Date: 2023-06-06T00:00:00.000Z
• National Class: 713
• National Sub-Class: 320000
• Examiner Employee Number: 100100
• Art Unit: 2176
• Tech Center: 2100

Rejection Summary

• 102 Rejections: 0
• 103 Rejections: 7

Cited Patents

The following patents were cited in the rejection:

• US 0212575🔗
• US 0102752🔗
• US 0267833🔗
• US 0239598🔗
• US 0301860🔗
• US 0168170🔗

Office Action Text

    DETAILED ACTION
Notice of Pre-AIA  or AIA  Status
Applicant’s amendment, filed 03/07/2025, for application number 18/206,283, has been received and entered into record. Claims 1, 3-5, 9, 11, 12, 15-17, 19 and 20 have been amended. Claim 10 has been cancelled. Claim 21 has been added. Thus, claims 1-9, 11-21 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Claim Rejections - 35 USC § 103

In the event the determination of the status of the application as subject to AIA  35 U.S.C. 102 and 103 (or as subject to pre-AIA  35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA  to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.  
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

Claims 1, 2, 5, 8, 16, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2020/0301860 A1) in view of Oner (US 8,270,552 B1) in further view of Chen et al. (US 2018/0267833 A1).
Regarding claim 1, Hsu discloses a method, comprising: a processor set (Figure 1, processors p0 – pN), a plurality of functions with a plurality of corresponding frequency levels (Figure 4 shows a plurality of frequency levels for the different processing groups, LP and BP, which handle interrupt requests which corresponds to processor functions) within a serverless computing cluster (“In one embodiment, the system may be part of … a cloud computing system.” Par 41, ll. 7-9 [which may be a serverless computing system]); measuring, by the processor set, a transition latency from an idle state to an active state for the plurality of functions (“The time interval from (T1) when P1 receives the IRQ to (T2) when the ISR is completed is P1′s response time to the interrupt… this response time is a measure of latency of the system.” And “P1 may spend the transition time to wake up from a low-power state,” par 26-27); and dynamically reallocating, by the processor set, at least one core (“the interrupt controller 110 uses a weighted combination of the power factors and performance factors in selecting a processor for handling an incoming interrupt.” Par 39, ll. 32-34 [the controller allocates processors to interrupts based on performance/power factors which include latency and response times]) within the serverless computing cluster. 
However, Hsu does not explicitly teach dynamically measuring latency; determining whether a target response time to perform a service level objective (SLO) is going to be missed; changing a frequency level across the plurality of functions by scaling down in response to a determination that the target response time to perform the SLO is going to be met; and changing the frequency level across the plurality of functions by scaling up in response to a determination that the target response time to perform the SLO is going to be missed. 
In the analogous art of resource management, Oner teaches a method for dynamically measuring latency (The controller 314 then takes another measurement of the lag or read and write pointer difference delta P (block 708). column 9, lines 61-62 [the lag refers to the latency]); determining whether a target response time to perform a service level objective (SLO) is going to be missed (“the controller 314 determines that the lag delta P is less than the threshold I,” column 9, lines 56-57 [that is, determining if the lag is approaching a data overflow/underflow situation, which may correspond to a service level objective]); changing a frequency level across the plurality of functions by scaling down in response to a determination that the target response time to perform the SLO is going to be met (“If, on the other hand, the controller 314 determines that the lag delta P is greater than the threshold I, the controller 314 sends a control signal to the spread-spectrum phase-locked loop 316 to add a negative (-) frequency offset delta f, to the frequency for of the spread clock signal RCLK (block 756).” column 11, lines 16-21 [that is, if the lag is greater than the threshold, the response time is going to be met, and the frequency is reduced]), and changing the frequency level across the plurality of functions by scaling up in response to a determination that the target response time to perform the SLO is going to be missed (“If, on the other hand, the controller 314 determines that the lag delta P is less than the threshold I, the controller 314 sends a control signal to the spread-spectrum phase-locked loop 316 to apply a positive (+) frequency offset delta f, to the frequency for of the spread clock signal RCLK (block 706).” column 9, lines 55-60) [that is, if the lag is less than the threshold, the response time is going to be missed, and the frequency is increased]).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hsu and Oner before him before the effective filing date of the claimed invention to have modified Hsu to incorporate the teachings of Oner to change the frequency based on whether the SLO is going to be met/missed to dynamically adjust the operating frequency of a processor selected for interrupt handling to allow for real-time power and performance optimization. 
However, Hsu and Oner do not explicitly teach wherein the dynamically reallocating the at least one core and changing the frequency level across the plurality of functions by scaling up comprises creating a new container instance for executing the plurality of functions on a different node than a node which includes the at least one core.
In the analogous art, Chen teaches wherein the dynamically reallocating the at least one core and changing the frequency level across the plurality of functions by scaling up comprises creating a new container instance for executing the plurality of functions on a different node than a node which includes the at least one core (“The expansion operation of the virtual machine may include at least one of the following operations: creating an empty virtual machine, booting/enabling a virtual machine and performing software deployment on the created virtual machine,” par 0028 and “Upon receiving the trigger signal sent by the analysis and determination device 404, in step S206, the resource deployment device 406 automatically performs an operation corresponding to the deployment type on the deployment target in the second cloud system in response to the trigger signal.” Par 0031) [the empty VMs may correspond to a new container instance and the second cloud system may correspond to a different node than a node which includes the at least one core].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hsu, Oner and Chen before him before the effective filing date of the claimed invention to have modified Hsu and Oner to incorporate the teachings of Chen to create empty VMs to execute functions on a different cloud system to provide additional computing resources for executing the function to not miss the SLO.

Regarding claim 2, Hsu, Oner and Chen disclose the method of claim 1. Hsu further discloses wherein the target response time comprises a summation of the transition latency for the functions and the measured latency for the functions (“the response time includes the ISR execution time and a transition time (t), where the transition time (t) is the time it takes for P1 to start the ISR execution after it receives the IRQ. For example, P1 may spend the transition time to wake up from a low-power state,” par 27, ll. 1-5 and Figure 3A [Figure 3A, the total response time includes a transition latency for the processor P1 to become active and a measured latency for completing the ISR]). 

Regarding claim 5, Hsu, Oner and Chen disclose the method of claim 1. Hsu further discloses dynamically reallocating the at least one core (“the interrupt controller 110 uses a weighted combination of the power factors and performance factors in selecting a processor for handling an incoming interrupt.” Par 39, ll. 32-34 [the controller allocates processors to interrupts based on performance/power factors which include latency and response times]). Oner further discloses wherein the changing the frequency level across the plurality of functions by scaling up across the plurality of functions further comprises increasing the frequency level (“if the FIFO controller 314 determines that the read pointer crosses the threshold IO, which may mean that the lag of the read pointer to the write pointer is varying between 7 and 17 instead of the normal lag range of 11 to 21, the controller 314 causes the spread-spectrum phase-locked loop 316 to add DC frequency offset to the frequency of the spread clock signal RCLK to attempt to position the lag range to its normal range.” column 8, ll. 28-35 [the frequency is increased to scale up to its normal range]).

Regarding claim 8, Hsu, Oner and Chen disclose the method of claim 1. Hsu further discloses dynamically reallocating the at least one core (“the interrupt controller 110 uses a weighted combination of the power factors and performance factors in selecting a processor for handling an incoming interrupt.” Par 39, ll. 32-34 [the controller allocates processors to interrupts based on performance/power factors which include latency and response times]). Oner further discloses wherein the changing the frequency level across the plurality of functions by scaling down comprises decreasing the frequency level (“if the FIFO controller 314 determines that the read pointer crosses the threshold IU, which may mean that the lag of the read pointer to the write pointer is varying between 15 and 25 instead of the normal lag range of 11 to 21, the controller 314 causes the spread-spectrum phase-locked loop 316 to subtract DC frequency offset to decrease the frequency of the spread clock signal RCLK to attempt to position the lag range to its normal range.” column 8  ll. 51- 58 [the frequency is decreased to scale down to its normal range]). 

Regarding claim 16, Hsu discloses a system (Figure 1, system 100) comprising one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media (“The method 600 may be performed by hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), or a combination of hardware and software (e.g., instructions run on a processing device).” Par 41, ll. 1-4).
The remainder of Claim 16 repeats the same limitations as recited in Claim 1 and 2, and is rejected accordingly. 

Regarding claim 19, Hsu, Oner and Chen disclose the system of claim 16. Claim 19 repeats  the same limitations as recited in claim 5 and is rejected accordingly.

Regarding claim 20, Hsu, Oner and Chen disclose the system of claim 16. Oner further teaches wherein the dynamically reallocating the at least one core and changing the frequency level across the plurality of functions by scaling down comprises decreasing the frequency level to provide just enough computing power to execute the plurality of functions and still meeting the SLO (“if the FIFO controller 314 determines that the read pointer crosses the threshold IU, which may mean that the lag of the read pointer to the write pointer is varying between 15 and 25 instead of the normal lag range of 11 to 21, the controller 314 causes the spread-spectrum phase-locked loop 316 to subtract DC frequency offset to decrease the frequency of the spread clock signal RCLK to attempt to position the lag range to its normal range.” column 8  ll. 51- 58 [the frequency is decreased to scale down to its normal range (indicating that that is the range for “normal lag”) so that the threshold is not crossed; the frequency is not decreased to fall below the normal range]).

Claims 3, 6, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, Oner and Chen, and in further view of Miller (US 2004/0168170 A1).

Regarding claim 3, Hsu, Oner and Chen disclose the method of claim 1. Hsu further discloses a serverless computing cluster (“In one embodiment, the system may be part of … a cloud computing system.” Par 41, ll. 7-9 [which may be a serverless computing system]) and reallocating the at least one core (“the interrupt controller 110 uses a weighted combination of the power factors and performance factors in selecting a processor for handling an incoming interrupt.” Par 39, ll. 32-34 [the controller allocates interrupts to certain processors based on performance/power factors which include latency and response times]). Oner further discloses changing the frequency level across the plurality of functions by scaling up (“If, on the other hand, the controller 314 determines that the lag delta P is greater than the threshold I, the controller 314 sends a control signal to the spread-spectrum phase-locked loop 316 to add a negative (-) frequency offset delta f, to the frequency for of the spread clock signal RCLK (block 756).” column 11, lines 16-21 [that is, if the lag is less than the threshold, the response time is going to be missed, and the frequency is increased]). 
However, Hsu, Oner and Chen do not explicitly teach stealing the at least one core from a second function of a first node and reallocating the at least one core to a first function of the first node.
In the analogous art of resource management, Miller teaches a method that comprises stealing the at least one core from a second function of a first node and reallocating the at least one core to a first function of the first node (“Dynamic processor allocation mechanism 124 is used to reallocate portions of a shared processing resource (e.g., one or more processors 110) from underutilized logical partitions (i.e., those partitions having a relatively lower current utilization of their owned portion of the shared processing resource) to overutilized partitions (i.e., those partitions having a relatively higher current utilization of their owned portion of the shared processing resource).” Par 28, ll. 1-8) [Figure 1 and 2, main memory (120) may be a first node and the partitions (125 and 127) may be a first and second function that each have their own operating system. According to Figure 2, partition 2 requires more processing resources and may steal it from partition 3, which has a lower utilization, thus partition 2 is scaling up processing resources. See paragraphs 44-50].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hsu, Oner, Chen and Miller before him before the effective filing date of the claimed invention to have modified Hsu, Oner and Chen to incorporate the teachings of Miller to reallocate a core to reduce the number of times computational costs are encountered when no action needs to be taken (Miller, par. 0052).

Regarding claim 6, Hsu, Oner and Chen disclose the method of claim 1. Hsu further discloses a serverless computing cluster (“In one embodiment, the system may be part of … a cloud computing system.” Par 41, ll. 7-9) and reallocating the at least one core (“the interrupt controller 110 uses a weighted combination of the power factors and performance factors in selecting a processor for handling an incoming interrupt.” Par 39, ll. 32-34 [the controller allocates interrupts to certain processors based on performance/power factors which include latency and response times]). Oner further discloses changing the frequency level across the plurality of functions by scaling up (“If, on the other hand, the controller 314 determines that the lag delta P is greater than the threshold I, the controller 314 sends a control signal to the spread-spectrum phase-locked loop 316 to add a negative (-) frequency offset delta f, to the frequency for of the spread clock signal RCLK (block 756).” column 11, lines 16-21 [that is, if the lag is less than the threshold, the response time is going to be missed, and the frequency is increased]). 
However, Hsu, Oner and Chen do not explicitly teach lending the at least one core from a first function of a first node and reallocating the at least one core to a second function of the first node.
In the analogous art of resource management, Miller teaches a method that comprises lending the at least one core from a first function of a first node and reallocating the at least one core to a second function of the first node (“Dynamic processor allocation mechanism 124 is used to reallocate portions of a shared processing resource (e.g., one or more processors 110) from underutilized logical partitions (i.e., those partitions having a relatively lower current utilization of their owned portion of the shared processing resource) to overutilized partitions (i.e., those partitions having a relatively higher current utilization of their owned portion of the shared processing resource).” Par 28, ll. 1-8) [Figure 1 and 2, Processor 1 (110) may be a first node and the partitions (125 and 127) may be a first and second function. According to Figure 2, partition 3 has a lower utilization and may donate/lend processing resources to partition 2, which has a higher utilization, thus partition 3 is scaling down processing resources. See paragraphs 44-50].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hsu, Oner, Chen and Miller before him before the effective filing date of the claimed invention to have modified Hsu, Oner and Chen to incorporate the teachings of Miller to reduce the number of times computational costs are encountered when no action needs to be taken (Miller, par 52).

Regarding claims 17 and 18, Hsu, Oner and Chen disclose the system of claim 16. Claims 17 and 18 repeat the same limitations as recited in claim 3 and claim 6 respectively, and are rejected accordingly.

Claims 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, Oner and Chen, and in further view of Kubala et al. (US 7,007,276 B1).

Regarding claim 4, Hsu, Oner and Chen disclose the method of claim 1. Hsu further discloses a serverless computing cluster (“In one embodiment, the system may be part of … a cloud computing system.” Par 41, ll. 7-9 [which may be a serverless computing system]) and reallocating the at least one core (“the interrupt controller 110 uses a weighted combination of the power factors and performance factors in selecting a processor for handling an incoming interrupt.” Par 39, ll. 32-34 [the controller allocates interrupts to certain processors based on performance/power factors which include latency and response times]). Oner further discloses changing the frequency level across the plurality of functions by scaling up (“If, on the other hand, the controller 314 determines that the lag delta P is greater than the threshold I, the controller 314 sends a control signal to the spread-spectrum phase-locked loop 316 to add a negative (-) frequency offset delta f, to the frequency for of the spread clock signal RCLK (block 756).” column 11, lines 16-21 [that is, if the lag is less than the threshold, the response time is going to be missed, and the frequency is increased ]). 
However, Hsu, Oner and Chen do not explicitly teach stealing the at least one core from a second function of a second node and reallocating the at least one core to a first function of a first node.
In the analogous art of resource management, Kubala teaches a method that comprises stealing the at least one core from a second function of a second node and reallocating the at least one core to a first function of a first node (“various physical resources are dynamically redistributed across the logical partitions of a computing environment under direction of one or more workload managers” column 5, ll. 61-64) [The computing environment may have two central processor complexes, CPC, each having a plurality of logical partitions as shown in Figure 1 b. As shown in the figure and disclosed in column 5, lines 61-64, physical resources are reallocated between different logical partitions. The resources of different workloads are redistributed to other partitions of other workloads.].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hsu, Oner, Chen and Kubala before him before the effective filing date of the claimed invention to have modified Hsu, Oner and Chen to incorporate the teachings of Kubala to steal the at least one core from a second function of a second node and reallocate the at least one core to a first function of a first node to balance the workload of all nodes in a computing environment (Kubala, column 3, ll. 64-65).

Regarding claim 7, Hsu, Oner and Chen disclose the method of claim 1. Hsu further discloses a serverless computing cluster (“In one embodiment, the system may be part of … a cloud computing system.” Par 41, ll. 7-9) and reallocating the at least one core (“the interrupt controller 110 uses a weighted combination of the power factors and performance factors in selecting a processor for handling an incoming interrupt.” Par 39, ll. 32-34 [the controller allocates interrupts to certain processors based on performance/power factors which include latency and response times]). Oner further discloses changing the frequency level across the plurality of functions by scaling up (“If, on the other hand, the controller 314 determines that the lag delta P is greater than the threshold I, the controller 314 sends a control signal to the spread-spectrum phase-locked loop 316 to add a negative (-) frequency offset delta f, to the frequency for of the spread clock signal RCLK (block 756).” column 11, lines 16-21 [that is, if the lag is less than the threshold, the response time is going to be missed, and the frequency is increased]). 
However, Hsu, Oner and Chen do not explicitly teach lending the at least one core from a first function of a first node and reallocating the at least one core to a second function of a second node.
In the analogous art of resource management, Kubala teaches a method that comprises lending the at least one core from a first function of a first node and reallocating the at least one core to a second function of a second node (“various physical resources are dynamically redistributed across the logical partitions of a computing environment under direction of one or more workload managers” column 5, ll. 61-64) [The computing environment may have two central processor complexes, CPC, each having a plurality of logical partitions as shown in Figure 1 b. As shown in the figure and disclosed in column 5, lines 61-64, physical resources are reallocated between different logical partitions. The resources of different workloads are redistributed across logical partitions to other workloads.].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hsu, Oner, Chen and Kubala before him before the effective filing date of the claimed invention to have modified Hsu, Oner and Chen to incorporate the teachings of Kubala to lend the at least one core from a first function of a first node and reallocate the at least one core to a second function of a second node to balance the workload of all nodes in a computing environment (Kubala, column 3, ll. 64-65).

Claims 9, 10, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Wang (US 2017/0212575 A1) and Chen.

Regarding claim 9, Hsu discloses a computer program product (a multi-processor system, Fig 1) comprising one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, the program instructions executable to (“The method 600 may be performed by hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), or a combination of hardware and software (e.g., instructions run on a processing device).” Par 41, ll. 1-4): measure power consumption needed to execute a function with a predetermined core frequency (“the power factor takes into account the energy efficiency of each processor, such as the power consumption at a present operating frequency of each processor,” par 38, ll. 15-18) within a serverless computing cluster (“In one embodiment, the system may be part of … a cloud computing system.” Par 41, ll. 7-9 [which may be a serverless computing system]); and store the power consumption needed to execute the function with the predetermined core frequency in at least one lookup table (“the hint logic 120 in FIG. 1 and FIG. 2 may store a per-processor DVFS power consumption table with respect to DVFS operating frequency steps,” par 38, ll. 19-21).
However, Hsu does not explicitly teach a computer product configured to determine that a power budget is going to be exceeded based on a number of cores and a next frequency level using the at least one lookup table; and reduce a frequency, in response to a determination that the power budget is going to be exceeded, wherein the reducing the frequency comprises creating a new container instance for executing the function on a different node than a node which includes the predetermined core.
In the analogous art of resource management, Wang teaches a computer product (multi-core processor system, Fig. 1) configured to determine that a power budget is going to be exceeded based on a number of cores and a next frequency level using the at least one lookup table (“the multi-core processor system 12 includes “Big” processor cores, “Middle” processor cores, and “Little” processor cores using individual buck voltages, the core combination setting (e.g., an on-line core combination) and a frequency setting (e.g., a current frequency) of each processor core selected by the core combination setting are referenced by the power management controller 102 to search an unexpanded power table for power values associated with online processor cores, and then … calculate the current power of the online processor cores.” par 39, ll. 3-14 and “The start points of the partial delta power table and the partial delta efficiency table selected by the power management controller 102 at step 304 are initialized on the basis of original/aligned frequencies of core combinations,” par 42, ll. 4-9 and  “the currently selected frequency settings of core combinations associated with clusters are initialized on the basis of original/aligned frequencies of the core combinations associated with the clusters into which the processor cores of the multi-core processor system 12 are categorized.” Par 42, ll. 11-16 and Figures 3-5 [the tables are initialized with original/predefined frequencies and are aligned with core combinations (i.e., Big, Middle, Little) which correspond to on-line, active/working, cores. It uses the current frequencies (which may be considered a next frequency with respect to the original frequencies stored in the table; see Figure 5 for the operating performance point (OPP) transitions which are associated with a frequency and a voltage level). The delta power budget is the power budget minus the current power, and the current power is calculated according to information from the system settings INFsys. The current power is an expected power value of the cores based on the current settings (see paragraph 39). Step 312 determines, using the current power, if the power budget will be exceeded.]); and perform at least one action of reducing a frequency, reducing the number of cores and turning off at least one core of the cores in response to a determination that the power budget is going to be exceeded (“When the delta power budget is a negative value, it means there is a demand for a lower frequency and/or fewer online cores. Hence, the flow proceeds with step 316 to decrease the frequency limit LFREG (or decrease the frequency limit LFREG and the online core limit LCORE) for one or more clusters. At step 318, the power management controller 102 outputs the final frequency limit LFREG (or the final frequency limit LFREG and online core limit LCORE) found by the power budget allocation process for each cluster.”, par 41, ll. 10-24 and Figures 3-4 [The delta power budget is the power budget minus the current power, and the current power is calculated according to information from the system settings INFsys. The current power is an expected power value of the cores based on the current settings (see paragraph 39). Thus, step 312 determines, using the current power, if the power budget will be exceeded.]).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hsu and Wang before him before the effective filing date of the claimed invention to have modified Hsu to incorporate the teachings of Wang to determine that a power budget is going to be exceeded based on a number of cores and a next frequency level using the at least one lookup table to achieve higher computing power by using pre-characterized data about the processors’ power consumption and avoid temperature overshoot in electronic devices (Wang, paragraph 3).
However, Hsu and Wang do not explicitly teach wherein the reducing the frequency comprises creating a new container instance for executing the function on a different node than a node which includes the predetermined core.
In the analogous art, Chen teaches creating a new container instance for executing the function on a different node than a node which includes the predetermined core (“The expansion operation of the virtual machine may include at least one of the following operations: creating an empty virtual machine, booting/enabling a virtual machine and performing software deployment on the created virtual machine,” par 0028 and “Upon receiving the trigger signal sent by the analysis and determination device 404, in step S206, the resource deployment device 406 automatically performs an operation corresponding to the deployment type on the deployment target in the second cloud system in response to the trigger signal.” Par 0031) [the empty VMs may correspond to a new container instance and the second cloud system may correspond to a different node than a node which includes the predetermined core].
It would have been obvious to one of ordinary skill in the art, having the teachings of Hsu, Wang and Chen before him before the effective filing date of the claimed invention to have modified Hsu and Wang to incorporate the teachings of Chen to create empty VMs to execute functions on a different cloud system to provide additional computing resources for executing the function to not miss the SLO.

Regarding claim 11, Hsu, Wang and Chen disclose the computer program product of claim 9. Wang further discloses wherein the performing the at least one action reduces the number of cores in response to the determination that the power budget is going to be exceeded (“decrease … the online core limit LCORE,” par 41, ll. 18 and Figure 3 [When the delta power budget is a negative value, the flow proceeds with step 316. Reducing the number of cores corresponds to reducing the number of online/active cores, which “decreasing the online core limit” achieves]).

Regarding claim 12, Hsu, Wang and Chen disclose the computer program product of claim 9. Wang further discloses herein the performing the at least one action turns off at least one core of the cores in response to the determination that the power budget is going to be exceeded (“If the candidate OPP transition with the minimum delta power efficiency value is the OPP transition “4-OFF”, the power management controller 102 changes a currently selected online core setting of a specific cluster with the minimum delta power efficiency value such that an online core limit (i.e., an online core number) of the specific cluster is decreased (Steps 404 and 406),” par 46, ll. 1-7 and Figures 3 and 4 [when the delta power budget is a negative value, the flow proceeds with step 316; the online core limit being decreased may correspond to turning off a number of active cores]).

Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu, Wang and Chen, and in further view of Varma (US 2017/0102752 A1).

Regarding claim 13, Hsu, Wang and Chen disclose the computer program product of claim 12. However, Hsu, Wang and Chen do not explicitly teach wherein the turning off at least one core comprises putting the at least one core in a deep sleep mode.
In the analogous art of resource management, Varma teaches a computer program product wherein the turning off at least one core comprises putting the at least one core in a deep sleep mode (“In an example, the method further comprises instructing a power delivery circuit associated with the at least one core to turn off power to the at least one core, where the low power state comprises a deep low power state.” Par 82, ll. 1-4 [one example of a deep low power state may be a C6 state in which power to a core is reduced to a zero or negligible amount, see paragraph 24]).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hsu, Wang, and Chen and Varma before him before the effective filing date of the claimed invention to have modified Hsu, Wang and Chen to incorporate the teachings of Varma to put inactive cores to deep sleep to achieve better energy efficiency and energy conservation in integrated circuits (Varma, par 23).

Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu, Wang and Chen, and in further view of Oner and in even further view of Kumar (US 2022/0239598 A1). 

Regarding claim 14, Hsu, Wang and Chen disclose the computer program product of claim 9. Hsu further discloses a serverless computing cluster (“In one embodiment, the system may be part of … a cloud computing system.” Par 41, ll. 7-9). 
However, Hsu, Wang and Chen do not explicitly teach determining whether a target response time to perform a service level objective (SLO) is going to be missed, the determining the target response time to perform the SLO is going to be missed is based on a tail latency for executing the function, and the tail latency represents a predetermined upper percentile of the target response time.
In the analogous art of resource management, Oner teaches determining whether a target response time to perform a service level objective (SLO) is going to be missed (“the controller 314 determines that the lag delta P is less than the threshold I,” column 9, lines 56-57 [that is, determining if the lag is approaching a data overflow/underflow situation, which may correspond to a service level objective]).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hsu, Wang, Chen and Oner before him before the effective filing date of the claimed invention to have modified Hsu and Wang to incorporate the teachings of Oner to determine whether a SLO is going to be missed to prevent data overflow or underflow of the FIFO memory (Oner, column 2, ll. 3-4).
However, Hsu, Wang, Chen and Oner do not teach the determining the target response time to perform the SLO is going to be missed is based on a tail latency for executing the function, and the tail latency represents a predetermined upper percentile of the target response time. In the analogous art of resource management, Kumar teaches a computer program product configured to determine the target response time to perform the SLO is going to be missed  based on a tail latency for executing the function (Algorithm 1, see paragraphs 57-59 [the algorithm uses the tail latency when it will be missed, corresponding to executing the remote procedure calls (RPCs), to adjust a probability measure, which is used to downgrade the RPCs.), and the tail latency represents a predetermined upper percentile of the target response time (“tail specified at a given percentile (say 99.9th-p),” par 46).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hsu, Wang, Chen, Oner and Kumar before him before the effective filing date of the claimed invention to have modified Hsu, Wang, Chen and Oner to incorporate the teachings of Kumar to manage a traffic-mix across QoS level to avoid priority inversion of RPC latencies (Kumar, paragraph 6).

Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu, Wang and Chen, and in further view of Oner. 

Regarding claim 15, Hsu, Wang and Chen disclose the computer program product of claim 9. Wang further discloses wherein the next frequency level is different from the predetermined core frequency (Figures 3-5; the tables are initialized with original/predefined frequencies and are aligned with core combinations. The current frequencies may be considered a next frequency which is different from the original/predetermined frequencies based on power budget constraints. See paragraphs 40-44]). 
However, Hsu, Wang and Chen do not explicitly teach wherein the frequency level is a frequency level which ensures that the target response time to perform the SLO is going to be met.
In the analogous art of resource management, Oner teaches a computer program product wherein the frequency level is a frequency level which ensures that the target response time to perform the SLO is going to be met (“For example, if the FIFO controller 314 determines that the read pointer crosses the threshold IO, which may mean that the lag of the read pointer to the write pointer is varying between 7 and 17 instead of the normal lag range of 11 to 21, the controller 314 causes the spread-spectrum phase-locked loop 316 to add DC frequency offset to the frequency of the spread clock signal RCLK to attempt to position the lag range to its normal range.” Column 8, ll. 28-41 [the reduction (or addition in another embodiment based on the threshold) reaches a next frequency level that ensures that the lag is within the threshold and will prevent any data underflow/overflow situations (which may correspond to a response time meeting an SLO)]).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hsu, Wang, Chen and Oner before him before the effective filing date of the claimed invention to have modified Hsu, Wang and Chen to incorporate the teachings of Oner to determine whether a SLO is going to be met to prevent data overflow or underflow of the FIFO memory (Oner, column 2, ll. 3-4).

Allowable Subject Matter

Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.

Response to Arguments

Applicant’s arguments, see pages 10-12, filed 03/07/2025, with respect to the rejection(s) of claim(s) 1, 9, and 16 under 35 U.S.C. 103 have been fully considered and are persuasive.  Therefore, the rejection has been withdrawn.  However, upon further consideration, a new ground(s) of rejection is made in view of Chen et al. (US 2018/0267833 A1). Chen explicitly teaches the creation of a new container instance for executing functions in a different node than a node which includes the at least one or predetermined core.

Conclusion

THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.

Any inquiry concerning this communication or earlier communications from the examiner should be directed to AYMAN FATIMA whose telephone number is (571)270-0830. The examiner can normally be reached M to Fri EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on (571) 270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.




/AYMAN FATIMA/Examiner, Art Unit 2176   

/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176